502-DPKLF [IDT]
Clock Generator, 190MHz, CMOS, DIE;
| 型号： | 502-DPKLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 190MHz, CMOS, DIE 时钟 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
LOCO™ PLL CLOCK MULTIPLIER
ICS502
Description
Features
TM
The ICS502 LOCO is the most cost effective way to
• Packaged as 8-pin SOIC or die
• Pb (lead) free package
• IDT’s lowest cost PLL clock
• Zero ppm multiplication error
• Easy to cascade with ICS5xx series
• Input crystal frequency of 5 – 27 MHz
• Input clock frequency of 2 – 50 MHz
• Output clock frequencies up to 190 MHz
• Low jitter – 50 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55 up to 160 MHz
• Operating voltages of 3.0 to 5.5 V
• 25 mA drive capability at TTL levels
• Industrial temperature version available
• Advanced, low-power CMOS process
generate a high-quality, high-frequency clock output and a
reference from a lower frequency crystal or clock input. The
name LOCO stands for Low Cost Oscillator, as it is
designed to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques, the
device uses a standard fundamental mode, inexpensive
crystal to produce output clocks up to 160 MHz.
Stored in the chip’s ROM is the ability to generate six
different multiplication factors, allowing one chip to output
many common frequencies (see table on page 2).
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed. For
applications which require defined input to output skew, use
the ICS570B.
Block Diagram
VDD
PLL Clock
CLK
Multiplier
Circuitry and
ROM
2
S1, S0
X1/ICLK
Crystal or
Crystal
Clock input
OScillator
REF
X2
GND
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Clock Decoding Table (MHz)
S1 S0
CLK
x2
0
0
0
1
0
1
0
1
X1/ICLK
VDD
8
7
6
5
1
2
3
4
X2
x5
S1
M
M
1
x3
x3.33
x4
GND
S0
REF
CLK
1
x2.5
8 Pin (150 mil) SOIC
Minimum input frequency for all selections is per table on
page 3.
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
20
10
25
10
30
10
32
16
33.33
10
37.5
15
40
20
48
16
50
20
54
60
20
Input
13.5
1, 0
Selection (S1, S0)
0, 0
1, 1
M, 0
0, 0
M, 1
1, 1
0, 0
M, 0
1, 1
M, 0
Output
64
16
66.66
20
72
24
75
15
80
20
81
27
90
27
100
20
108
27
120
24
135
27
Input
Selection (S1, S0)
1, 0
M, 1
M, 0
0, 1
1, 0
M, 0
M, 1
0, 1
1, 0
0, 1
0, 1
Pin Descriptions
Pin
Number
Pin
Pin
Type
Pin Description
Name
XI/ICLK
VDD
GND
REF
CLK
S0
1
2
3
4
5
6
7
8
Input
Crystal connection or clock input.
Power Connect to +3.3 V or +5 V.
Power Connect to ground.
Output Buffered crystal oscillator output clock.
Output Clock output per table above.
Input
Input
Input
Select 0 for output clock. Connect to GND or VDD.
S1
Select 1 for output clock. Connect to GND or VDD or float.
Crystal connection. Leave unconnected for clock input.
X2
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Crystal Load Capacitors
External Components
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors, if needed, must be connected from each of the
pins X1 and X2 to ground.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS502
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND. It must be connected close to the
ICS502 to minimize lead inductance. No external power
supply filtering is required for the ICS502.
Series Termination Resistor
The value (in pF) of these crystal caps should equal (CL -12
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 8 pF [(16-12) x 2] = 8.
A 33Ωterminating resistor can be used next to the CLK pin.
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS502. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
-40 to +85° C
0 to +70° C
Ambient Operating Temperature (industrial)
Ambient Operating Temperature (commercial)
Storage Temperature
-65 to +150° C
260°C
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
0
–
–
-40
+3
+85
° C
+5.5
V
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=5.0 V 5% , Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol Conditions
Min.
3
Typ.
Max.
Units
Operating Voltage
VDD
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
VIH
VIL
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
(VDD/2)+1
V
VIH
VIL
2
V
Input Low Voltage
V
Input High Voltage
VIH
VIM
VIL
VDD-0.5
V
Input Mid Voltage
S1
VDD/2
20
V
Input Low Voltage
S0, S1
0.5
0.4
V
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = -25 mA
IOL = 25 mA
2.4
V
V
IDD Operating Supply Current, 20
MHz crystal
No load,
100 MHz
mA
Short Circuit Current
CLK output
Pin 7
+70
270
4
mA
kΩ
pF
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Pins 4, 6, 7
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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CLOCK MULTIPLIER
AC Electrical Characteristics
VDD = 5.0 V 5%, Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
FIN
Conditions
Min. Typ. Max. Units
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5V
Output Frequency, VDD = 3.0 to 3.6V
Output Frequency, VDD = 4.5 to 5.5V
Output Frequency, VDD = 3.0 to 3.6V
Output Clock Rise Time
5
27
50
MHz
MHz
MHz
MHz
MHz
MHz
ns
FIN
2
FOUT
0 to +70° C
14
14
14
14
160
120
190
140
-40 to +85° C
+25° C
FOUT
+25° C
tOR
tOF
tOD
0.8 to 2.0 V
2.0 to 8.0V
1.5V, up to 160 MHz
1
1
Output Clock Fall Time
ns
Output Clock Duty Cycle
45
10
49-51
55
%
PLL Bandwidth
kHz
ns
Output Enable Time, OE high to
output on
50
50
Output Disable Time, OE low to
tri-state
ns
Deviation from mean
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
tja
tjs
+70
25
ps
ps
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
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LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
Min Max
0.0532 0.0688
0.0040 0.0098
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
A
A1
B
C
D
E
e
1.35
1.10
0.33
0.19
4.80
3.80
0.013
0.0075 0.0098
.1890 .1968
0.020
Index
Area
E
H
0.1497 0.1574
0.050 Basic
1.27 Basic
H
h
L
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
0.2284 0.2440
0.010
0.016
0°
0.020
0.050
8°
Pin 1
a
D
h x 450
A
Q
c
e
b
Ordering Information
Part / Order Number
502MLF
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
502MLF
502MLF
502MILF
502MILF
-
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
502MLFT
502MILF
Tape and Reel
Tubes
502MILFT
502-DWF
502-DPK
Tape and Reel
Die on uncut, probed wafers
Tested die in waffle pack
-
Parts that are ordered with an “LF” suffix to the part number are the Pb-free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
6
ICS502
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ICS502
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
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www.IDT.com
For Sales
800-345-7015
For Tech Support
www.idt.com/go/clockhelp
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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