554-01DWF [IDT]
Clock Generator, 0.032768MHz, CMOS, DIE;
| 型号： | 554-01DWF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 0.032768MHz, CMOS, DIE |
| 文件： | 总7页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
CLOCK DIVIDER
ICS544-01
Description
Features
The ICS544-01 is crystal oscillator module IC with
divide by 512 frequency output. It employs a 16.777216
MHz fundamental frequency crystal source oscillator to
generate 32.768 kHz output crystal oscillator output. In
addition a divide by 256, 64 and 32 options are also
provided through select pins. The chip has an OE pin
that tri-states the output and stops the oscillator circuits.
• Packaged in 8-pin SOIC
• Pb-free package
• IDT’s lowest cost clock divider
• Easy to use with other generators and buffers
• Input crystal at 16.777216MHz
• Output clock duty cycle of 45/55
• Output Enable
• Advanced, low-power CMOS process
• Operating voltage of 2.25 V to 3.6 V
• Does not degrade phase noise - no PLL
• Available in industrial temperature range
The ICS544-01 is a member of IDT’s ClockBlocksTM
family of clock building blocks. See the ICS541 and
ICS542 for other clock dividers, and the ICS501, 502,
511, 512, and 525 for clock multipliers.
Block Diagram
VDD
S1, S0 (1:0)
Divider and
Selection
CLK1
Circuitry
/32, /64
/256, /512,
X1
X2
16.777216MHz
crystal input
Optional tuning
capacitors
OE
GND
IDT® CLOCK DIVIDER
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CLOCK DIVIDER
CLOCK DIVIDER
Pin Assignment
Clock Divider Table
S1 S0
CLK
X1/ICLK
X2
8
7
6
5
1
2
3
4
S1
0
0
1
1
0
1
0
1
Input/32
Input/64
Input/256
Input/512
VDD
OE
GND
S0
CLK
0 = connect directly to ground
1 = connect directly to VDD
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Pin
Type
Pin Description
Name
X1/ICLK
X2
1
2
3
XI
Crystal input.
Xo
Connect to crystal for crystal input and leave open for clock input.
Connect to ground.
GND
Power
Select 0 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
4
5
6
7
8
S0
CLK
OE
Input
Output Clock output per table above. Internal Pull down resistor.
Output Enable.Tri-states output clock when low. Also shuts down the oscillator
circuit. Internal pull-up resistor. OE=1 normal operation.
Input
VDD
S1
Power
Input
Connect to 2.25 V to 3.6 V.
Select 1 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
External Components
Series Termination Resistor
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS544-01 must be isolated from system power supply
noise to perform optimally.
Ω
Ω
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Ω
On chip capacitors
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C -12)*2 in this equation,
L
C =crystal load capacitance in pf. For example, for a
L
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
IDT® CLOCK DIVIDER
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CLOCK DIVIDER
CLOCK DIVIDER
2) To minimize EMI, the 33Ωseries termination resistor
PCB Layout Recommendations
(if needed) should be placed close to the clock output.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS544-01. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the VDD
pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS544-01. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
+85
3.6
Units
° C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
0
-40
2.25
° C
V
IDT® CLOCK DIVIDER
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CLOCK DIVIDER
DC Electrical Characteristics
Unless stated otherwise, VDD = 2.25 V to 3.6 V, C =15pF 5%, Ambient Temperature -40°C to +85°C
L
Parameter
Operating Voltage
Symbol
Conditions
Min.
2.25
Typ.
Max.
Units
V
VDD
3.6
Input High Voltage
V
S0, S1, OE, ICLK
S0, S1, OE, ICLK
0.7VDD
V
IH
Input Low Voltage
V
0.3VDD
V
IL
Output High Voltage
Output Low Voltage
Operating Supply Current
Operating Supply Current
Standby Current
V
I
I
= -2 mA
= 2 mA
VDD-0.4 VDD-0.15
V
OH
OH
OL
V
0.15
0.3
0.4
0.6
1
V
OL
DD
DD
I
I
VDD =2.25 V - 2.75 V
VDD= 2.75 V - 3.6 V
OE=0
mA
mA
ua
mA
pF
Ω
0.5
I
10
SB
OS
Short Circuit Current
Input Capacitance
I
40
4
C
Z
S0, S1, OE
at VDD/2
IN
O
Nominal Output Impedance
Internal Pull-up Resistor
20
Rpup
OE, S1, S0
420
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDD = 2.25 V to 3.6 V 5%, C =15pF 5%, Ambient Temp -40° C to +85°C
L
Parameter
Input Frequency, clock input
Output Rise Time
Symbol
Conditions
Min.
Typ.
16.777216
0.2
Max.
Units
MHz
μs
VDD = 3.3 V
0
t
0.1VDD to 0.9VDD
0.9VDD to 0.1VDD
at VDD/2
1
1
OR
Output Fall Time
t
0.2
μs
OF
Duty Cycle
45
49 to 51
55
2
%
Output Enable Delay Time
t
OE going high to CLK
output valid
μs
OE
Output Disable Delay Time
t
OE going low to CLK
output invalid
2
μs
OD
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
IDT® CLOCK DIVIDER
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CLOCK DIVIDER
CLOCK DIVIDER
Marking Diagram (ICS554M-01LF)
Marking Diagram (ICS554MI-01LF)
8
5
8
5
554M01LF
######
554MI01L
######
YYWW
YYWW
1
4
1
4
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “L” or “LF” denotes Pb (lead) free package.
4. “I” denotes industrial temperature range.
5. Bottom Marking: (origin)
Origin = country of origin if not USA.
IDT® CLOCK DIVIDER
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CLOCK DIVIDER
CLOCK DIVIDER
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0688
.0098
.020
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
0.25
0.40
0°
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
544M-01LF
Marking
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
544M01LF
544M01LF
544MI01L
544MI01L
544M-01LFT
544MI-01LF
544MI-01LFT
Tape and Reel
Tubes
Tape and Reel
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
IDT® CLOCK DIVIDER
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ICS544-01
REV B 051810
ICS544-01
CLOCK DIVIDER
CLOCK DIVIDER
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