5991A-5JI8 [IDT]
Low Skew Clock Driver, PQCC32;
| 型号： | 5991A-5JI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, PQCC32 |
| 文件： | 总8页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT5991A
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
DESCRIPTION:
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 100MHz
• 2x, 4x, 1/2, and 1/4 outputs
The IDT5991A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5991A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The IDT5991A maintains Cypress CY7B991 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B991
compatibility). However, if GND/sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
• 5V with TTL outputs
• 3 skew grades:
IDT5991A-2: tSKEW0<250ps
IDT5991A-5: tSKEW0<500ps
IDT5991A-7: tSKEW0<750ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA IOL high drive outputs
• Low Jitter: <200ps peak-to-peak
Furthermore, when the VCCQ/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B991 com-
patibility). When VCCQ/PE is held low, all the outputs are synchronized
with the negative edge of REF.
• Outputs drive 50Ω terminated lines
• Pin-compatible with Cypress CY7B991
• Available in PLCC Package
FUNCTIONALBLOCKDIAGRAM
GND/sOE
1Q0
Skew
Select
1Q1
3
3
3
1F1:0
2F1:0
3F1:0
4F1:0
VCCQ/PE
2Q0
2Q1
Skew
Select
3
REF
PLL
FB
3Q0
3Q1
Skew
Select
3
3
3
3
FS
4Q0
4Q1
Skew
Select
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2008
1
c
2006 Integrated Device Technology, Inc.
DSC 5843/4
IDT5991A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Supply Voltage to Ground
DC Input Voltage
Max
Unit
V
–0.5 to +7
–0.5 to +7
150
VI
V
4
3
2
1
32 31 30
TJ
Junction Temperature
Storage Temperature
° C
° C
3F1
4F0
5
29
28
27
26
25
24
23
22
21
2F0
TSTG
–65 to +150
6
GND/sOE
1F1
NOTE:
4F1
7
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
VCCQ/PE
8
1F0
VCCN
VCCN
4Q1
9
10
11
12
13
1Q0
4Q0
1Q1
GND
GND
GND
GND
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
14 15 16 17 18 19 20
Parameter
Description
Typ.
Max.
Unit
CIN
InputCapacitance
5
7
pF
NOTE:
PLCC
TOP VIEW
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PINDESCRIPTION
Pin Name
REF
Type
IN
Description
ReferenceClockInput
FeedbackInput
FB
IN
TEST(1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
SummaryTable)remainineffect. SetLOWfornormaloperation.
GND/sOE(1)
VCCQ/PE
IN
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
thefeedbacksignaltomaintainphaselock. WhenTESTisheldatMIDlevelandGND/sOEisHIGH,thenF[1:0]pinsactasoutputdisable
controls for individual banks when nF[1:0] = LL. Set GND/sOELOW for normal operation.
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthe
referenceclock.
nF[1:0]
FS
IN
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions
IN
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeePLLProgrammableSkewRange.)
Fourbanksoftwooutputswithprogrammableskew
nQ[1:0]
VCCN
VCCQ
GND
OUT
PWR
PWR
PWR
Powersupplyforoutputbuffers
Powersupplyforphaselockedloopandotherinternalcircuitry
Ground
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[1:0] = LL.
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
for PCB trace delays, backplane propagation delays or to accommodate are used, they are intended for but not restricted to hard-wiring. Undriven
requirements for special timing relationships between clocked compo- 3-level inputs default to the MID level. Where programmable skew is
nents. Skew is selectable as a multiple of a time unit tU which is of the not a requirement, the control pins can be left open for the zero skew
order of a nanosecond (see PLL Programmable Skew Range and Resolution default setting. The Control Summary Table shows how to select specific
Table). There are nine skew configurations available for each output skew taps by using the nF1:0 control pins.
pair. These configurations are chosen by the nF1:0 control pins. In order
2
IDT5991A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
EXTERNALFEEDBACK
By providing external feedback, the IDT5991A gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PLLPROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE
FS = LOW
1/(44 x FNOM)
15 to 35MHz
FS = MID
1/(26 x FNOM)
25 to 60MHz
FS = HIGH
1/(16 x FNOM)
40 to 100MHz
Comments
TimingUnitCalculation(tU)
VCOFrequencyRange(FNOM)(1,2)
SkewAdjustmentRange(3)
MaxAdjustment:
9.09ns
49ꢀ
9.23ns
83ꢀ
9.38ns
135ꢀ
ns
PhaseDegrees
ꢁ of Cycle Time
14ꢁ
23ꢁ
37ꢁ
Example 1, FNOM = 15MHz
Example 2, FNOM = 25MHz
Example 3, FNOM = 30MHz
Example 4, FNOM = 40MHz
Example 5, FNOM = 50MHz
Example 6, FNOM = 80MHz
tU = 1.52ns
tU = 0.91ns
tU = 0.76ns
—
—
—
tU = 1.54ns
tU = 1.28ns
tU = 0.96ns
tU = 0.77ns
—
—
—
tU = 1.56ns
tU = 1.25ns
tU = 0.78ns
—
—
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where 6tU skew adjustment is possible and at the lowest FNOM value.
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS
nF1:0
LL(1)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)
Divide by 2
–6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
M H
HL
Zero Skew
1tU
Zero Skew
2tU
Zero Skew
2tU
2tU
4tU
4tU
H M
H H
3tU
6tU
6tU
Inverted(2)
4tU
Divide by 4
NOTES:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.
2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ/PE = LOW.
3
IDT5991A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
RECOMMENDEDOPERATINGRANGE
IDT5991A-5,-7
(Industrial)
IDT5991A-2
(Commercial)
Symbol
VCC
Description
Min.
Max.
5.5
Min.
Max.
5.25
+70
Unit
V
Power Supply Voltage
AmbientOperatingTemperature
4.5
-40
4.75
0
TA
+85
° C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
Min.
Max.
Unit
V
VIH
Input HIGH Voltage
2
—
VIL
InputLOWVoltage
—
0.8
V
VIHH
VIMM
VILL
IIN
Input HIGH Voltage(1)
InputMIDVoltage(1)
InputLOWVoltage(1)
InputLeakageCurrent
(REF, FB Inputs Only)
VCC
−
−
1
—
V
3-Level Inputs Only
VCC/2
0.5
VCC/2+0.5
V
3-Level Inputs Only
—
1
5
V
VIN = VCC or GND
—
µ A
VCC = Max.
VIN = VCC
HIGH Level
MID Level
LOW Level
—
—
—
—
—
2.4
—
—
—
200
50
I3
3-Level Input DC Current (TEST, FS, nF1:0)
VIN = VCC/2
µ A
VIN = GND
200
100
100
—
IPU
IPD
Input Pull-Up Current (VCCQ/PE)
VCC = Max., VIN = GND
VCC = Max., VIN = VCC
µ A
µ A
V
InputPull-DownCurrent(GND/sOE
)
VOH
Output HIGH Voltage
VCC = Min., IOH =
VCC = Min., IOH =
−
−
16mA
40mA
—
VOL
IOS
OutputLOWVoltage
OutputShortCircuitCurrent(2)
VCC = Min., IOL = 46mA
VCC = Max., VO = GND
0.45
V
−250
mA
NOTES:
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
2. This is to be measured at 25°C with 10:1 duty cycle, one output at a time, and one second maximum.
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
VCC = Max., TEST = MID, REF = LOW,
GND/sOE=LOW,Alloutputsunloaded
VCC = Max., VIN = 3.4V
Typ.(2)
Max.
Unit
ICCQ
Quiescent Power Supply Current
10
40
mA
Δ
ICC
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
TotalPowerSupplyCurrent
0.4
100
43
1.5
160
—
mA
ICCD
ITOT
VCC = Max., CL = 0pF
μ
A/MHz
VCC = 5V, FREF = 20MHz, CL = 240pF(1)
VCC = 5V, FREF = 33MHz, CL = 240pF(1)
VCC = 5V, FREF = 66MHz, CL = 240pF(1)
63
—
mA
117
—
NOTE:
1. For eight outputs, each loaded with 30pF.
4
IDT5991A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
INPUTTIMINGREQUIREMENTS
Symbol
tR, tF
tPWC
Description(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
—
Max.
10
Unit
ns/V
ns
3
—
DH
10
90
ꢁ
REF
ReferenceClockInput
3.75
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
IDT5991A-2
IDT5991A-5
IDT5991A-7
Typ.
Symbol Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
FNOM
tRPWH
tRPWL
tU
VCO Frequency Range
SeePLLProgrammableSkewRangeandResolutionTable
REF Pulse Width HIGH(1)
REF Pulse Width LOW(1)
3
3
—
—
—
—
3
3
—
—
—
—
3
3
—
—
—
—
ns
ns
ProgrammableSkewTimeUnit
SeeControlSummaryTable
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
—
—
—
0.05
0.1
0.2
0.25
0.5
—
—
—
0.1
0.25
0.6
0.25
0.5
—
—
—
0.1
0.3
0.6
0.25
0.75
1
ns
ns
ns
tSKEW0
tSKEW1
ZeroOutputSkew(AllOutputs)(1,4,5)
OutputSkew
0.25
0.7
(Rise-Rise,Fall-Fall,SameClassOutputs)(1,3)
OutputSkew
(Rise-Fall,Nominal-Inverted,Divided-Divided)(1,6)
tSKEW2
tSKEW3
tSKEW4
—
—
—
—
0.5
0.25
0.5
1
—
—
—
—
0.5
0.5
0.5
1.2
0.7
1
—
—
—
—
0.5
0.7
1.2
1.5
1.2
1.7
ns
ns
ns
OutputSkew
0.5
0.9
(Rise-Rise,Fall-Fall,DifferentClassOutputs)(1,6)
OutputSkew
(Rise-Fall,Nominal-Divided,Divided-Inverted)(1,2)
Device-to-Device Skew(1,2,7)
REF Input to FB Propagation Delay(1,9)
Output Duty Cycle Variation from 50ꢁ(1)
Output HIGH Time Deviation from 50ꢁ(1,10)
OutputLOWTimeDeviationfrom50ꢁ(1,11)
OutputRiseTime(1)
tDEV
tPD
—
0
0.75
0.25
1.2
2
—
0
1.25
0.5
1.2
2.5
3
—
0
1.65
0.7
1.2
3
ns
ns
ns
ns
ns
ns
ns
ms
ps
−
0.25
−
0.5
−
0.7
1.2
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
−1.2
0
−1.2
0
−
0
—
—
—
1
—
—
—
1
—
—
—
1.5
1.5
—
—
—
—
0.15
0.15
—
2.5
1.2
1.2
0.5
25
—
0.15
0.15
—
—
0.15
0.15
—
3.5
2.5
2.5
0.5
25
1.5
1.5
0.5
25
OutputFallTime(1)
PLLLockTime(8)
1
1
—
—
—
—
—
—
Cycle-to-CycleOutputJitter(1)
RMS
—
—
—
Peak-to-Peak
—
200
—
200
—
200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5991A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max.
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
5
IDT5991A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
AC TEST LOADS AND WAVEFORMS
VCC
130 Ω
91 Ω
Output
CL
CL = 50pF (CL = 30pF for -2 and -5 devices)
Test Load
t
t
OFALL
ORISE
t
2.0V
0.8V
PWH
t
PWL
TTL Output Waveform
≤1ns
≤1ns
3.0V
2.0V
Vth = 1.5V
0.8V
0V
TTL Input Test Waveform
6
IDT5991A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
AC TIMING DIAGRAM
tRPWL
tREF
tRPWH
REF
tPD
tODCV
tODCV
FB
Q
tJR
tSKEWPR
tSKEW0, 1
tSKEWPR
tSKEW0, 1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3, 4
tSKEW3, 4
tSKEW3, 4
tSKEW2, 4
REF DIVIDED BY 2
tSKEW1, 3, 4
REF DIVIDED BY 4
NOTES:
VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VDD. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the
negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 50pF (30pF for
-2 and -5) and terminated with 50 to 2.06V.
Ω
tSKEWPR:
tSKEW0:
tDEV:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
The skew between outputs when they are selected for 0tU
.
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
The deviation of the output from a 50ꢁ duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tODCV:
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7
IDT5991A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
XXXXX
XX
X
Package Process
Device Type
,5991A-2
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C),5991A-5,5991A-7
Blank
I
J
JG
Rectangular Plastic Leaded Chip Carrier
PLCC - Green
Programmable Skew PLL Clock Driver TurboClock
5991A-2
5991A-5
5991A-7
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
800-345-7015 or 408-284-8200
clockhelp@idt.com
San Jose, CA 95138
fax: 408-284-2775
www.idt.com
8
相关型号：
5991A-7JG
PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, GREEN, PLASTIC, LCC-32
IDT
5991A-7JGI
PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, GREEN, PLASTIC, LCC-32
IDT
©2020 ICPDF网 联系我们和版权申明