5P49EE505NDGI [IDT]
Video Clock Generator, 120MHz, 3 X 3 MM, ROHS COMPLIANT, VFQFPN-20;
| 型号： | 5P49EE505NDGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Video Clock Generator, 120MHz, 3 X 3 MM, ROHS COMPLIANT, VFQFPN-20 时钟 外围集成电路 晶体 |
| 文件： | 总26页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
VERSACLOCK® LOW POWER CLOCK GENERATOR
IDT5P49EE505
Description
Features
The IDT5P49EE505 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to five unique
non-integer-related frequencies. The frequencies are
generated from a single reference clock. The reference
clock needs to come from a TCXO sine wave input.
• Four internal PLLs
• Internal non-volatile EEPROM
2
• Internal I C EEPROM master interface
2
• FAST (400kHz) mode I C serial interfaces
• Input Frequencies
– TCXO: 10 MHz to 40 MHz
A buffered reference Sine wave output clock is supported
with amplitude of 750 mV to 1V, peak to peak.
• One buffered Sine wave output at 750 mV to 1Vpp
• Output Frequency Ranges: kHz to 100 MHz
The IDT5P49EE505 can be programmed through the use
• Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
2
of the I C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
• 8-bit output-divider blocks
• One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
• I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
• 2 independent adjustable VDDO groups.
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Individual output enable/disable
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
spectrum mode.
• Power-down/Sleep mode
– 10μA max in power down mode
• 1.8V VDD Core Voltage
• Available in 20pin 3x3mm QFN packages
• -40 to +85 C Industrial Temp operation
There are total four 8-bit output dividers. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
• Smart Mobile Handset
• Personal Navigation Device (PND)
• Camcorder
• DSC
• Portable Game Console
• Personal Media Player
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Functional Block Diagram
VDD
VDDO1
VDDO2
AVDD
S
R
C
0
/DIV0
OUT0
TCXO_IN
S
R
C
1
750 mV to 1 Vpp
PLLA
/DIV1
/DIV2
/DIV3
OUT1
OUT2
OUT3
S
R
C
2
PLLB(SS)
SDA
Control
Logic
S
R
C
3
SCL
SEL
PLLC
OUT4
750 mV to 1 Vpp
PLLD
GND
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Pin Assignment
16
VDDA
TCXO_IN
GND
OUT0
SCLK
GND
1
SEL1
OUT3
11
OUT1
SEL0
6
20- pin QFN
Pin Descriptions
Pin Name
VDDA
Pin #
I/O Pin Type
Pin Description
1
2
3
4
--
I
Power
Input
Filtered analog power supply. Connect to 1.8V.
TCXO input or external reference clock input.
Connect to Ground.
TCXO_IN
GND
Power
OUT3
O
I
OUTPUT Configurable clock output 3. Single-ended output voltage levels
are register controlled by VDDO2.
SEL0*
VDD
5
6
7
8
LVTTL
Power
Power
Power
Configuration select pin. Weak internal pull down resistor.
Device power supply. Connect to 1.8V.
VDDx
VDDO1
Device power supply. Connect to 1.8V.
Device power supply. Connect to 1.8 to 3.3V. VDDO1 must be
the highest voltage on the device. Using register settings, select
output voltage levels for OUT0-OUT3.
GND
9
Power
Connect to Ground.
OUT2
10
O
O
I
Adjustable Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
OUT1
11
Adjustable Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
SEL1*
GND
12
13
14
LVTTL
Power
LVTTL
Configuration select pin. Weak internal pull down resistor.
Connect to Ground.
I2C clock. Logic levels set by VDDO1. 5V tolerant.
SCLK
I
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OUT0
OUT4
15
16
O
O
Adjustable Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
Output
Buffered reference Sine wave clock output. Single-ended output
voltage levels are controlled by VDDA. Output high-Z when
disabled. AC couple wiht 0.1μF capacitor.
SDA
17
18
I/O
Open Drain Bidirectional I2C data. Logic levels set by VDDO1. 5V tolerant.
VDDO2
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT3. If VDDO2
is 1.8V, only OUT4 may be connected to VDDO2.
VDD
GND
19
20
Power
Power
Device power supply. Connect to 1.8V.
Connect to Ground.
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above.
Note 2: Default configuration CLK3=Buffered Reference output. All other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
Ideal Power Up Sequence
Ideal Power Down Sequence
1) VDDO must drop first, followed by VDD and VDD
x
1) VDD and VDDx must come up first, followed by VDD
O
2) VDD and VDDx must come down within 1ms after VDDO1 comes down
3) VDDO2 must be equal to, or lower than, VDDO1
2) VDDO1 must come up within 1ms after VDD and VDDX come up
3) VDDO2 must be equal to, or lower than, VDDO1
4) VDD and VDDx have approx. the same ramp rate
5) VDDO1 and VDDO2 have approx. same ramp rate
4) VDD and VDDx have approx. the same ramp rate
5) VDDO1 and VDDO2 have approx. same ramp rate
V
V
VDDO1
VDDO1
V
DDO2, VDDO3
VDDO2, VDDO3
VDD, VDD
x
VDD, VDD
x
t
1 ms
1 ms
t
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PLL Features and Descriptions
D
VCO
M
XDIV
PLL Block Diagram
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Feedback
Programmable
Spread Spectrum
(M) Values Loop Bandwidth Generation Capability
Values
PLLA
PLLB
PLLC
PLLD
1 - 255
1 - 255
1 - 255
1 - 255
1 or 4
4
6 - 2047
6 - 2047
6 - 2047
6 - 2047
Yes
Yes
Yes
Yes
No
Yes
No
No
1 or 8 bit divide
1 or 4
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
XDIV*M
F *
=
FOUT
(
)
(Eq. 2)
IN
D
ODIV
Where F is the reference frequency, XDIV is the feedback
IN
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and F
is the resulting output frequency. Programming
OUT
any of the dividers may cause glitches on the outputs.
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Modulation frequency:
SPREAD SPECTRUM GENERATION
(PLLB)
F
= F
/ NC (Eq. 11)
MOD
MID
PLLB has spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The programmable spread
spectrum generation parameters are NC[10:0], MOD[12:0],
and NSS[10:0] bits. To enable spread spectrum, set
SSENB_B=0.
Video Example
F
= 27 MHz, F
= 27 MHz, 640 pixels per line, center
OUT
REF
spread of 1%. Using F
spread spectrum register settings.
=432MHz, find the necessary
VCO
F
= F /8
MID
VCO
NC = 640 (integer number of spread periods/screen)
MOD = (25MHz * 640)/(2 * 54MHz) = 160
The spread spectrum circuitry was specifically developed to
accommodate video display applications. The spread
modulation frequency can be defined to exactly equal the
horizontal line frequency (HSYNC)
NSS = (640/2)+(640/8)*(27.27MHz-26.73MHz)/27MHz =
321.
NC[10:0]
These bits are used to determine the number of pulses per
spread spectrum cycle. For video applications, NC is the
number of pixels on the horizontal display row (or integer
multiple of displayed pixels in a row). By matching the
spread period to the screen, no tearing or “shimmer” will be
apparent.
F
= 27MHz/640 = 11.8kHz.
MOD
Non-Video Example
F
= 25MHz, F
= 27 MHz, 31.25kHz modulation rate,
OUT
REF
center spread of 1%. Find the necessary spread spectrum
register settings.
NC must be an even number to insure that the upward
spread transition has the same number of steps as the
downward spread transition.
F
F
= F
/ 8
VCO
MID
= 31.25kHz = 50.625MHz/NC.
MOD
For non-video applications, this can also be seen as the
number of clock cycles for a complete spread spectrum
period.
NC = 1620
MOD = (25MHz * 1620)/(2 * 50.625MHz) = 400
MOD[12:0]
NSS = (1620/2)+(1620/8)*(27.27MHz-26.73MHz)/27MHz =
814.
These bits relate the VCO frequency to the target average
spread output frequency (F ).
MID
F
F
F
= (F
) / 8
VCO
MID
MAX
MIN
= F
+ (SS% * F
MID)
MID
MID
= F
- (SS% * F
MID)
MOD = (F
* NC) / (2 * F
)
REF
MID
NSS[10:0]
These bits control the amplitude of the spread modulation.
NSS = (NC / 2) + (NC / 8) * (F
- F ) / F
MIN MID
MAX
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VSYNC, HSYNC, DOT_CLK – Modulation Rate Relationship
VSYNC
HSYNC
Integer multiple of HSYNC periods
DOT_CLK
Modulation
Rate
X/2
X
X/2
X
X = Number of cycles of DOT_CLK per HSYNC period.
X/2 = Number of cycles of DOT_CLK that the modulation edge rises/falls.
Zero capacitor (Cz) = 280pF
Pole capacitor (Cp) = 30pF
LOOP FILTER
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low jitter
generation. The specific loop filter components that can be
programmed are the resistor via the RZ[4:0] bits, zero
capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0]
bits, and the charge pump current via the IP#[2:0] bits.
Charge pump (Ip) = IP#[2:0] uA
VCO gain (KVCO) = 350MHz/V * 2π
The following equations govern how the loop filter is set:
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Damping Factor:
ζ= Rz/2 *(KVCO * Ip * Cz) /M
1/2
Example
Fc = 150KHz is the desired loop bandwidth. The total A*M
value is 160. The ζ(damping factor) target should be 0.7,
meaning the loop is critically damped. Given Fc and A*M, an
optimal loop filter setting needs to be solved for that will
meet both the PLL loop bandwidth and maintain loop
stability.
Choose a mid-range charge pump from register table
Icp= 11.9uA.
PLL Loop Bandwidth:
Charge pump gain (Kφ⎞) = Ip / 2π
Kφ * KVCO = 350MHz/V * 40uA = 12000A/Vs
5
-1
ωc = 2π * Fc = 9.42x10 s
VCO gain (KVCO) = 350MHz/V * 2π
ωp = (Cz + Cp)/(Rz * Cz * Cp) = ωz (1 + Cz / Cp)
M = Total multiplier value (See the PRE-SCALERS,
FEEDBACK-DIVIDERS, POST-DIVIDERS section for more
detail)
Solving for Rz, the best possible value Rz=30kOhms
(RZ[1:0]=10) gives
ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp))
Fc = ωc / 2π
ζ= 1.4 (Ideal range for ζ is 0.7 to 1.4)
Solving back for the PLL loop bandwidth, Fc=149kHz.
The phase margin must be checked for loop stability.
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce your phase margin thus
compromising loop stability.
5
-1
5 -1
φm = (360 / 2π) * [tan-1 (9.42x10 s / 1.19x10 s )
-1
5
-1
6 -1
- tan (9.42x10 s / 1.23x10 s )] = 45°
To determine if the loop is stable, the phase margin (φm)
would need to be calculated as follows.
The phase margin would be acceptable with a fairly stable
loop.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = (Cz + Cp)/(Rz * Cz * Cp)
-1
-1
φm = (360 / 2π) * [tan (ωc/ ωz) - tan (ωc/ ωp)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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SEL[1:0] Function
The IDT5P49EE505 can support up to three unique
configurations. Users may pre-program all configurations,
selected using SEL[1:0] pins. Alternatively, users may use
I2C interface to configure these registers on- the-fly.
Always power with SEL1=1 and/or SEL0=1.
.
SEL1
SEL0
Configuration Selections
Power Down/Sleep Mode
0
0
1
1
0
1
0
1
Select CONFIG0
Select CONFIG1
Select CONFIG2
voltage of any pin on the device. VDDO2 may have any
value between 1.8V and VDDO1. If VDDO2 is set to 1.8V,
only OUT4 may be connected to this supply.
Configuration OUTx IO Standard
Users can configure the individual output IO standard from
a single 1.8V power supply. Each output can support 1.8V/
2.5V or 3.3V LVCMOS. VDDO1 must have the highest
Programming the Device
2
I C may be used to program the IDT5P49EE505.
The frame formats are shown in the following illustration.
– Device (slave) address = 7'b1101010
I2C Programming
The IDT5P49EE505 is programmed through an I2C-Bus
2
serial interface, and is an I C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
Framing
2
First Byte Transmitted on I C Bus
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External I2C Interface Condition
after the STOP condition is issued by the Master, during
which time the IDT5P49EE505 will not generate
EEPROM Interface
The IDT5P49EE505 can store its configuration in an internal
EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by
issuing a save instruction (ProgSave) and can be loaded
back to the internal programming registers by issuing a
restore instruction (ProgRestore).
Acknowledge bits. The IDT5P49EE505 will acknowledge
the instructions after it has completed execution of them.
2
During that time, the I C bus should be interpreted as busy
by all other users of the bus.
On power-up of the IDT5P49EE505, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The IDT5P49EE505 will be ready to
accept a programming instruction once it acknowledges its
2
To initiate a save or restore using I C, only two bytes are
transferred. The Device Address is issued with the
read/write bit set to “0”, followed by the appropriate
command code. The save or restore instruction executes
2
7-bit I C address.
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
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Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
S
Address R/W ACK ID Byte ACK Data_1 ACK Data_2 ACK Data_last NACK
P
7-bits
1
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the IDT5P49EE505 registers.
PROGREAD is for reading the IDT5P49EE505 registers.
PROGSAVE is for saving all the contents of the
IDT5P49EE505 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM
contents to the IDT5P49EE505 registers.
Progrestore
Note:
During PROGRESTORE, outputs will be turned off to
ensure that no improper voltage levels are experienced
before initialization.
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I2C Bus DC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
V
Input HIGH Level
0.7xVDDO1
IH
V
Input LOW Level
0.3xVDDO1
V
IL
V
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
0.05xVDDO1
V
HYS
I
V
= 0V
1.0
0.4
µA
V
IN
DD
V
I
= 3 mA
OL
OL
I2C Bus AC Characteristics for Standard Mode
Symbol
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Min
0
Typ
Max
Unit
kHz
µs
F
100
SCLK
t
4.7
4.7
4
BUF
t
µs
SU:START
HD:START
t
Hold Time, START
µs
t
Setup Time, data input (SDA)
250
0
ns
SU:DATA
1
t
Hold Time, data input (SDA)
µs
HD:DATA
t
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCLK)
Fall Time, data and clock (SDA, SCLK)
HIGH Time, clock (SCLK)
3.45
400
µs
OVD
C
pF
ns
B
t
1000
300
R
t
ns
F
t
4
4.7
4
µs
HIGH
t
LOW Time, clock (SCLK)
µs
LOW
t
Setup Time, STOP
µs
SU:STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V MIN of
IH
the SCLK signal) to bridge the undefined region of the falling edge of SCLK.
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I2C Bus AC Characteristics for Fast Mode
Symbol
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Min
0
Typ
Max
Unit
kHz
µs
F
400
SCLK
t
1.3
0.6
0.6
100
0
BUF
t
µs
SU:START
HD:START
t
Hold Time, START
µs
t
Setup Time, data input (SDA)
ns
SU:DATA
HD:DATA
1
t
Hold Time, data input (SDA)
µs
t
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCL)
Fall Time, data and clock (SDA, SCL)
HIGH Time, clock (SCL)
0.9
400
300
300
µs
OVD
C
pF
ns
B
t
20 + 0.1xC
20 + 0.1xC
0.6
R
B
t
ns
F
B
t
µs
HIGH
t
LOW Time, clock (SCL)
1.3
µs
LOW
t
Setup Time, STOP
0.6
µs
SU:STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V MIN of
IH
the SCL signal) to bridge the undefined region of the falling edge of SCL.
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5P49EE505. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Symbol
Description
Internal Power Supply Voltage
Input Voltage
Max
Unit
V
V
-0.5 to +4.6
-0.5 to +4.6
DD
V
V
I
V
Output Voltage (not to exceed 4.6 V)
Junction Temperature
-0.5 to V +0.5
V
O
DD
T
150
°C
°C
J
T
Storage Temperature
-65 to +150
STG
Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
V
, V x, Power supply voltage for VDD
1.71
1.8
1.89
V
DD
DD
V
A
DD
V
Power supply voltage for outputs VDDO1/2/3
1.71
2.375
3.135
-40
1.8
2.5
3.3
1.89
2.625
3.465
+85
15
V
V
DDOX
V
T
Operating temperature, ambient
°C
pF
pF
MHz
ms
A
C
C
Maximum load capacitance (3.3V LVTTL only)
Maximum load capacitance (1.8V or 2.5V LVTTL only)
External reference clock CLKIN
LOAD_OUT
LOAD_OUT
8
F
10
40
IN
t
Power up time for all V s to reach minimum specified
0.05
5
PU
DD
voltage (power ramps must be monotonic)
Capacitance (T = +25 °C, f = 1 MHz)
A
Symbol
Parameter
Min
Typ
Max
Unit
C
Input Capacitance
3
pF
IN
TCXO Specifications
TCXO_FREQ TCXO frequency
10
40
MHz
V
TCXO_V
Voltage swing (peak-to-peak, nominal)
0.75
1.0
PP
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EEPROM CLOCK GENERATOR
DC Electrical Characteristics for 3.3 Volt LVTTL 1
Symbol
Parameter
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min
Typ
Typ
Typ
Max
VDDO
0.4
Unit
V
V
I
I
= 33mA
2.4
OH
OH
V
= 33mA
V
OL
OH
I
Output Leakage Current 3-state outputs
5
µA
OZDD
DC Electrical Characteristics for 2.5Volt LVTTL 1
Symbol
Parameter
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min
Max
VDDO
0.4
Unit
V
V
I
I
= 25mA
2.1
OH
OH
V
= 25mA
V
OL
OH
I
Output Leakage Current 3-state outputs
5
µA
OZDD
DC Electrical Characteristics for 1.8Volt LVTTL 1
Symbol
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
Max
VDDO
Unit
V
V
VDD = 1.71V to 1.89V
0.65*VDDO
OH
V
0.35*VDDO
V
OL
V
SEL[1:0], 3.3V tolerant
SEL[1:0], 3.3V tolerant
0.75VDD
V
IH
V
0.25VDD
5
V
IL
OZDD
I
Output Leakage Current 3-state outputs
µA
Power Supply Characteristics for LVTTL Outputs
Total Supply Current Vs VCO Frequency
Supply current Vs Output Frequency
30
14
12
10
8
6
4
25
20
15
10
5
2
0
0
0
100
200
300
400
0
20
40
60
80
100
120
VCO Frequency(MHz)
Output Frequency(MHz)
1 output on
4 outputs on
2 outputs on
5 outputs on
3 outputs on
1 PLL ON IDD (mA)
3 PLLs on IDD (mA)
2 PLLs On IDD (mA)
All PLLs ON IDD (mA)
1: See “Recommended Operating Conditions” table. Alway completely power up VDD and VDDx prior to applying VDDO
power.
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EEPROM CLOCK GENERATOR
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
fIN
Parameter
Test Conditions
Input Frequency Limit (TCXO_IN)
Single Ended Clock output limit (LVTTL) 3.3V
Single Ended Clock output limit (LVTTL) 2.5V
Single Ended Clock output limit (LVTTL) 1.8V
VCO operating Frequency Range
PFD operating Frequency Range
Duty Cycle for Input
Min. Typ. Max. Units
Input Frequency
10
40
120
110
100
475
20
MHz
MHz
MHz
MHz
MHz
MHz
%
1 / t1
Output Frequency
0.001
fVCO
fPFD
t2
VCO Frequency
100
0.5 1
40
PFD Frequency
Input Duty Cycle
60
t3
Output Duty Cycle
Slew Rate, SLEWx(bits) = 00
Measured at VDD/2
45
55
%
t4
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
5.1
4.4
2.8
1.8
V/ns
Slew Rate, SLEWx(bits) = 01
Slew Rate, SLEWx(bits) = 10
Slew Rate, SLEWx(bits) = 11
Clock Jitter
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
t5
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Single output frequency only.
100
200
ps
ps
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Multiple output frequencies switching.
t6
t7
Output Skew
Lock Time
Skew between output to output on the same
bank
75
ps
ps
Skew between any output (Same freq and IO
type, FOUT >10MHz)
200
PLL Lock Time from Power-up 1
5
5
20
10
ms
ms
PLL Lock time from shutdown mode
1.Time from supply voltage crosses VDD=1.62V to PLLs are locked.
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Spread Spectrum Generation Specifications
Symbol
Parameter
Description
Min Typ Max
Unit
MHz
kHz
1
f
Input Frequency Input Frequency Limit
Mod Frequency Modulation Frequency
1
40
IN
f
32
120
MOD
f
Spread Value
Amount of Spread Value (programmable) - Down Spread
Amount of Spread Value (programmable) - Center Spread
Total Spread Value
Programmable
Programmable
0.5 4.0
%f
OUT
SPREAD
Note 1: Practical lower frequency is determined by loop filter settings.
Test Circuits and Conditions 1
Test Circuits for DC Outputs
Other Termination Scheme (Block Diagram)
RS
OUTPUTS
GND
CLKOUT
CLOAD
LVTTL Output Load: ~7pF for each output
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Programming Registers Table
Default
Bit #
Register
Addr
Description
0
Hex
Value
04
7
6
5
4
3
2
1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Reserved
00
INV[0]
SLEW1[0:1]
Reserved
PS0[2:1]
Reserved
INV[#] - Invert output#
SLEW#[0:1] - output# slew setting
0 0 - 5.1V/ns
0 1 - 4.4V/ns
1 0 - 2.8V/ns
1 1 - 1.8V/ns
PS#[2:1] -Power Select
00 - Reserved
01 - CLK# connects to VDDO1
10 - CLK# connects to VDDO2
11 - Reserved
00
Reserved
Reserved
00
00
INV[1]
INV[2]
INV[3]
SLEW1[0:1]
SLEW2[0:1]
SLEW3[0:1]
Reserved
Reserved
Reserved
PS1[2:1]
PS2[2:1]
PS3[2:1]
Reserved
Reserved
Reserved
00
00
00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
REFA[7:0]
00
00
00
00
00
00
00
Configuration0
REFA[7:0] - Reference Divide PLLA
0x0F
0x10
0x11
00
00
00
FBA[10:3)
FBA[10:0] - Feedback Divide PLLA
Reserved
RZA[1:0]
FBA[2:0)
Reserved
XDIVA
IPA[2:0]
Reserved
RZA[1:0] - Zero Resistor PLLA
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPA[2:0] - charge Pump Current PLLA
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
00
00
00
00
00
00
00
20
00
REFB[7:0]
FBB[10:3]
REFB[7:0] - Reference Divide PLLB
FBB[10:0] - Feedback Divide PLLB
MOD[4:0]
NSS[4:0]
FBB[2:0]
NC[2:0]
PLLB Spread Parameters MOD[12:0]
NC[10:0]
NSS[12:0]
MOD[12:5]
NC[10:3]
NSS[12:5]
Reserved
IPB[2:0]
RZB[1:0]
SSENB_B
RZB[1:0] - Zero Resistor PLLB
00 - 5kOhm
01 - 10kOhm
Reserved
10 - 30kOhm
11 - 80kOhm
IPB[2:0] - charge Pump Current PLLB
000 - 0.37uA, 100 - 6.3uA
001 - 1.1uA, 101 - 11.9uA
010 - 1.8 uA, 110 - 17.7uA
011 - 3.4uA, 111 - 22.7uA
0x1B
0x1C
0x1D
0x1E
00
00
00
00
REFC[7:0]
FBC[10:3]
REFC[7:0] - Reference Divide PLLC
FBC[10:0] - Feedback Divide PLLC
Reserved
FBC[2:0]
FBC2[7:0]
FBC2 - Feedback Predivide PLLC
Turn on using XDIVC=1
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EEPROM CLOCK GENERATOR
Default
Bit #
Register
Addr
Description
0
Hex
Value
00
7
6
5
4
3
2
1
0x1F
IPC[2:0]
RZC[1:0]
Reserved
XDIVC
Reserved
RZC[1:0] - Zero Resistor PLLC
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPC[2:0] - charge Pump Current PLLC
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
0x20
0x21
0x22
0x23
00
00
00
00
REFD[7:0]
FBD[10:3]
REFD[7:0] - Reference Divide PLLD
FBD[10:0] - Feedback Divide PLLD
Reserved
FBD[2:0]
XDIVD
RZD[1:0]
IPD[2:0]
Reserved
RZD[1:0] - Zero Resistor PLLD
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPD[2:0] - charge Pump Current PLLD
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
00
00
00
00
00
00
00
00
00
00
OD0[7:0]
Reserved
Reserved
OD1[7:0]
OD2[7:0]
OD3[7:0]
Reserved
Reserved
Reserved
Reserved
SCR3[1:0]
SRC3[1:0] - OD4 source
00 - off; 10 - PLLA
01 - Reference (square wave);
11 - PLLD
0x2E
00
SCR2[1:0]
SCR1[1:0]
Reserved
SRC1[1:0] - OD1 source
00 - off; 10 - PLLB
01 - PLLA; 11 - PLLD
SRC2[1:0] - OD2 source
00 - off; 10 - PLLC
01 - PLLA; 11 - PLLD
0x2F
0x30
01
FF
SCR0[1:0]
Reserved
SRC0[1:0] - OD0 source
00 - off; 10 - PLLC
01 - PLLB; 11 - PLLD
Reserved
0x31
0x32
0x33
00
00
00
PDB[4]
Reserved
OE[4]
OE[2]
Reserved
PDB[4:0] - Powerdown OUT#.
PDB#=0, OUT# driven low
OE[4:0] - Output enable OUT#.
OE#=0, OUT# tri-stated.
Reserved
Reserved
OE[3]
PDB[3]
OE[1]
Reserved
Reserved
OE[0]
PDB[0]
PDB[2]
PDB[1]
If PDB#=OE#=0, OUT# driven low
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EEPROM CLOCK GENERATOR
Default
Bit #
Register
Addr
Description
0
Hex
Value
00
7
6
5
4
3
2
1
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
REFA[7:0]
FBA[10:3)
Configuration1
(See definitions from Configuration0
above)
00
00
Reserved
FBA[2:0)
00
Reserved
XDIVA
RZA[1:0]
IPA[2:0]
Reserved
00
REFB[7:0]
FBB[10:3]
00
00
MOD[4:0]
NSS[4:0]
FBB[2:0]
NC[2:0]
00
MOD[12:5]
NC[10:3]
00
00
00
NSS[12:5]
40
Reserved
IPB[2:0]
RZB[1:0]
00
Reserved
Reserved
SSENB_B
00
REFC[7:0]
FBC[10:3]
00
00
Reserved
FBC[2:0]
XDIV
00
FBC2[7:0]
RZC[1:0]
00
IPC[2:0]
Reserved
Reserved
00
REFD[7:0]
FBD[10:3]
00
00
Reserved
FBD[2:0]
00
XDIVD
RZD[1:0]
IPD[2:0]
Reserved
00
OD0[7:0]
Reserved
Reserved
OD1[7:0]
OD2[7:0]
OD3[7:0]
Reserved
Reserved
Reserved
00
00
00
00
00
00
00
00
00
Reserved
SCR1[1:0]
SCR3[1:0]
00
SCR2[1:0]
SCR0[1:0]
Reserved
Reserved
01
Reserved
FF
00
Reserved
PDB[4]
Reserved
OE[4]
OE[2]
00
Reserved
Reserved
OE[3]
PDB[3]
OE[1]
Reserved
Reserved
OE[0]
PDB[0]
00
PDB[2]
PDB[1]
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EEPROM CLOCK GENERATOR
Default
Bit #
Register
Addr
Description
0
Hex
Value
00
7
6
5
4
3
2
1
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
REFA[7:0]
FBA[10:3)
Configuration2
(See definitions from Configuration0
above)
00
00
Reserved
FBA[2:0)
00
Reserved
XDIVA
RZA[1:0]
IPA[2:0]
Reserved
00
REFB[7:0]
FBB[10:3]
00
00
MOD[4:0]
NSS[4:0]
FBB[2:0]
NC[2:0]
00
MOD[12:5]
NC[10:3]
00
00
00
NSS[12:5]
40
Reserved
IPB[2:0]
RZB[1:0]
00
Reserved
Reserved
SSENB_B
00
REFC[7:0]
FBC[10:3]
00
00
Reserved
FBC[2:0]
XDIV
00
FBC2[7:0]
RZC[1:0]
00
IPC[2:0]
Reserved
Reserved
00
REFD[7:0]
FBD[10:3]
00
00
Reserved
FBD[2:0]
00
XDIVD
RZD[1:0]
IPD[2:0]
Reserved
00
OD0[7:0]
Reserved
Reserved
OD17:0]
00
00
00
00
OD2[7:0]
OD3[7:0]
Reserved
Reserved
Reserved
00
00
00
00
00
Reserved
SCR1[1:0]
SCR3[1:0]
00
SCR2[1:0]
SCR0[1:0]
Reserved
Reserved
01
Reserved
FF
00
Reserved
PDB[4]
Reserved
OE[4]
OE[2]
00
Reserved
Reserved
OE[3]
PDB[3]
OE[1]
Reserved
Reserved
OE[0]
PDB[0]
00
PDB[2]
PDB[1]
®
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Marking Diagram (ND20)
YYWW
5DGI
Notes:
1. YYWW is the last two digits of the year and week that the part was assembled.
2. “G” designates RoHS compliant package.
3. “I” at the end of part number indicates industrial temperature range.
4. Bottom marking: country of origin if not USA.
Thermal Characteristics 20-pin VFQFPN
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
64
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
56.6
51.8
84.3
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
®
IDT® VERSACLOCK LOW POWER CLOCK GENERATOR
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20-pin QFN PCB Land Pattern
ZDMAX
=
3.26 mm
D2 =
1.75 mm
ZEMAX
3.26 mm
GEMIN
2.15 mm
=
AEMAX
1.83 mm
E2 =
1.75 mm
=
=
ADMAX
1.83 mm
=
Y = 0.55 mm
GDMIN
2.15 mm
=
X = 0.23 mm
®
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Package Outline and Package Dimensions (20-pin QFN)
Package dimensions are kept current with JEDEC Publication No. 95
(Ref)
ND & N
EvenE
Seating Plane
(ND-1)x
(Ref)
e
A1
Index Area
(Typ)
If ND & N
L
A3
e
N
1
2
N
E
2
are Even
1
2
(NE-1)x
(Ref)
e
Sawn
Singulation
E2
E
E2
2
Top View
b
A
(Ref)
ND & N
e
Thermal Base
D
Odd E
EP – Exposed thermal pad
should be externally
D2
2
connected to ground.
C
D2
0.08 C
Millimeters
Symbol
Min
Max
A
A1
A3
b
0.80
0
0.25 Reference
1.00
0.05
0.15
0.25
e
0.40 BASIC
N
20
N
N
5
5
D
E
D x E BASIC
3.00 x 3.00
D2
E2
L
0.95
0.95
0.30
1.25
1.25
0.50
Ordering Information
Part / Order Number
Marking
See page 22
See page 22
Shipping Packaging
Tubes
Package
20pin VFQFPN
20pin VFQFPN
Temperature
-40 to +85° C
-40 to +85° C
5P49EE505NDGI
5P49EE505NDGI8
Tape and Reel
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
®
IDT® VERSACLOCK LOW POWER CLOCK GENERATOR
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Revision History
Rev. Originator
Date
Description of Change
A
B
C
D
E
F
R.Willner
R.Willner
R.Willner
R.Willner
R.Willner
R.Willner
R. Willner
12/8/09 Initial Preliminary Datasheet
4/1/10
Typographical changes. Register corrections. Correct spread spectrum calculations.
6/11/10 Typographical changes. Default configuration.
9/08/10 Power ramp sequence. Package marking. Thermal pad connected to ground.
10/29/10 Typographical changes. Loop filter calculations. Default register bit corrections.
01/19/11 Corrected top-side marking notes.
G
04/13/11 1. Updated SCLK and SDA pin descriptions
2. Updated DC Electrical Char table for 1.8V LVTTL; added VIH and VIL.
3. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC
Timing Electrical Char table.
H
J
R. Willner
R. Willner
0930/11 Updated Power-up/Power-down Sequence notes.
10/17/11 1. Added VDDOx specs in Recommende Operations table
2. Updated Ideal Power-up/Down Sequence diagrams
®
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EEPROM CLOCK GENERATOR
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
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