5P49V5907_16 概述
Programmable Clock Generator
5P49V5907_16 数据手册
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PDF下载Programmable Clock Generator
5P49V5907
DATASHEET
Description
Features
The 5P49V5907 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
• Generates up to four independent output frequencies with a
total of 7 differential outputs and one reference output
• Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency of
each output pair can be individually programmed
2
Programmable (OTP) memory or changed using I C
interface. This is IDTs fifth generation of programmable clock
®
technology (VersaClock 5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
– Four copies of Low Power HCSL(LP-HCSL) outputs.
• Programmable frequency:
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
– See Output Features and Descriptions for details
• One reference LVCMOS output clock
• High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
2
The device may be configured to use one of two I C
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
addresses to allow multiple devices to be used in a system.
Pin Assignment
• Four fractional output dividers (FODs)
• Independent Spread Spectrum capability from each
fractional output divider (FOD)
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
2
• I C serial programming interface
• Input frequency ranges:
35
40 39 38 37 36
34 33 32 31
30
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
1
2
VDDO
2
NC
XOUT
XIN/REF
VDDA
OUT2
29
28
27
26
– Crystal frequency range: 8MHz to 40MHz
OUT2B
3
4
• Output frequency ranges:
VDD
– LVCMOS Clock Outputs – 1MHz to 200MHz
5
6
7
VDDO
VDD
EPAD
– LP-HCSL Clock Outputs – 1MHz to 200MHz
VDD_CORE
OUT3
OUT3B
NC
25
24
OUT7
OUT7B
– Other Differential Clock Outputs – 1MHz to 350MHz
23
22
21
8
OUT6
OUT6B
SD/OE
• Programmable loop bandwidth
• Programmable crystal load capacitance
• Power-down mode
9
10
NC
12
17 18
19 20
13 14 15 16
11
• Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 4 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
40-pin VFQFPN
– See Pin Descriptions for details
• Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)
• -40° to +85°C industrial temperature operation
5P49V5907 NOVEMBER 11, 2016
1
©2015 Integrated Device Technology, Inc.
5P49V5907 DATASHEET
Functional Block Diagram
VDDO
OUT0_SEL_I2CB
VDDO
0
XIN/REF
XOUT
1
OUT1
SD/OE
FOD1
FOD2
FOD3
OUT1B
SEL1/SDA
VDDO
2
OTP
and
Control Logic
OUT2
SEL0/SCL
OUT2B
PLL
VDDA
OEB3,5
VDD_CORE
VDDO
OE_buffer
VDD
OUT3, 5
OEB6,7
OUT6, 7
VDDO
4
OUT4
FOD4
OUT4B
Applications
• Ethernet switch/router
• PCI Express 1.0/2.0/3.0
• Broadcast video/audio timing
• Multi-function printer
• Processor and FPGA clocking
• Any-frequency clock conversion
• MSAN/DSLAM/PON
• Fiber Channel, SAN
• Telecom line cards
• 1 GbE and 10 GbE
PROGRAMMABLE CLOCK GENERATOR
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5P49V5907 DATASHEET
Table 1:Pin Descriptions
Number
Name
Type
Description
1
2
3
NC
Input
Input
Input
Do not connect
XOUT
Crystal Oscillator interface output.
XIN/REF
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V max. Refer to the section “Overdriving the
XIN/REFInterfac e”.
4
5
VDDA
VDDO
OUT7
Power
Power
Output
Output
Output
Output
Input
Analog functions power supply pin. Connect to 1.8V.
Connect to 1.8V. Power pin for outputs 3, 5-7
6
Output Clock 7. Low-Power HCSL (LP-HCSL) output.
7
OUT7B
OUT6
Complementary Output Clock 7. Low-Power HCSL (LP-HCSL) output..
Output Clock 6. Low-Power HCSL (LP-HCSL) output.
8
9
OUT6B
SD/OE
Complementary Output Clock 6. Low-Power HCSL (LP-HCSL) output..
10
Internal Pull- Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
down
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of
the signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the
single-ended LVCMOS outputs are driven low. When configured as OE, and
outputs are disabled, the outputs can be selected to be tri-stated or driven
high/low, depending on the programming bits as shown in the SD/OE Pin
Function Truth table.
11
12
SEL1/SDA
SEL0/SCL
Input
Input
Internal Pull- Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
down Weak internal pull down resistor.
Internal Pull- Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
down
Weak internal pull down resistor.
Connect to 1.8V
13
14
15
16
17
VDD
Power
Power
Output
Output
Input
VDDO
OUT5
OUT5B
Connect to 1.8V. Power pin for outputs 3, 5-7.
Output Clock 5. Low-Power HCSL (LP-HCSL) output.
Complementary Output Clock 5. Low-Power HCSL (LP-HCSL) output.
Internal Pull- Active low Output Enable pin for Outputs 3 and 5.
OEB3,5
down
1=disable outputs, 0=enable outputs. This pin has internal pull-down.
Connect to 1.8V to 3.3V. VDD supply for OUT4.
18
19
20
VDDO4
OUT4
Power
Output
Output
Output Clock 4. Please refer to the Output Drivers section for more details.
OUT4B
Complementary Output Clock 4. Please refer to the Output Drivers section for
more details.
21
22
23
24
25
26
27
28
NC
Do not connect
—
—
NC
Do not connect
OUT3B
OUT3
VDD_Core
VDD
Output
Output
Power
Power
Power
Output
Complementary Output Clock 3. Low-Power HCSL (LP-HCSL) output.
Output Clock 3. HCSL Low-Power HCSL (LP-HCSL) output..
Connect to 1.8V
Connect to 1.8V
Connect to 1.8V
VDD
OUT2B
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
29
30
31
OUT2
Output
Power
Output
Output Clock 2. Please refer to the Output Drivers section for more details.
VDDO2
OUT1B
Connect to 1.8V to 3.3V. VDD supply for OUT2.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
32
33
34
OUT1
Output
Power
Input
Output Clock 1. Please refer to the Output Drivers section for more details.
VDDO1
Connect to 1.8V to 3.3V. VDD supply for OUT1.
Internal Pull- Active low Output Enable pin for Outputs 6 and 7.
OEB6,7
down
1=disable outputs, 0=enable outputs. This pin has internal pull-down.
Do not connect
35
NC
—
NOVEMBER 11, 2016
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
Pin Descriptions (cont.)
Number
Name
Type
Description
36
37
38
VDDO
Power
Power
Connect to 1.8V. Power pin for outputs 3, 5-7
Connect to 1.8V.
VDD
OE_buffer
Internal Pull- Active High Output enable for outputs 3, 5-7. 0=disable outputs.
up
1=enable outputs. This pin has internal pull-up.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
39
40
VDDO0
Power
OUT0_SEL_I2CB Output
Internal Pull- Latched input/LVCMOS Output. At power up, the voltage at the pin
down
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 11
and 12. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 11 and
12 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull
down (10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 11 and
12 will act as the SDA and SCL pins of an I2C interface. After power up, the pin
acts as a LVCMOS reference output.
ePAD GND
GND
Connect to ground pad
Table 3: Configuration Table
PLL Features and Descriptions
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
5P49V5907 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5907 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The Spread spectrum can be
applied to any output divider and any spread amount from
±0.25% to ±2.5% center spread and -0.5% to -5% down
spread.
2
OUT0_SEL_I2CB SEL1 SEL0
@ POR
I C
REG0:7 Config
Access
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
No
0
0
0
0
1
0
1
2
3
No
No
No
Yes
I2C
Table 2: Loop Filter
defaults
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
0
X
X
Yes
0
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDA power supply so that they ramp with that
supply or are tied low (this is the same as floating the pins).
This will cause the register configuration to be loaded that is
selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10mS of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDA. The
SELx pins must be driven with a digital signal of < 300nS
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
Input Reference
Loop
Loop
Frequency–Fref BandwidthMin Bandwidth Max
(MHz)
5
(kHz)
40
(kHz)
126
350
300
1000
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
PROGRAMMABLE CLOCK GENERATOR
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5P49V5907 DATASHEET
You can write the following equations for the total capacitance
at each crystal pin:
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
C
C
= Ci + Cs + Ce
1 1 1
XIN
= Ci + Cs + Ce
XOUT
2
2
2
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
Ci and Ci are the internal, tunable capacitors. Cs and Cs
2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
1
2
1
Ce and Ce are additional external capacitors that can be
1
2
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce and/or Ce to avoid
1
2
crystal startup issues. Ce and Ce can also be used to adjust
for unpredictable stray capacitance in the PCB.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
1
2
The final load capacitance of the crystal:
CL = C
× C
/ (C
+ C
)
XIN
XOUT
XIN
XOUT
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
C
= C
= Cx → CL = Cx / 2
XIN
XOUT
The complete formula when the capacitance at both crystal
pins is the same:
XTAL[5:0] Tuning Capacitor Characteristics
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Parameter
Bits
Step (pF)
Min (pF)
Max (pF)
Example 1: The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs=1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
XTAL
6
0.5
9
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →
0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
Example 2: The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →
XTAL[5:0] = 20 (decimal)
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
OTP Interface
Table 4: SD/OE Pin Function Truth Table
The 5P49V5907 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
SH bit SP bit OSn bit OEn bit SD/OE
OUTn
0
0
0
0
0
0
0
0
0
1
1
1
x
0
1
1
x
x
0
1
Tri-state2
Output active
Output active
Output driven High Low
0
0
0
0
1
1
1
1
0
1
1
1
x
0
1
1
x
x
0
1
Tri-state2
Output active
Output driven High Low
Output active
2
To initiate a save or restore using I C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5907 will
not generate Acknowledge bits. The 5P49V5907 will
1
1
1
0
0
0
0
1
1
x
0
1
0
0
0
Tri-state2
Output active
Output active
1
1
1
1
1
1
0
1
1
x
0
1
0
0
0
Tri-state2
acknowledge the instructions after it has completed execution
Output active
Output driven High Low
Output driven High Low 1
2
of them. During that time, the I C bus should be interpreted as
busy by all other users of the bus.
1
x
x
x
1
On power-up of the 5P49V5907, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5907 will be ready to
accept a programming instruction once it acknowledges its
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
2
7-bit I C address.
Output Divides
2
Availability of Primary and Secondary I C addresses to allow
Each output divide block has a synchronizing POR pulse to
provide startup alignment between outputs divides. This
allows alignment of outputs for low skew performance. This
low skew would also be realized between outputs that are
both integer divides from the VCO frequency. This phase
alignment works when using configuration with SEL1, SEL0.
2
programming for multiple devices in a system. The I C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
2
Programming Guide provides detailed I C programming
guidelines and register map.
2
2
For I C programming, I C reset is required.
SD/OE Pin Function
An output divide bypass mode (divide by 1) will also be
provided, to allow multiple buffered reference outputs.
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD.
Each of the four output divides are comprised of a 12 bit
integer counter, and a 24 bit fractional counter. The output
divide can operate in integer divide only mode for improved
performance, or utilize the fractional counters to generate a
clock frequency accurate to 50 ppb.
Each of the output divides also have structures capable of
independently generating spread spectrum modulation on the
frequency output.
SP
OUTn
SD/OE Input
The Output Divide also has the capability to apply a spread
modulation to the output frequency. Independent of output
frequency, a triangle wave modulation between 30 and 63kHz
may be generated.
OEn
Global Shutdown
OSn
SH
For all outputs, there is a bypass mode, to allow the output to
behave as a buffered copy of the input.
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
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Output Skew
Device Start-up & Reset Behavior
For outputs that share a common output divide value, there
will be the ability to skew outputs by quadrature values to
minimize interaction on the PCB. The skew on each output
can be adjusted from 0 to 360 degrees. Skew is adjusted in
units equal to 1/32 of the VCO period. So, for 100 MHz output
and a 2800 MHz VCO, you can select how many 11.161pS
units you want added to your skew (resulting in units of 0.402
degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so
on. The granularity of the skew adjustment is always
The 5P49V5907 has an internal power-up reset (POR) circuit.
The POR circuit will remain active for a maximum of 10ms
after device power-up.
Upon internal POR circuit expiring, the device will exit reset
and begin self-configuration.
The device will load internal registers using the configuration
stored in the internal One-Time Programmable (OTP)
memory.
dependent on the VCO period and the output period.
Output Drivers
Once the full configuration has been loaded, the device will
respond to accesses on the serial port and will attempt to lock
the PLL to the selected source and begin operation.
The OUT1 to OUT4 clock outputs are provided with
register-controlled output drivers. By selecting the output drive
type in the appropriate register, any of these outputs can
support LVCMOS, LVPECL, HCSL or LVDS logic levels
Power Up Ramp Sequence
The operating voltage ranges of each output is determined by
VDDA and VDD must ramp up together. VDD0-1, VDDO4,
VDD_CORE and VDDO must ramp up before, or concurrently
with, VDDA and VDD. All power supply pins must be
connected to a power rail even if the output is unused. All
power supplies must ramp in a linear fashion and ramp
monotonically.
its independent output power pin (V
) and thus each can
DDO
have different output voltage levels. Output voltage levels of
2.5V or 3.3V are supported for differential HCSL, LVPECL
operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS
and differential LVDS operation.
Each output may be enabled or disabled by register bits.
When disabled an output will be in a logic 0 state as
determined by the programming bit table shown on page 6.
VDD0-1, VDDO4,
VDD_CORE and VDDO
LVCMOS Operation
When a given output is configured to provide LVCMOS levels,
then both the OUTx and OUTxB outputs will toggle at the
selected output frequency. All the previously described
configuration and control apply equally to both outputs.
Frequency, phase alignment, voltage levels and enable /
disable status apply to both the OUTx and OUTxB pins. The
OUTx and OUTxB outputs can be selected to be
VDD
phase-aligned with each other or inverted relative to one
another by register programming bits. Selection of
phase-alignment may have negative effects on the phase
noise performance of any part of the device due to increased
simultaneous switching noise within the device.
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
2
I C Mode Operation
2
The device acts as a slave device on the I C bus using one of
2
the two I C addresses (0xD0 or 0xD4) to allow multiple
devices to be used in the system. The interface accepts
byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest
byte (most significant bit first). Read and write block transfers
can be stopped after any complete byte transfer. During a
write operation, data will not be moved into the registers until
the STOP bit is received, at which point, all data received in
the block write will be written simultaneously.
2
For full electrical I C compliance, it is recommended to use
external pull-up resistors for SDATA and SCLK. The internal
pull-down resistors have a size of 100k typical.
Current Read
S
Dev Addr + R
A
A
A
Data 0
A
Data 1
A
A
Data n
Data 0
A
Abar
A
P
Sequential Read
S
Dev Addr + W
Reg start Addr
Reg start Addr
A
A
Sr
Dev Addr + R
A
Data 1
A
A
Data n
Abar
P
Sequential Write
S
Dev Addr + W
Data 0
A
Data 1
A
Data n
A
P
S = start
from master to slave
from slave to master
Sr = repeated start
A = acknowledge
Abar= none acknowledge
P = stop
I2C Slave Read and Write Cycle Sequencing
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Table 5: I2C Bus DC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
For SEL1/SDA pin
and SEL0/SCL pin.
For SEL1/SDA pin
and SEL0/SCL pin.
5.5 2
VIH
Input HIGH Level
Input LOW Level
0.7xVDDD
V
VIL
GND-0.3
0.3xVDDD
V
VHYS
IIN
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
0.05xVDDD
-1
V
µA
V
30
VOL
IOL = 3 mA
0.4
Table 6: I2C Bus AC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
FSCLK
Serial Clock Frequency (SCL)
10
400
kHz
µs
µs
µs
ns
µs
µs
pF
ns
ns
µs
µs
µs
tBUF
Bus free time between STOP and START
1.3
0.6
0.6
100
0
tSU:START Setup Time, START
tHD:START Hold Time, START
tSU:DATA
tHD:DATA
tOVD
Setup Time, data input (SDA)
Hold Time, data input (SDA) 1
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCL)
Fall Time, data and clock (SDA, SCL)
HIGH Time, clock (SCL)
0.9
400
300
300
CB
tR
20 + 0.1xCB
tF
20 + 0.1xCB
tHIGH
tLOW
0.6
1.3
0.6
LOW Time, clock (SCL)
tSU:STOP
Setup Time, STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V (MIN) of the SCL signal) to bridge the undefined region of the falling edge
IH
of SCL.
Note 2: I2C inputs are 5V tolerant.
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Table 7: Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5P49V5907. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Item
Rating
Supply Voltage, VDDA, VDDO
3.465V
Inputs
XIN/REF
0V to 1.2V voltage swing
-0.5V to VDDO+ 0.5V
10mA
Outputs, VDDO (LVCMOS)
Outputs, IO (SDA)
Package Thermal Impedance,
Package Thermal Impedance,
Storage Temperature, TSTG
ESD Human Body Model
Junction Temperature
42°C/W (0 mps)
41.8°C/W (0 mps)
-65°C to 150°C
2000V
ΘJA
ΘJC
125°C
Table 8: Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDx
Power supply voltage for supporting 1.8V outputs
Analog power supply voltage. Use filtered analog power
supply if available.
1.71
1.8
1.89
V
VDDA
1.71
-40
1.89
V
TA
CLOAD_OUT
FIN
Operating temperature, ambient
85
15
40
°C
pF
Maximum load capacitance (3.3V LVCMOS only)
External reference crystal
8
MHz
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
tPU
0.05
5
ms
Table 9: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down
Resistance (T = +25 °C)
A
Symbol
Parameter
Min
Typ
Max
7
Unit
pF
Input Capacitance (SD/OE, SEL1/SDA, SEL0/SCL)
CIN
3
Pull-down Resistor
100
300
kΩ
LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)
Programmable capacitance at XIN/REF
ROUT
17
Ω
XIN/REF
XOUT
9
9
25
25
pF
pF
Programmable capacitance at XOUT
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Table 10: Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical Maximum
Fundamental
25
Units
8
40
100
7
MHz
Ω
pF
10
Load Capacitance (CL) @ <=25 MHz
Load Capacitance (CL) >25M to 40M
Maximum Crystal Drive Level
6
6
8
12
8
100
pF
pF
µW
Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.
Table 11: DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
100 MHz on all outputs, 25 MHz
REFCLK
Iddcore3
Core Supply Current
43
42
37
18
17
16
29
28
16
14
12
36
27
16
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LVPECL, 350 MHz, 3.3V VDDOx
LVPECL, 350 MHz, 2.5V VDDOx
LVDS, 350 MHz, 3.3V VDDOx
47
42
21
20
19
33
33
18
16
14
42
32
19
14
LVDS, 350 MHz, 2.5V VDDOx
LVDS, 350 MHz, 1.8V VDDOx
HCSL, 250 MHz, 3.3V VDDOx, 2 pF load
HCSL, 250 MHz, 2.5V VDDOx, 2 pF load
Iddox
Output Buffer Supply Current
1,2
LVCMOS, 50 MHz, 3.3V, VDDOx
1,2
LVCMOS, 50 MHz, 2.5V, VDDOx
1,2
LVCMOS, 50 MHz, 1.8V, VDDOx
LVCMOS, 200 MHz, 3.3V VDDOx1
LVCMOS, 200 MHz, 2.5V VDDOx1,2
LVCMOS, 200 MHz, 1.8V VDDOx1,2
SD asserted, I2C Programming
Iddpd
Power Down Current
1. Single CMOS driver active.
2. Measured into a 5” 50 Ohm trace with 2 pF load.
3. Iddcore = IddA+ IddD, no loads.
Output Features and Descriptions
OUT1/OUT1B, OUT2/OUT2B, and OUT4/OUT4B can form three output pairs. Each output pair has individually programmable
frequencies and can be configured as one differential pair (LVDS, LVPECL, regular HCSL) or two LVCMOS outputs. VDDO is
individually selectable from 1.8V to 3.3V for LVDS and LVCMOS, and 2.5V to 3.3V for LVPECL and regular current-mode HCSL
outputs. OUT3, 5-7 are four Low-Power HCSL(LP-HCSL) differential output pairs. They are the same frequency which can be
individually programmed. They utilize the 1.8V LP-HCSL technology which can reduce supply current and termination resistor
count. LP-HCSL outputs are from 1MHz to 200MHz and other differential outputs are from 1MHz to 350MHz.
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1
Table 12: DC Electrical Characteristics for 3.3V LVCMOS (V
= 3.3V±5%, TA = -40°C to +85°C)
DDO
Min
2.4
Symbol
VOH
VOL
IOZDD
IOZDD
VIH
Parameter
Test Conditions
Typ
Max
Unit
V
IOH = -15mA
Output HIGH Voltage
Output LOW Voltage
Output Leakage Current (OUT1,2,4)
Output Leakage Current (OUT0)
Input HIGH Voltage
VDDO
IOL = 15mA
0.4
V
Tri-state outputs, VDDO = 3.465V
Tri-state outputs, VDDO = 3.465V
Single-ended inputs - SD/OE
Single-ended inputs - SD/OE
Single-ended input OUT0_SEL_I2CB
Single-ended input OUT0_SEL_I2CB
Single-ended input - XIN/REF
Single-ended input - XIN/REF
SD/OE, SEL1/SDA, SEL0/SCL
5
30
µA
µA
V
0.7xVDDD
GND - 0.3
2
VDDD + 0.3
0.3xVDDD
VDDO0 + 0.3
0.4
VIL
Input LOW Voltage
V
VIH
Input HIGH Voltage
V
VIL
Input LOW Voltage
GND - 0.3
0.8
V
VIH
Input HIGH Voltage
1.2
V
VIL
Input LOW Voltage
GND - 0.3
0.4
V
TR/TF
Input Rise/Fall Time
300
nS
1. See “Recommended Operating Conditions” table.
Table 13: DC Electrical Characteristics for 2.5V LVCMOS (V
= 2.5V±5%, TA = -40°C to +85°C)
DDO
Symbol
VOH
VOL
IOZDD
IOZDD
VIH
Parameter
Test Conditions
Min
Typ
Max
Unit
V
IOH = -12mA
Output HIGH Voltage
Output LOW Voltage
Output Leakage Current (OUT1,2,4)
Output Leakage Current (OUT0)
Input HIGH Voltage
0.7xVDDO
IOL = 12mA
0.4
V
Tri-state outputs, VDDO = 2.625V
Tri-state outputs, VDDO = 2.625V
Single-ended inputs - SD/OE
Single-ended inputs - SD/OE
Single-ended input OUT0_SEL_I2CB
Single-ended input OUT0_SEL_I2CB
Single-ended input - XIN/REF
Single-ended input - XIN/REF
SD/OE, SEL1/SDA, SEL0/SCL
5
30
µA
µA
V
0.7xVDDD
GND - 0.3
1.7
VDDD + 0.3
0.3xVDDD
VDDO0 + 0.3
0.4
VIL
Input LOW Voltage
V
VIH
Input HIGH Voltage
V
VIL
Input LOW Voltage
GND - 0.3
0.8
V
VIH
Input HIGH Voltage
1.2
V
VIL
Input LOW Voltage
GND - 0.3
0.4
V
TR/TF
Input Rise/Fall Time
300
nS
Table 14: DC Electrical Characteristics for 1.8V LVCMOS (V
= 1.8V±5%, TA = -40°C to +85°C)
DDO
Symbol
Parameter
Test Conditions
IOH = -8mA
Min
Typ
Max
VDDO
Unit
V
VOH
Output HIGH Voltage
Output LOW Voltage
0.7 xVDDO
IOL = 8mA
VOL
0.25 x VDDO
V
Tri-state outputs, VDDO = 3.465V
Tri-state outputs, VDDO = 3.465V
Single-ended inputs - SD/OE
Output Leakage Current (OUT1,2,4)
Output Leakage Current (OUT0)
Input HIGH Voltage
5
30
IOZDD
µA
VIH
VIL
0.7 * VDDD
GND - 0.3
0.65 * VDDO
GND - 0.3
0.8
VDDD + 0.3
0.3 * VDDD
VDDO0 + 0.3
0.4
V
V
Single-ended inputs - SD/OE
Single-ended input OUT0_SEL_I2CB
Single-ended input OUT0_SEL_I2CB
Single-ended input - XIN/REF
Single-ended input - XIN/REF
SEL0/SCL
Input LOW Voltage
VIH
VIL
Input HIGH Voltage
0
V
Input LOW Voltage
V
VIH
VIL
Input HIGH Voltage
1.2
V
Input LOW Voltage
GND - 0.3
0.4
V
TR/TF
Input Rise/Fall Time
300
nS
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Table 15: DC Electrical Characteristics for LVDS(V
= 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)
DDO
Symbol
Parameter
Min
247
Typ
Max
454
-454
50
Unit
mV
mV
mV
V
Differential Output Voltage for the TRUE binary state
Differential Output Voltage for the FALSE binary state
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
V
(+)
(-)
OT
V
-247
OT
V
OT
V
1.125
1.25
1.375
50
OS
Change in VOS between Complimentary Output States
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO
V
mV
mA
mA
OS
I
9
6
24
OS
Differential Outputs Short Circuit Current, VOUT+ = VOUT
-
I
12
OSD
Table 16: DC Electrical Characteristics for LVDS (V
= 1.8V+5%, TA = -40°C to +85°C)
DDO
Symbol Parameter
Min
247
Typ
Max
454
-454
50
Unit
mV
mV
mV
V
V
V
OT (+)
OT (-)
Differential Output Voltage for the TRUE binary state
Differential Output Voltage for the FALSE binary state
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
-247
∆VOT
VOS
0.8
0.875
0.95
50
∆VOS
IOS
Change in VOS between Complimentary Output States
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDD
mV
mA
mA
9
6
24
IOSD
Differential Outputs Short Circuit Current, VOUT+ = VOUT
-
12
Table 17: DC Electrical Characteristics for LVPECL (V
+85°C)
= 3.3V+5% or 2.5V+5%, TA = -40°C to
DDO
Symbol
Parameter
Min
Typ
Max
Unit
V
Output Voltage HIGH, terminated through 50 tied to VDD - 2 V
Output Voltage LOW, terminated through 50 tied to VDD - 2 V
Peak-to-Peak Output Voltage Swing
V
V
- 1.19
- 1.94
V
- 0.69
DDO
OH
DDO
DDO
V
V
V
- 1.4
DDO
V
OL
V
0.55
0.993
V
SWING
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Table 18: Electrical Characteristics – DIF 0.7V Regular HCSL Outputs (TA = -40°C to +85°C)
(For OUT1, OUT2 and OUT4 programmable differential output pairs when configured as HCSL outputs)
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Trf
CONDITIONS
MIN
1
TYP MAX UNITS NOTES
V/ns
%
Slew rate
Slew rate matching
Scope averaging on
Slew rate matching, Scope averaging on
4
20
1, 2, 3
1, 2, 4
Trf
Δ
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Voltage High
Voltage Low
VHIGH
660
850
1,7
1,7
mV
VLOW
-150
150
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Vmax
Vmin
Vswing
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
1150
1
1
mV
-300
300
250
mV
mV
mV
1,2,7
1,5,7
1, 6
Vcross_abs
Scope averaging off
Scope averaging off
550
140
Crossing Voltage (var)
-Vcross
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
∆
-
absolute) allowed. The intent is to limit Vcross induced modulation by setting Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
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Table 19: Electrical Characteristics–Low Power HCSL (LP-HCSL) Outputs
(For OUT3 and OUT5–7 LP-HCSL differential output pairs.)
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
SYMBOL
tRF
CONDITIONS
Scope averaging on
MIN
1
TYP
2.5
7
MAX
4
UNITS
V/ns
%
NOTES
1,2,3
1,2,4
7
Slew rate matching
Voltage High
dV/dt
Slew rate matching, Scope averaging on
20
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
660
0
850
mV
Voltage Low
VLOW
-150
0
150
7
Max Voltage
Min Voltage
Vswing
Vmax
Vmin
0
0
0
1150
7
7
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
-300
300
Vswing
Scope averaging off
Scope averaging off
Scope averaging off
mV
mV
mV
1,2
Crossing Voltage (abs) Vcross_abs
250
0
0
550
140
1,5
1,6
Crossing Voltage (var) ∆-Vcross
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge
(i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)
allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
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Table 20: AC Timing Electrical Characteristics (V
= 1.8V ±5%, TA = -40°C to +85°C)
DDO
(Spread Spectrum Generation = OFF)
Symbol
Min.
Typ.
Max.
40
Units
MHz
MHz
Parameter
Test Conditions
8
1
Input frequency limit (XIN)
Input frequency limit (REF)
1
fIN
Input Frequency
200
200
350
2900
150
0.9
1
Single ended clock output limit (LVCMOS)
Differential clock output limit
fOUT
Output Frequency
MHz
1
fVCO
fPFD
fBW
t2
VCO Frequency
PFD Frequency
Loop Bandwidth
Input Duty Cycle
2500
MHz
MHz
MHz
%
VCO operating frequency range
PFD operating frequency range
Input frequency = 25MHz
1 1
0.06
45
55
Duty Cycle
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX= 2.5V or
3.3V
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX=1.8V
Measured at VDD/2, Reference output
OUT0 (5MHz - 120MHz) with 50% duty
cycle input
45
40
40
50
50
50
55
60
60
%
%
%
t3 5
Output Duty Cycle
Measured at VDD/2, Reference output
OUT0 (150.1MHz - 200MHz) with 50% duty
cycle input
30
50
70
%
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Rise Times
2.2
2.3
2.4
2.7
1.3
1.4
1.4
1.7
0.7
0.8
0.9
1.2
300
300
400
400
1.0
1.2
1.3
1.7
0.6
0.7
0.6
1.0
0.3
0.4
0.4
0.7
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=3.3V
Single-ended 2.5V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=2.5V
t4 2
V/ns
Single-ended 1.8V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=1.8V
LVDS, 20% to 80%
LVDS, 80% to 20%
LVPECL, 20% to 80%
LVPECL, 80% to 20%
Fall Times
t5
ps
Rise Times
Fall Times
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Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
differential outputs
46
74
ps
ps
ps
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
LVCMOS outputs
t6
Clock Jitter
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
25 MHz LVCMOS outputs
0.5
RMS Phase Jitter (12kHz to 20MHz
integration range) differential output, 25MHz
crystal, 156.25MHz output frequency
0.75
75
1.5
84
ps
Skew between the same frequencies , with
outputs using the same driver format and
phase delay set to 0 ns.
Skew between outputs at same frequency
and conditions
Output Skew between OUT1,
OUT2, OUT4
ps
ps
t7
Output Skew between OUT3
and OUT5-11
49.5
PLL lock time from power-up, measured
after all VDD's have raised above 90% of
their target value.
t8 3
t9 4
Startup Time
10
2
ms
ms
Startup Time
PLL lock time from shutdown mode
1. Practical low er frequency is determined by loop filter settings.
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/w rite time.
4. Actual PLL lock time depends on the loop configuration.
5. Duty Cycle is only guaranteed at max slew rate settings.
Table 21: PCI Express Jitter Specifications (V
(For regular HCSL (OUT1, OUT2 and OUT4) outputs)
= 3.3V±5% or 2.5V±5%, T = -40°C to +85°C)
DDO
A
PCIe Industry
Specification
Symbol
Parameter
Conditions
Min
Typ
Max
Units Notes
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
Phase Jitter Peak-
to-Peak
tJ (PCIe Gen1)
30
86
ps
ps
1,4
2,4
ƒ = 100MHz, 25MHz Crystal Input High
Phase Jitter RMS Band: 1.5MHz - Nyquist (clock
frequency/2)
tREFCLK_HF_RMS
(PCIe Gen2)
2.56
3.10
tREFCLK_LF_RMS
(PCIe Gen2)
ƒ = 100MHz, 25MHz Crystal Input Low
Phase Jitter RMS
0.27
0.8
3.0
1.0
ps
ps
2,4
3,4
Band: 10kHz - 1.5MHz
ƒ = 100MHz, 25MHz Crystal Input
tREFCLK_RMS
(PCIe Gen3)
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
Phase Jitter RMS
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained
transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.
2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation
band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
(High Band) and 3.0ps RMS for t
(Low Band).
REFCLK_HF_RMS
REFCLK_LF_RMS
3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is
subject to change pending the final release version of the specification.
4. This parameter is guaranteed by characterization. Not tested in production.
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Table 22: PCI Express Jitter Specifications (V
(For LP-HCSL (OUT3, OUT5-7) outputs.)
= 1.8V +5%, T = -40°C to +85°C)
DDO
A
PCIe Industry
Specification
Symbol
Parameter
Conditions
Min
Typ
Max
Units Notes
ƒ = 100MHz, 25MHz Crystal Input
Phase Jitter Peak- Evaluation Band: 0Hz - Nyquist (clock
tJ (PCIe Gen1)
to-Peak
frequency/2)
23.85
86
ps
1,4
ƒ = 100MHz, 25MHz Crystal Input High
Band: 1.5MHz - Nyquist (clock
frequency/2)
tREFCLK_HF_RMS
(PCIe Gen2)
Phase Jitter RMS
Phase Jitter RMS
1.83
0.54
3.1
3
ps
ps
2,4
2,4
tREFCLK_LF_RMS
(PCIe Gen2)
ƒ = 100MHz, 25MHz Crystal Input Low
Band: 10kHz - 1.5MHz
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
tREFCLK_RMS
(PCIe Gen3)
Phase Jitter RMS
0.51
1
ps
3,4
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained
transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.
2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation
band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
(High Band) and 3.0ps RMS for t
(Low Band).
REFCLK_HF_RMS
REFCLK_LF_RMS
3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is
subject to change pending the final release version of the specification.
4. This parameter is guaranteed by characterization. Not tested in production.
Table 23: Spread Spectrum Generation Specifications
Symbol Parameter
fOUT Output Frequency
fMOD
Description
Min
Typ
Max
Unit
MHz
kHz
Output Frequency Range
1
300
Mod Frequency
Spread Value
Modulation Frequency
30 to 63
Amount of Spread Value (programmable) - Center Spread
Amount of Spread Value (programmable) - Down Spread
±0.25% to ±2.5%
-0.5% to -5%
fSPREAD
%fOUT
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5P49V5907 DATASHEET
5P49V5907 Reference Schematic
2
2
1
1
1
1
2
2
E P A D
4 9
E P A D
4 8
4 7
E P A D
E P A D
4 6
4 5
E P A D
E P A D
4 4
4 3
E P A D
E P A D
4 2
E P A D
4 1
1
1
1
1
2
2
2
2
1
1
1
2
2
2
1
2
2
1
2
2
1
1
1
2
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19
PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
Test Circuits and Loads
VDDOx
VDDD
VDDA
OUTx
CLKOUT
0.1µF
0.1µF
0.1µF
CL
GND
HCSL Differential Output Test Load
Zo=100ohm differential
33
2pF
2pF
33
50
50
HCSL Output
Low-Power Differential Output Test Load
5 inches
Rs
Rs
Zo=100ohm
2pF
2pF
Alternate Differential Output Terminations
Rs
33
27
Zo
100
85
Units
Ohms
Test Circuits and Loads for Outputs
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5P49V5907 DATASHEET
Typical Phase Noise at 100MHz (3.3V, 25°C)
NOTE: All outputs operational at 100MHz, Phase Noise Plot with Spurs On.
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
Overdriving the XIN/REF Interface
This configuration has three properties; the total output
impedance of Ro and Rs matches the 50 ohm transmission
line impedance, the Vrx voltage is generated at the CLKIN
inputs which maintains the LVCMOS driver voltage level
across the transmission line for best S/N and the R1-R2
voltage divider values ensure that the clock level at XIN is less
than the maximum value of 1.2V.
LVCMOS Driver
The XIN/REF input can be overdriven by an LVCMOS driver
or by one side of a differential driver through an AC coupling
capacitor. The XOUT pin can be left floating. The amplitude of
the input signal should be between 500mV and 1.2V and the
slew rate should not be less than 0.2V/ns. Figure General
Diagram for LVCMOS Driver to XTALInput Interface shows an
example of the interface diagram for a LVCMOS driver.
VDD
XOUT
C3
Ro
Rs
Zo = 50 Ohm
R1
V_XIN
XIN / REF
Ro + Rs
LVCMOS
=
50 ohms
0. 1 uF
R2
General Diagram for LVCMOS Driver to XTAL Input Interface
Table 24Nominal Voltage Divider Values vs LVCMOS VDD for
XIN shows resistor values that ensure the maximum drive
level for the XIN/REF port is not exceeded for all combinations
of 5% tolerance on the driver VDD, the VersaClock VDDAand
5% resistor tolerances. The values of the resistors can be
adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the voltage divider attenuation
as long as the minimum drive level is maintained over all
tolerances. To assist this assessment, the total load on the
driver is included in the table.
Table 24: Nominal Voltage Divider Values vs LVCMOS VDD for XIN
LVCMOS Driver VDD
Ro+Rs
50.0
R1
130
100
62
R2
75
V_XIN (peak)
Ro+Rs+R1+R2
3.3
2.5
1.8
0.97
1.00
0.97
255
250
242
50.0
100
130
50.0
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5P49V5907 DATASHEET
LVPECL Driver
Figure General Diagram for LVPECL Driver to XTAL Input
Interface shows an example of the interface diagram for a
+3.3V LVPECL driver. This is a standard LVPECL termination
with one side of the driver feeding the XIN/REF input. It is
recommended that all components in the schematics be
placed in the layout; though some components might not be
used, they can be utilized for debugging purposes. The
datasheet specifications are characterized and guaranteed by
using a quartz crystal as the input. If the driver is 2.5V
LVPECL, the only change necessary is to use the appropriate
value of R3.
XOUT
C1
Zo = 50 Ohm
XIN / REF
0. 1 uF
Zo = 50 Ohm
R1
50
R2
50
+3.3V LVPECL Dr iv er
R3
50
Table 25 Nominal Voltage Divider Values vs Driver VDD
shows resistor values that ensure the maximum drive level for
the CLKIN port is not exceeded for all combinations of 5%
tolerance on the driver VDD, the VersaClock Vddo_0 and 5%
resistor tolerances. The values of the resistors can be
adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the impedance of the R1-R2
divider. To assist this assessment, the total load on the driver
is included in the table.
Table 25: Nominal Voltage Divider Values vs Driver VDD
LVCMOS Driver VDD
Ro+Rs
50.0
R1
130
100
62
R2
75
Vrx (peak)
0.97
Ro+Rs+R1+R2
3.3
2.5
1.8
255
250
242
50.0
100
130
1.00
50.0
0.97
NOVEMBER 11, 2016
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
common mode noise. The capacitor value should be
approximately 50pF. In addition, since these outputs are LVDS
compatible, the input receiver's amplitude and common-mode
input range should be verified for compatibility with the IDT
LVDS output. If using a non-standard termination, it is
recommended to contact IDT and confirm that the termination
will function as intended. For example, the LVDS outputs
cannot be AC coupled by placing capacitors between the
LVDS outputs and the 100 ohm shunt load. If AC coupling is
required, the coupling caps must be placed between the 100
ohm shunt termination and the receiver. In this manner the
termination of the LVDS output remains DC coupled
termination impedance (Z ) is between 90. and 132. The
T
actual value should be selected to match the differential
impedance (Zo) of your transmission line. A typical
point-to-point LVDS design uses a 100 parallel resistor at the
receiver and a 100. differential transmission-line
environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must
be placed as close to the receiver as possible. The standard
termination schematic as shown in figure Standard
Termination or the termination of figure Optional Termination
can be used, which uses a center tap capacitance to help filter
Z
Z
T
LVDS
Receiver
O
LVDS
Driver
Z
T
Standard Termination
Z
2
T
Z
Z
T
LVDS
Driver
O
LVDS
Receiver
Z
2
C
T
Optional Termination
PROGRAMMABLE CLOCK GENERATOR
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5P49V5907 DATASHEET
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below
shows the most frequently used Common Clock Architecture
in which a copy of the reference clock is provided to both ends
of the PCI Express Link. In the jitter analysis, the transmit (Tx)
and receive (Rx) serdes PLLs are modeled as well as the
phase interpolator in the receiver. These transfer functions are
called H1, H2, and H3 respectively. The overall system
transfer function at the receiver is:
RMS. The two evaluation ranges for PCI Express Gen 2 are
10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High
Band). The plots show the individual transfer functions as well
as the overall transfer function Ht.
Hts = H3s H1s – H2s
The jitter spectrum seen by the receiver is the result of
applying this system transfer function to the clock spectrum
X(s) and is:
Ys = Xs H3s H1s – H2s
In order to generate time domain jitter numbers, an inverse
Fourier Transform is performed on X(s)*H3(s) * [H1(s) -
H2(s)].
PCIe Gen2A Magnitude of Transfer Function
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and
the evaluation is performed over the entire spectrum. The
transfer function parameters are different from Gen 1 and the
jitter result is reported in RMS.
PCIe Gen1 Magnitude of Transfer Function
For PCI Express Gen2, two transfer functions are defined with
2 evaluation ranges and the final jitter number is reported in
NOVEMBER 11, 2016
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
PCIe Gen3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI
Express Reference Clock Requirements.
Marking Diagram
IDT5P49V59
07BdddNDGI
#YYWW$
LOT
1. “ddd” denotes the dash code.
2. “G” denotes RoHS compliance.
3. “I” denotes industrial temperature.
4. “#” denotes the stepping code.
5. “YYWW” is the two last digits of the year and week that the part was assembled.
6. “$” denotes mark code.
7. “LOT” denotes lot number.
PROGRAMMABLE CLOCK GENERATOR
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5P49V5907 DATASHEET
Package Outline and Package Dimensions NDG40 (40-pin 5 x 5mm VFQFPN)
NOVEMBER 11, 2016
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PROGRAMMABLE CLOCK GENERATOR
5P49V5907 DATASHEET
Package Outline and Package Dimensions NDG40 (40-pin 5 x 5mm VFQFPN), cont.
PROGRAMMABLE CLOCK GENERATOR
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NOVEMBER 11, 2016
5P49V5907 DATASHEET
Ordering Information
Part / Order Number
5P49V5907BdddNDGI
5P49V5907BdddNDGI8
Marking
see page 26
Shipping Packaging
Trays
Package
40-pin VFQFPN
40-pin VFQFPN
Temperature
-40° to +85C
-40° to +85C
Tape and Reel
“ddd” denotes the dash code.
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Revision History
Rev.
A
Date
Originator
B. Chandhoke
B. Chandhoke
Description of Change
06/24/15
07/13/15
Initial release.
B
1. Added conditions text and min/max values for VIH/VIL.
2. Updated 1.8V, 2.5V, and 3.3V VIH/VIL conditions text and min/max values for "Single-ended
inputs - CLKSEL, SD/OE"
3. Changed name of parameter "Lock Time" to "Startup Time"
4. Added IDT and Fox crystal references.
C
D
E
F
10/15/15
11/12/15
09/19/16
10/19/16
11/11/19
B. Chandhoke
B. Chandhoke
Y. Guo
Changed device revision from “A” to “B”.
Updated fVCO, t3, and t4 parameters in AC Characteristics table.
Corrected typo [Ci1 to Cs1] on page 5.
Y. Guo
Removed IDT crystal part number
G
Y. Guo
Corrected typo for the order of t4 Slew Rates
NOVEMBER 11, 2016
29
PROGRAMMABLE CLOCK GENERATOR
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.
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