5T2110NLGI8 [IDT]
PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PQCC68, GREEN, PLASTIC, VFQFP-68;
| 型号： | 5T2110NLGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PQCC68, GREEN, PLASTIC, VFQFP-68 驱动 逻辑集成电路 |
| 文件： | 总24页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT5T2110
2.5V ZERO DELAY PLL
DIFFERENTIAL CLOCK
DRIVER TERACLOCK™
FEATURES:
DESCRIPTION:
• 2.5VDD
The IDT5T2110 is a 2.5V PLL differential clock driver intended for high
performance computing and data-communications applications. The
IDT5T2110hassixdifferentialoutputsinsixbanks, includingadedicated
differential feedback. The redundant input capability allows for a smooth
change over to a secondary clock source when the primary clock source
isabsent.
• 6 differential outputs
• Low skew: 100ps all outputs
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput
bank also allows for a divide-by functionality of 2 or 4.
The5T2110featuresauser-selectable,single-endedordifferentialinputto
sixdifferentialoutputs. Thedifferentialclockdriveralsoactsasatranslatorfrom
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectableinterfaceiscontrolledby3-levelinputsignalsthatmaybehard-wired
toappropriatehigh-mid-lowlevels. Thedifferentialoutputscanbesynchro-
nouslyenabled/disabled.
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• 1.8V / 2.5V LVTTL: up to 250MHz
• HSTL / eHSTL: up to 250MHz
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• 3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and six differen-
tial outputs
• PLL bypass for DC testing
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs
are synchronized with the negative edge of REF.
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in BGA and VFQFPN package
TxS
FUNCTIONALBLOCKDIAGRAM
1sOE
1Q
OMODE
Divide
Select
1Q
1F2:1
2sOE
PE
2Q
PD
FS LOCK
Divide
Select
PLL_EN
2Q
FB
/N
2F2:1
3sOE
3
3
FB/
VREF2
3Q
3Q
DS1:0
Divide
Select
PLL
0
1
REF0
3F2:1
4sOE
5sOE
REF0/
VREF0
0
1
4Q
4Q
Divide
Select
RxS
4F2:1
REF1
REF1/
VREF1
REF_SEL
Divide
Select
5Q
5Q
5F2:1
QFB
Divide
Select
QFB
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
FBF2:1
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2004
1
c
2004 Integrated Device Technology, Inc.
DSC 5982/29
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
2
4
6
8
11
1
3
5
7
9
10
12
VDD
1F2
1sOE
1Q
GND
GND
2Q
2Q
2sOE
2F2
VDDQ
1Q
A
B
A
B
VDD
VDD
VDD
NC
1F1
GND
GND
2F1
NC
VDDQ
VDDQ
VDDQ
3F2
OMODE VDD
VDD
VDD
NC
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
NC
3sOE
3Q
C
D
E
F
C
D
E
F
REF_
GND
SEL
VDD
VDD
VDD
GND
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
REF1
REF1
3F1
3Q
/VREF1
REF0
REF0
VDD
VDDQ
VDDQ
/VREF0
FB
FB
VDD
PE
VDD
GND
GND
GND
GND
FBF1
GND
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
4Q
G
H
G
H
/VREF2
PLL_
PD
EN
VDD
VDD
VDD
NC
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
4F1
NC
GND
GND
GND
5F1
RxS
LOCK
VDD
TxS
VDD
VDD
VDD
VDD
FS
4Q
J
J
K
K
VDDQ
VDDQ
4sOE
4F2
L
L
DS1
FBF2
QFB
QFB
GND
GND
5Q
5Q
5sOE
5F2
VDDQ
M
DS0
M
1
3
4
5
6
7
8
9
10
11
12
2
BGA
TOP VIEW
2
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
PINCONFIGURATION
VDD
3F2
51
50
49
48
47
46
1
REF_SEL
VDD
2
REF1
3sOE
VDDQ
3
4
REF1/VREF1
REF0
VDDQ
5
3Q
REF0/VREF0
6
45
3Q
7
FB
3F1
VDD
44
43
42
FB/VREF2
8
GND
9
VDD
PE
10
11
12
13
14
15
16
17
4F1
4Q
41
40
39
PD
PLL_EN
VDD
4Q
VDDQ
38
VDDQ
4sOE
4F2
RxS
TxS
37
36
35
LOCK
VDD
VDD
VFQFPN
TOP VIEW
3
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Min.
2.5
—
Typ. Max.
Unit
pF
Symbol
Description
Max
–0.5 to +3.6
–0.5 to +3.6
–0.5 to VDDQ +0.5
–0.5 to +3.6
150
Unit
V
VDDQ, VDD Power Supply Voltage(2)
CIN
InputCapacitance
OutputCapacitance
3
3.5
7
VI
Input Voltage
V
COUT
6.3
pF
VO
Output Voltage
V
NOTE:
1. Capacitance applies to all inputs except RxS, TxS, nF[2:1], FBF[2:1],and DS[1:0].
VREF
TJ
Reference Voltage(3)
Junction Temperature
Storage Temperature
V
°C
°C
TSTG
–65 to +165
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
RECOMMENDEDOPERATINGRANGE
Symbol
Description
Min.
–40
2.3
Typ.
+25
2.5
Max.
+85
2.7
Unit
°C
V
TA
AmbientOperatingTemperature
InternalPowerSupplyVoltage
(1)
VDD
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
1.4
1.65
1.5
1.8
1.6
1.95
V
V
(1)
VDDQ
2.5VLVTTLOutputPowerSupplyVoltage
TerminationVoltage
VDD
V
V
VT
VDDQ / 2
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
PINDESCRIPTION
Symbol
I/O
Type
Description
REF[1:0]
I
I
Adjustable(1) Clockinput. REF[1:0] isthe"true"sideofthedifferentialclockinput. Ifoperatinginsingle-endedmode, REF[1:0] istheclockinput.
Adjustable(1)
REF[1:0]/
VREF[1:0]
Complementaryclockinput. REF[1:0]/VREF[1:0] isthe"complementary"sideofREF[1:0] iftheinputisindifferentialmode. Ifoperating
insingle-endedmode,REF[1:0]/VREF[1:0] isleftfloating. Forsingle-endedoperationindifferentialmode,REF[1:0]/VREF[1:0] shouldbeset
tothedesiredtogglevoltageforREF[1:0]:
2.5VLVTTL
1.8VLVTTL,eHSTL
HSTL
VREF =1250mV(SSTL2compatible)
VREF = 900mV
VREF = 750mV
LVEPECL
VREF = 1082mV
FB
I
I
Adjustable(1) Clockinput. FBisthe"true"sideofthedifferentialfeedbackclockinput. Ifoperatinginsingle-endedmode,FBisthedifferentialfeedback
clockinput.
FB/VREF2
Adjustable(1) Complementaryfeedbackclockinput. FB/VREF2isthe"complementary"sideofFBiftheinputisindifferentialmode. Ifoperatinginsingle-
endedmode,FB/VREF2isleftfloating. Forsingle-endedoperationindifferentialmode, FB/VREF2shouldbesettothedesiredtogglevoltage
for FB:
2.5VLVTTL
1.8VLVTTL,eHSTL
HSTL
VREF =1250mV(SSTL2compatible)
VREF = 900mV
VREF = 750mV
LVEPECL
VREF = 1082mV
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
4
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
PINDESCRIPTION,CONTINUED
Symbol
REF_SEL
nsOE
I/O
Type
Description
I
I
LVTTL(1)
LVTTL(1)
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
Synchronousoutputenable. WhennsOEisHIGH,nQandnQaresynchronouslystopped. OMODEselectswhethertheoutputsare
gatedLOW/HIGHortri-stated. WhenOMODEisHIGH,PEdeterminesthelevelatwhichtheoutputsstop. WhenPEisLOW/HIGH,
the nQ is stopped in a HIGH/LOW state, while the nQ is stopped at a LOW/HIGH state. When OMODE is LOW, the outputs are tri-
stated. SetnsOELOWfornormaloperation.
QFB
QFB
nQ
O
O
O
O
I
Adjustable(2) Feedbackclockoutput
Adjustable(2) Complementaryfeedbackclockoutput
Adjustable(2) Clockoutputs
nQ
RxS
Adjustable(2) Complementaryclockoutputs
3-Level(3)
3-Level(3)
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input
TxS
I
Setsthedrivestrengthoftheoutputdriversandfeedbackinputstobe2.5VLVTTL(HIGH),1.8VLVTTL(MID)oreHSTL/HSTL(LOW)
compatible. UsedinconjuctionwithVDDQ tosettheinterfacelevels.
PE
I
LVTTL(1)
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock(hasinternalpull-up).
nF[2:1]
FBF[2:1]
FS
I
I
I
I
I
I
LVTTL(1)
LVTTL(1)
LVTTL(1)
3-Level(3)
LVTTL(1)
LVTTL(1)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank. (See Control Summary table.)
Functionselectinputsfordivide-by-2, divide-by-4, zerodelay, orinvertonthefeedbackbank(SeeControlSummarytable)
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange(SeeVCOFrequencyRangeSelecttable)
3-levelinputsforfeedbackinputdividerselection(SeeDivideSelectiontable)
DS[1:0]
PLL_EN
PD
PLLenable/disablecontrol. SetLOWfornormaloperation. WhenPLL_ENisHIGH,thePLLisdisabledandREF[1:0] goestoalloutputs.
Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, thenQandQFBarestoppedinaHIGH/LOWstate, whilethenQandQFB arestoppedinaLOW/HIGHstate. WhenOMODE
is LOW, the outputs are tri-stated. Set PD HIGH for normal operation.
LOCK
OMODE
VDDQ
O
I
LVTTL
LVTTL(1)
PWR
PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtothe
inputs. Theoutputwillbe2.5VLVTTL. (FormoreinformationonapplicationspecificuseoftheLOCKpin,pleaseseeAN237.)
Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/Disableand
Powerdowntables.)
Powersupplyforoutputbuffers. Whenusing2.5VLVTTL,VDDQshouldbeconnectedtoVDD.
VDD
GND
PWR
PWR
Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry
Ground
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
OUTPUTENABLE/DISABLE
nsOE
OMODE
Output
NormalOperation
Tri-State
VCOFREQUENCYRANGESELECT
FS(1)
LOW
Min.
50
Max.
125
Unit
MHz
MHz
L
H
H
X
L
H
Gated(1)
HIGH
100
250
NOTE:
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (FNOM) always appears at nQ and nQ outputs when they
are operated in their undivided modes. The frequency appearing at the REF[1:0] and
REF[1:0] /VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB
are undivided and DS[1:0] = MM. The frequency of REF[1:0] and REF[1:0] /VREF[1:0]
and FB and FB/VREF2 inputs will be FNOM/2 or FNOM/4 when the part is configured for
frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM.
Using the DS[1:0] inputs allows a different method for frequency multiplication (see
Divide Selection table).
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
is stopped in a HIGH/LOW state while the nQ is stopped at a LOW/HIGH state.
POWERDOWN
PD
H
OMODE
Output
NormalOperation
Tri-State
X
L
L
L
H
Gated(1)
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a
LOW/HIGH state.
5
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
EXTERNALDIFFERENTIALFEEDBACK
By providing a dedicated external differential feedback, the IDT5T2110
An internal loop filter moderates the response of the VCO to the
gives users flexibility with regard to divide selection. The FB and FB/ phase detector. The loop filter transfer function has been chosen to
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0] provide minimal jitter (or frequency variation) while still providing accu-
signals at the phase detector in order to drive the VCO. Phase differ- rate responses to input frequency changes.
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
DIVIDESELECTIONTABLE
(1)
DS [1:0]
LL
Divide-by-n
Permitted Output Divide-by-n connected to FB and FB/VREF2
2
3
1, 2
1
LM
LH
4
1, 2
1, 2
1, 2, 4
1, 2
1
ML
5
MM
M H
HL
1
6
8
H M
H H
10
12
1
1
NOTE:
1. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF[1:0]/VREF[1:0] inputs will be FNOM/N when the parts are configured for
frequency multiplication by using an undivided output for FB and FB/VREF2 and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
CONTROLSUMMARYTABLEFORALL
OUTPUTS
nF2/FBF2
nF1/FBF1
Output Skew
Divide by 2
ZeroDelay
Inverted
L
L
L
H
L
H
H
H
Divide by 4
6
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INPUT/OUTPUTSELECTION(1)
Input
Output
Input
Output
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
eHSTL
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
2.5VLVTTL
HSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
1.8VLVTTL
HSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
HSTL DIF
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the
REF[1:0]/VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2. Differential
(DIF) inputs are used only in differential mode.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
VIHH
Parameter
Test Conditions
Min.
Max
Unit
V
Input HIGH Voltage Level(1)
Input MID Voltage Level(1)
InputLOWVoltageLevel(1)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN = VDD
VDD – 0.4
—
VIMM
VDD/2 – 0.2 VDD/2 + 0.2
V
VILL
—
—
0.4
200
+50
—
V
HIGH Level
MID Level
LOW Level
I3
3-LevelInputDCCurrent
(RxS, TxS, DS[1:0])
VIN = VDD/2
–50
–200
–100
µA
µA
VIN = GND
IPU
Input Pull-Up Current (PE)
VDD = Max., VIN = GND
—
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.
7
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
VDD = 2.7V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
±5
±5
µA
InputLOWCurrent
—
—
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
- 0.7
- 1.2
+3.6
—
V
VIN
VDIF
VCM
VIH
VIL
DCInputVoltage
- 0.3
0.2
V
DCDifferentialVoltage(2,8)
DC Common Mode Input Voltage(3,8)
DC Input HIGH(4,5,8)
DC Input LOW(4,6,8)
Single-EndedReferenceVoltage(4,8)
V
680
750
750
900
mV
mV
mV
mV
VREF + 100
—
—
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
VOX
Output HIGH Voltage
IOH = -8mA
IOH = -100µA
IOL = 8mA
VDDQ - 0.4
VDDQ - 0.1
—
—
V
V
—
0.4
OutputLOWVoltage
IOL = 100µA
—
0.1
Qn/Qn and FB/FB Output Crossing Point
VDDQ/2 - 150
VDDQ/2
VDDQ/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
8
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
15
25
mA
IDDQQ
Quiescent VDDQ Power Supply Current(3)
0.7
50
µA
IDDPD
Power Down Current
0.8
13
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
20
µA/MHz
IDDDQ
ITOT
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
16
25
µA/MHz
mA
CurrentperOutput
Total Power VDD Supply Current(4)
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF
35
55
45
80
55
85
ITOTQ
Total Power VDDQ Supply Current(4)
70
mA
120
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
VDIF
Parameter
Value
Units
InputSignalSwing(1)
1
V
mV
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
750
VTHI
CrossingPoint
1
tR, tF
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
9
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOReHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
VDD = 2.7V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
±5
±5
µA
InputLOWCurrent
—
—
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
- 0.7
- 1.2
+3.6
—
V
VIN
VDIF
VCM
VIH
VIL
DCInputVoltage
- 0.3
0.2
V
DCDifferentialVoltage(2,8)
DC Common Mode Input Voltage(3,8)
DC Input HIGH(4,5,8)
DC Input LOW(4,6,8)
Single-EndedReferenceVoltage(4,8)
V
800
900
900
1000
—
mV
mV
mV
mV
VREF + 100
—
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
VOX
Output HIGH Voltage
IOH = -8mA
IOH = -100µA
IOL = 8mA
VDDQ - 0.4
VDDQ - 0.1
—
—
V
V
—
0.4
OutputLOWVoltage
V
IOL = 100µA
—
0.1
V
Qn/Qn and FB/FB Output Crossing Point
VDDQ/2 - 150
VDDQ/2
VDDQ/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
15
25
mA
IDDQQ
Quiescent VDDQ Power Supply Current(3)
1.7
50
µA
IDDPD
Power Down Current
0.8
13
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
20
µA/MHz
IDDDQ
ITOT
Dynamic VDDQ Power Supply
CurrentperOutput
Total Power VDD Supply Current(4)
VDD = Max., VDDQ = Max., CL = 0pF
20
30
µA/MHz
mA
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
35
55
55
85
ITOTQ
Total Power VDDQ Supply Current(4)
50
75
mA
115
175
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH
10
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
VDIF
Parameter
Value
Units
V
InputSignalSwing(1)
1
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
900
mV
V
VTHI
CrossingPoint
1
tR, tF
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR
LVEPECL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
VDD = 2.7V
VDD = 2.3V, IIN = -18mA
VI = VDDQ/GND
—
—
—
—
±5
±5
µA
InputLOWCurrent
VI = GND/VDDQ
VIK
ClampDiodeVoltage
—
- 0.7
—
- 1.2
3.6
V
VIN
VCM
VREF
VIH
VIL
DCInputVoltage
- 0.3
915
—
V
DC Common Mode Input Voltage(3,5)
Single-EndedReferenceVoltage(4,5)
DC Input HIGH
1082
1082
—
1248
—
mV
mV
mV
mV
1275
555
1620
875
DC Input LOW
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
11
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
DIFFERENTIALINPUTACTESTCONDITIONSFORLVEPECL
Symbol
VDIF
Parameter
Value
Units
mV
mV
V
InputSignalSwing(1)
732
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
1082
CrossingPoint
1
VTHI
tR, tF
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR2.5V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
InputLOWCurrent
ClampDiodeVoltage
DCInputVoltage
VDD = 2.7V
VDD = 2.7V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
—
±5
±5
µA
VIK
VIN
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
+3.6
V
V
- 0.3
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
1.7
—
—
V
V
VIL
0.7
DifferentialInputs
VDIF
VCM
VIH
DCDifferentialVoltage(3,9)
DC Common Mode Input Voltage(4,9)
DC Input HIGH(5,6,9)
DC Input LOW(5,7,9)
Single-EndedReferenceVoltage(5,9)
0.2
1150
—
1350
V
1250
1250
mV
mV
mV
mV
VREF + 100
—
—
VIL
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -12mA
IOH = -100µA
IOL = 12mA
IOL = 100µA
VDDQ - 0.4
VDDQ - 0.1
—
—
—
V
V
V
V
OutputLOWVoltage
0.4
0.1
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and REF[1:0]/VREF[1:0] is left floating. If TxS is HIGH, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
12
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
POWERSUPPLYCHARACTERISTICSFOR2.5VLVTTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
15
25
mA
IDDQQ
Quiescent VDDQ Power Supply Current(3)
12
50
µA
IDDPD
Power Down Current
0.5
15
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
25
µA/MHz
IDDDQ
ITOT
Dynamic VDDQ Power Supply
CurrentperOutput
Total Power VDD Supply Current(4)
VDD = Max., VDDQ = Max., CL = 0pF
30
40
µA/MHz
mA
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF
40
60
60
90
ITOTQ
Total Power VDDQ Supply Current(4)
80
120
300
mA
200
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VDIF
Parameter
Value
VDD
Units
InputSignalSwing(1)
V
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
VDD/2
VTHI
CrossingPoint
2.5
V
tR, tF
V/ns
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF
(AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VIH
Parameter
Value
VDD
0
Units
V
Input HIGH Voltage
VIL
InputLOWVoltage
V
VTHI
InputTimingMeasurementReferenceLevel(1)
InputSignalEdgeRate(2)
VDD/2
2
V
tR, tF
V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
13
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR1.8V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
InputLOWCurrent
ClampDiodeVoltage
DCInputVoltage
VDD = 2.7V
VDD = 2.7V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
—
±5
±5
µA
VIK
VIN
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
V
- 0.3
VDDQ + 0.3
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
1.073(10)
—
—
0.683(11)
V
V
VIL
DifferentialInputs
VDIF
VCM
VIH
DCDifferentialVoltage(3,9)
DC Common Mode Input Voltage(4,9)
DC Input HIGH(5,6,9)
DC Input LOW(5,7,9)
Single-EndedReferenceVoltage(5,9)
0.2
825
—
975
V
900
900
mV
mV
mV
mV
VREF + 100
—
—
VIL
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -6mA
IOH = -100µA
IOL = 6mA
VDDQ - 0.4
VDDQ - 0.1
—
—
—
V
V
V
V
OutputLOWVoltage
0.4
0.1
IOL = 100µA
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and REF[1:0]/VREF[1:0] is left floating. If TxS is MID, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
14
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
POWERSUPPLYCHARACTERISTICSFOR1.8VLVTTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
15
25
mA
IDDQQ
Quiescent VDDQ Power Supply Current(3)
1.5
50
µA
IDDPD
Power Down Current
0.5
16
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
25
µA/MHz
IDDDQ
ITOT
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
22
30
µA/MHz
mA
CurrentperOutput
Total Power VDD Supply Current(4)
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF
40
70
60
105
85
ITOTQ
Total Power VDDQ Supply Current(4)
55
mA
135
205
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VDIF
Parameter
Value
VDDI
Units
InputSignalSwing(1)
V
mV
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
VDDI/2
VTHI
CrossingPoint
1.8
tR, tF
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VIH
Parameter
Value
VDDI
0
Units
V
Input HIGH Voltage(1)
VIL
InputLOWVoltage
V
VTHI
InputTimingMeasurementReferenceLevel(2)
InputSignalEdgeRate(3)
VDDI/2
2
mV
V/ns
tR, tF
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
15
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
FNOM
tRPW
Parameter
Min.
Typ.
Max
Unit
VCO Frequency Range
see VCO Frequency Range Select Table
Reference Clock Pulse Width HIGH or LOW
Feedback Input Pulse Width HIGH or LOW
OutputSkew(Rise-Rise,Fall-Fall,Nominal)(1,2)
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,2,3)
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,2,3)
InvertingSkew(Nominal-Inverted)(1,2)
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,2,3)
Process Skew(1,2,4)
REF Input to FB Static Phase Offset(5)
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
tFPW
tSK(O)
—
—
—
—
—
—
-100
-375
-275
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
300
300
300
300
100
375
275
1.2
1
tSK1(ω)
tSK2(ω)
tSK1(INV)
tSK2(INV)
tSK(PR)
t(φ)
tODCV
Output Duty Cycle Variation from 50%(11,12) 1.8VLVTTL
2.5VLVTTL
tORISE
tOFALL
OutputRiseTime(6)
OutputFallTime(6)
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
ns
ns
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
1.2
1
tL
Power-upPLLLockTime(7)
1
ms
ms
ms
µs
ms
ps
tL(ω)
tL(PD)
PLLLockTimeAfterInputFrequencyChange(7)
PLL Lock Time After Asserting PD Pin(7)
PLL Lock Time After Change in REF_SEL(7,9)
PLLLockTimeAfterChangeinREF_SEL(REF1 andREF0 aredifferentfrequency)(7)
Cycle-to-CycleOutputJitter(peak-to-peak)(2,8)
PeriodJitter(peak-to-peak)(2,8)
HalfPeriodJitter(peak-to-peak)(2,8,10)
1
1
tL(REFSEL1)
tL(REFSEL2)
tJIT(CC)
tJIT(PER)
tJIT(HP)
100
1
75
75
ps
125
100
ps
tJIT(DUTY)
DutyCycleJitter(peak-to-peak)(2,8)
ps
VOX
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel
VDDQ/2 - 150 VDDQ/2 VDDQ/2 + 150 mV
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. For differential LVTTL outputs, the measurement is made at VDDQ/2, where the true outputs are only compared with other true outputs and the complementary outputs are only
compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (VOX) of the true and complementary signals.
3. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
4. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.).
5. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken from VTHI on REF to VTHI on
FB. For TxS/RxS = LOW, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay, FB input divider is set to
divide-by-one, and FS = HIGH.
6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
7. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQ is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
8. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and FS = HIGH.
9. Both REF inputs must be the same frequency, but up to ±180° out of phase.
10. For HSTL/eHSTL outputs only.
11. For LVTTL outputs only.
12. tODCV is measured with all outputs selected for zero delay.
16
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
ACDIFFERENTIALINPUTSPECIFICATIONS(1)
Symbol
Parameter
Min.
Typ.
—
Max
—
Unit
t W
Reference/FeedbackInputClockPulseWidthHIGHorLOW(HSTL/eHSTLoutputs)(2)
Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2)
1
1
ns
—
—
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF
VIH
ACDifferentialVoltage(3)
AC Input HIGH(4,5)
AC Input LOW(4,6)
400
Vx + 200
—
—
—
—
—
—
mV
mV
mV
VIL
Vx - 200
LVEPECL
VDIF
ACDifferentialVoltage(3)
AC Input HIGH(4)
AC Input LOW(4)
400
1275
—
—
—
—
—
—
mV
mV
mV
VIH
VIL
875
NOTES:
1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined
by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.
The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
17
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
AC TIMING DIAGRAM(1)
tRPWL
tRPWH
REF
REF
tFPWH
tFPWL
FB
FB
tODCV
tODCV
Q
Q
tSK(O)
tSK(O)
OTHER Q
OTHER Q
tSK1(INV)
tSK1(INV)
INVERTED Q
INVERTED Q
tSK2(ω),
tSK2(INV)
tSK2(INV)
tSK2(ω)
tSK1(ω)
Q DIVIDED BY 2
Q DIVIDED BY 2
tSK1(ω),
tSK2(INV)
Q DIVIDED BY 4
Q DIVIDED BY 4
NOTE:
1. The AC TIMING DIAGRAM applies to PE = VDD. For PE = GND, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative
edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align.
18
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
JITTERANDOFFSETTIMINGWAVEFORMS
nQ, QFB
nQ, QFB
tcycle n
tcycle n + 1
=
tjit(cc) tcycle n
tcycle n+1
Cycle-to-Cycle jitter
REF[1:0]
REF[1:0]
FB
FB
t(Ø)n + 1
t(Ø)n
n = N
1
(N is a large number of samples)
∑
t(Ø)n
=
t(Ø)
N
Static Phase Offset
NOTE:
1. Diagram for PE = H and TxS/RxS = L.
19
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
JITTERANDOFFSETTIMINGWAVEFORMS
nQ, QFB
nQ, QFB
tW(MIN)
tW(MAX)
tJIT(DUTY) = tW(MAX) - tW(MIN)
Duty-Cycle Jitter
nQ, QFB
nQ, QFB
tcycle n
nQ, QFB
nQ, QFB
1
f
o
1
=
tjit(per)
tcycle n
f
o
Period jitter
nQ, QFB
nQ, QFB
thalf period n+1
thalf period n
nQ, QFB
nQ, QFB
1
f
o
1
2*f
=
tjit(hper) thalf period n
Half-Period jitter
20
o
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
TESTCIRCUITSANDCONDITIONS
VDDI
R1
R2
3 inch, ~50Ω
Transmission Line
VIN
VDDQ
VDD
VDDI
REF[1:0]
D.U.T.
Pulse
Generator
R1
R2
3 inch, ~50Ω
Transmission Line
REF[1:0]
VIN
Test Circuit for Differential Input(1)
DIFFERENTIALINPUTTESTCONDITIONS
Symbol
VDD = 2.5V ± 0.2V
Unit
R1
100
100
Ω
R2
Ω
VDDI
VCM*2
V
HSTL: Crossing of REF[1:0] and REF[1:0]
eHSTL: Crossing of REF[1:0] and REF[1:0]
LVEPECL: Crossing of REF[1:0] and REF[1:0]
1.8V LVTTL: VDDI/2
VTHI
V
2.5V LVTTL: VDD/2
NOTE:
1. This input configuration is used for all input interfaces. For single-ended testing,
the REF[1:0] must be left floating. For testing single-ended in differential input
mode, the VIN should be floating.
21
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
VDDQ
VDD
VDDQ
VDDQ
VDDQ
REF[1:0]
R1
R1
nQ
R2
R1
R2
VDDQ
VDD
CL
D.U.T.
R2
CL
REF[1:0]
nQ
VDDQ
QFB
D.U.T.
FB
FB
QFB
QFB
R1
R2
CL
FB
FB
QFB
CL
SW1
SW1
Test Circuit for Differential Feedback
Test Circuit for Differential Outputs
DIFFERENTIALFEEDBACKTEST
CONDITIONS
DIFFERENTIALOUTPUTTEST
CONDITIONS
Symbol
VDD = 2.5V ± 0.2V
VDDQ = Interface Specified
15
Unit
Symbol
VDD = 2.5V ± 0.2V
VDDQ = Interface Specified
15
Unit
CL
R1
pF
Ω
Ω
V
CL
R1
pF
100
100
Ω
Ω
V
R2
100
R2
100
VOX
HSTL: Crossing of QFB and QFB
eHSTL: Crossing of QFB and QFB
1.8V LVTTL: VDDQ/2
2.5V LVTTL: VDDQ/2
TxS = MID or HIGH
TxS = LOW
VOX
HSTL: Crossing of nQ and nQ
eHSTL: Crossing of nQ and nQ
1.8V LVTTL: VDDQ/2
2.5V LVTTL: VDDQ/2
TxS = MID or HIGH
TxS = LOW
VTHO
V
VTHO
SW1
V
SW1
Open
Open
Closed
Closed
22
IDT5T2110
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
RECOMMENDEDLANDINGPATTERN
NL 68 pin
NOTE: All dimensions are in millimeters.
23
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XXXXX
XX
Package Package
IDT
Device Type
I
-40°C to +85°C (Industrial)
Plastic Ball Grid Array
BB
NL
Thermally Enhanced Plastic Very Fine
Pitch Quad Flat No Lead Package
VFQFPN - Green
NLG
2.5V Zero Delay PLL Differential Clock
Driver Teraclock
5T2110
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(408) 654-6459
24
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