5T93GL061PFGI [IDT]
Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32;
| 型号： | 5T93GL061PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V LVDS 1:6 GLITCHLESS
IDT5T93GL061
CLOCK BUFFER
TERABUFFER™ II
DESCRIPTION:
FEATURES:
The IDT5T93GL061 2.5V differential clock buffer is a user-selectable
• Guaranteed Low Skew < 50ps (max)
• Very low duty cycle distortion < 100ps (max)
• High speed propagation delay < 2.2ns (max)
• Up to 450MHz operation
differentialinputtosixLVDSoutputs. Thefanoutfromadifferentialinputtosix
LVDSoutputsreducesloadingontheprecedingdriverandprovidesanefficient
clockdistributionnetwork. TheIDT5T93GL061canactasatranslatorfroma
differentialHSTL,eHSTL,LVEPECL (2.5V),LVPECL(3.3V),CML,orLVDS
input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be
usedtotranslatetoLVDSoutputs. Theredundantinputcapabilityallowsfora
glitchlesschange-over fromaprimaryclocksourcetoasecondaryclocksource
upto450MHz. SelectableinputsarecontrolledbySEL. Duringtheswitchover,
theoutputwilldisablelowforuptothreeclockcyclesofthepreviously-selected
inputclock. Theoutputswillremainlowforuptothreeclockcyclesofthenewly-
selectedclock,afterwhichtheoutputswillstartfromthenewly-selectedinput.
AFSELpinhasbeenimplementedtocontroltheswitchoverincaseswherea
clocksourceisabsentorisdriventoDClevelsbelowtheminimumspecifications.
The IDT5T93GL061 outputs can be asynchronously enabled/disabled.
Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple
power and grounds reduce noise.
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in TQFP package
APPLICATIONS:
• Clock distribution
FUNCTIONALBLOCKDIAGRAM
GL
G
Q1
OUTPUT
CONTROL
Q1
PD
Q2
Q2
OUTPUT
CONTROL
A1
1
A1
Q3
Q3
OUTPUT
CONTROL
A2
Q4
Q4
OUTPUT
CONTROL
0
A2
Q5
Q5
OUTPUT
CONTROL
SEL
FSEL
Q6
Q6
OUTPUT
CONTROL
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2007
1
© 2007 Integrated Device Technology, Inc.
DSC 6740/7
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
32
30
29 28 27 26 25
31
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PD
G
VDD
VDD
GND
Q4
GND
Q1
Q4
Q1
GND
A2
GND
A1
A2
A1
9
10 11 12 13 14 15 16
TQFP
TOP VIEW
2
IDT5T93GL061
INDUSTRIALTEMPERATURERANGE
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDD
VI
Description
Max
–0.5 to +3.6
–0.5 to +3.6
–0.5 to VDD +0.5
–65 to +150
150
Unit
V
Symbol
Parameter
Min
Typ.
Max.
Unit
Power Supply Voltage
CIN
Input Capacitance
—
—
3
pF
Input Voltage
V
NOTE:
VO
Output Voltage(2)
Storage Temperature
Junction Temperature
V
1. This parameter is measured at characterization but not tested
TSTG
TJ
°C
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Not to exceed 3.6V.
RECOMMENDEDOPERATINGRANGE
Symbol
Description
Min.
–40
2.3
Typ.
+25
2.5
Max.
+85
2.7
Unit
°C
V
TA
AmbientOperatingTemperature
InternalPowerSupplyVoltage
VDD
PINDESCRIPTION
Symbol
A[1:2]
I/O
Type
Description
I
I
Adjustable(1,4) Clockinput. A[1:2] isthe"true"sideofthedifferentialclockinput.
Adjustable(1,4) Complementaryclockinputs. A[1:2] isthecomplementarysideofA[1:2]. ForLVTTLsingle-endedoperation, A[1:2] shouldbesettothe
A[1:2]
desiredtogglevoltageforA[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
G
I
I
LVTTL
LVTTL
GatecontrolfordifferentialoutputsQ1 andQ1 throughQ6 and Q6. WhenGisLOW, thedifferentialoutputsareactive. WhenGis
HIGH,thedifferentialoutputsareasynchronouslydriventotheleveldesignatedbyGL(2).
GL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputsdisableLOWand"complementary"outputsdisableHIGH.
Qn
Qn
SEL
O
O
I
LVDS
LVDS
LVTTL
LVTTL
Clockoutputs
Complementaryclockoutputs
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.
PD
I
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both
"true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)
FSEL
VDD
I
LVTTL
PWR
PWR
At a rising edge, FSEL forces select to the input designated by SEL. Set LOW for normal operation.
Power supply for the device core and inputs
Ground
GND
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-
up after asserting PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
3
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
RANGEFORLVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
—
—
—
—
±5
±5
μA
InputLOWCurrent
VDD = 2.7V
VIK
ClampDiodeVoltage
DCInputVoltage
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
+3.6
—
V
V
V
V
V
V
VIN
VIH
VIL
- 0.3
1.7
—
DC Input HIGH
DC Input LOW
0.7
VTHI
VREF
DCInputThresholdCrossingVoltage
Single-EndedReferenceVoltage(3)
VDD/2
1.65
3.3VLVTTL
2.5VLVTTL
—
—
—
—
1.25
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
DCELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
RANGEFORDIFFERENTIALINPUTS(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(4)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
—
—
—
—
±5
±5
μA
InputLOWCurrent
VDD = 2.7V
VIK
VIN
VDIF
VCM
ClampDiodeVoltage
DCInputVoltage
DCDifferentialVoltage(2)
DC Common Mode Input Voltage(3)
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
+3.6
—
V
V
V
V
- 0.3
0.1
0.05
VDD
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential
voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2.
4. Typical values are at VDD = 2.5V, +25°C ambient.
DCELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
RANGE FOR LVDS(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max
Unit
OutputCharacteristics
VOT(+)
VOT(-)
ΔVOT
VOS
DifferentialOutputVoltagefortheTrueBinaryState
DifferentialOutputVoltagefortheFalseBinaryState
ChangeinVOT BetweenComplementaryOutputStates
OutputCommonModeVoltage(OffsetVoltage)
ChangeinVOS BetweenComplementaryOutputStates
OutputsShortCircuitCurrent
247
247
—
—
—
—
1.2
—
12
6
454
454
50
mV
mV
mV
V
1.125
—
1.375
50
ΔVOS
IOS
mV
mA
mA
VOUT + and VOUT - = 0V
VOUT + = VOUT -
—
24
IOSD
DifferentialOutputsShortCircuitCurrent
—
12
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
4
IDT5T93GL061
INDUSTRIALTEMPERATURERANGE
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
VDIF
VX
Parameter
Value
Units
V
InputSignalSwing(1)
DifferentialInputSignalCrossingPoint(2)
1
750
mV
%
DH
Duty Cycle
50
VTHI
tR, tF
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
CrossingPoint
2
V
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
VDIF
VX
Parameter
Value
Units
V
InputSignalSwing(1)
DifferentialInputSignalCrossingPoint(2)
1
900
mV
%
DH
Duty Cycle
50
VTHI
tR, tF
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
CrossingPoint
2
V
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND
LVPECL(3.3V)
Symbol
VDIF
Parameter
Value
Units
mV
InputSignalSwing(1)
732
VX
DifferentialInputSignalCrossingPoint(2)
LVEPECL
LVPECL
1082
mV
1880
DH
Duty Cycle
50
%
V
VTHI
tR, tF
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
CrossingPoint
2
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
5
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS
Symbol
VDIF
VX
Parameter
Value
Units
mV
V
InputSignalSwing(1)
DifferentialInputSignalCrossingPoint(2)
400
1.2
DH
Duty Cycle
50
%
VTHI
tR, tF
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
CrossingPoint
2
V
V/ns
NOTES:
1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
ACDIFFERENTIALINPUTSPECIFICATIONS(1)
Symbol
VDIF
VIX
Parameter
Min.
0.1
Typ.
—
Max
3.6
Unit
V
ACDifferentialVoltage(2)
DifferentialInputCrosspointVoltage
CommonModeInputVoltageRange(3)
InputVoltage
0.05
0.05
- 0.3
—
VDD
VDD
+3.6
V
VCM
—
V
VIN
V
NOTES:
1. The output will not change state until the inputs have crossed and the minimum differential voltage defined by VDIF has been met or exceeded.
2. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage
must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2.
POWERSUPPLYCHARACTERISTICSFORLVDSOUTPUTS(1)
Symbol
Parameter
Test Conditions
VDD = Max., All Input Clocks = LOW(2)
Outputsenabled
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
—
240
mA
ITOT
IPD
Total Power VDD Supply Current
Total Power Down Supply Current
VDD = 2.7V., FREFERENCE CLOCK = 450MHz
PD = LOW
—
250
5
mA
mA
—
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
2. The true input is held LOW and the complementary input is held HIGH.
6
IDT5T93GL061
INDUSTRIALTEMPERATURERANGE
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(1,5)
Symbol
Parameter
Min.
Typ.
Max
Unit
SkewParameters
tSK(O)
Same Device Output Pin-to-Pin Skew(2)
Pulse Skew(3)
—
—
—
—
—
—
50
ps
ps
ps
tSK(P)
100
300
tSK(PP)
Part-to-PartSkew(4)
PropagationDelay
tPLH
tPHL
fO
Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint
—
1.5
2.2
ns
FrequencyRange(6)
—
—
450
MHz
OutputGateEnable/DisableDelay
tPGE
Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint
—
—
—
—
3.5
3.5
ns
ns
tPGD
Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level
Power Down Timing
tPWRDN
PD Crossing VTHI to Qn = VDD, Qn = VDD
Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level
—
—
—
—
100
100
μS
μS
tPWRUP
NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any single differential output pair under identical input and output interfaces, transitions and load
conditions on any one device.
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions
at identical VDD levels and temperature.
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
7
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
DIFFERENTIALACTIMINGWAVEFORMS
1/fo
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
tPHL
tPLH
+ VDIF
VDIF = 0
- VDIF
Qn - Qn
tSK(O)
tSK(O)
+ VDIF
VDIF = 0
- VDIF
Qm - Qm
Output Propagation and Skew Waveforms
NOTES:
1. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
8
IDT5T93GL061
INDUSTRIALTEMPERATURERANGE
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
VIH
VTHI
VIL
GL
tPLH
VIH
VTHI
VIL
G
tPGE
tPGD
+ VDIF
VDIF = 0
- VDIF
Qn - Qn
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.
+ VDIF
VDIF = 0
- VDIF
A1 - A1
A2 - A2
SEL
+ VDIF
VDIF = 0
- VDIF
VIH
VTHI
VIL
+ VDIF
VDIF = 0
- VDIF
Qn - Qn
Glitchless Output Operation with Switching Input Clock Selection
NOTES:
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays LOW for up to three clock cycles of the
new input clock. After this, the output starts with the rising edge of the new input clock.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
9
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
FSEL Operation for When Current Clock Dies
NOTES:
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the SEL pin should be toggled
and FSEL asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
than or equal to the minimum DC differential specified in the datasheet.
FSEL Operation for When Opposite Clock Dies
NOTES:
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should
be asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
than or equal to the minimum DC differential specified in the datasheet.
10
IDT5T93GL061
INDUSTRIALTEMPERATURERANGE
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
+VDIF
VDIF=0
-VDIF
A1 - A1
A2 - A2
FSEL
SEL
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF=0
-VDIF
Qn - Qn
Selection of Input While Protecting Against When Opposite Clock Dies
NOTES:
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL
pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with
the input clock selected by the SEL pin.
+VDIF
VDIF=0
-VDIF
A1 - A1
A2 - A2
G
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
PD
+VDIF
VDIF=0
-VDIF
Qn - Qn
Power Down Timing
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after
asserting PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn - Qn goes to VDIF = 0.
11
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDCONDITIONS
~50Ω
Transmission Line
VIN
VDD/2
A
D.U.T.
Pulse
Generator
A
~50Ω
Transmission Line
VIN
-VDD/2
Scope
50Ω
50Ω
Test Circuit for Differential Input
DIFFERENTIALINPUTTESTCONDITIONS
Symbol
VDD = 2.5V ± 0.2V
Unit
VTHI
Crossing of A and A
V
12
IDT5T93GL061
INDUSTRIALTEMPERATURERANGE
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
VDD
A
Qn
Qn
Pulse
Generator
RL
RL
A
D.U.T.
VOS
VOD
Test Circuit for DC Outputs and Power Down Tests
VDD/2
SCOPE
CL
Z = 50Ω
A
A
Qn
Pulse
Generator
50Ω
50Ω
D.U.T.
Qn
Z = 50Ω
CL
-VDD/2
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
LVDSOUTPUTTESTCONDITION
Symbol
VDD = 2.5V ± 0.2V
Unit
CL
0(1)
8(1,2)
50
pF
RL
Ω
NOTES:
1. Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only.
2. The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent
load.
13
IDT5T93GL061
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
X
XXXXX
IDT
Package Process
Device Type
I
-40°C to +85°C (Industrial)
Thin Quad Flat Pack
TQFP - Green
PF
PFG
2.5V LVDS 1:6 Glitchless Clock Buffer Terabuffer™ II
5T93GL061
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
clockhelp@idt.com
www.idt.com
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相关型号：
5T93GL061PFGI8
Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32
IDT
5T93GL06NLGI8
Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQCC28, GREEN, PLASTIC, VFQFPN-28
IDT
5T93GL101PFGI8
Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQFP44, GREEN, TQFP-44
IDT
5T93GL161PFGI
Low Skew Clock Driver, 5T Series, 16 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, GREEN, TQFP-64
IDT
5T93GL161PFI
Clock Driver, 5T Series, 16 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, TQFP-64
IDT
5T93GL16NLGI8
Low Skew Clock Driver, 5T Series, 16 True Output(s), 0 Inverted Output(s), PQCC52, GREEN, PLASTIC, QFN-52
IDT
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