5T995PFI [IDT]
Clock Driver, PQFP44;
| 型号： | 5T995PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PQFP44 时钟 驱动 时钟驱动器 |
| 文件： | 总10页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V PROGRAMMABLE
IDT5T995/A
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ II
FEATURES:
DESCRIPTION:
• Ref input is 3.3V tolerant
The IDT5T995 is a high fanout 2.5V PLL based clock driver intended
forhighperformancecomputinganddata-communicationsapplications.A
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag
theREFinputsignal.TheIDT5T995haseightprogrammableskewoutputs
in four banks of 2. Skew is controlled by 3-level input signals that may be
hard-wired to appropriate high-mid-low levels.
• 4 pairs of programmable skew outputs
• Low skew: 185ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Input frequency:
– Std: 2MHz to 160MHz
– A: 2MHz to 200MHz
• Output frequency:
– Std: 6MHz to 160MHz
The feedback input allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronouslydisabled. TheLOCKoutputassertstoindicatewhenPhase
Lock has been achieved.
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs
are synchronized with the negative edge of REF. The IDT5T995 has
LVTTL outputs with 12mA balanced drive outputs.
– A: 6MHz to 200MHz
• 3-level inputs for skew and PLL range control
• 3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <100ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Standard and A speed grades
• Available in TQFP package
PE TEST
FS LOCK
FUNCTIONALBLOCKDIAGRAM
PD
sOE
3
3
REF
FB
PLL
/ N
3
3
DS1:0
1F1:0
1Q0
1Q1
3
3
Skew
Select
3
3
2Q0
2Q1
Skew
2F1:0
3F1:0
4F1:0
Select
3
3
3Q0
3Q1
Skew
Select
3
3
4Q0
4Q1
Skew
Select
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
DECEMBER 2006
1
c
2006 Integrated Device Technology, Inc.
DSC 5850/7
IDT5T995/A
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
–0.5 to +4.6
–0.5 to VDD+0.5
–0.5 to +4.6
0.7
Unit
V
VDDQ, VDD Supply Voltage to Ground
VI
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
V
V
42
38 37 36
34
35
44 43
41 40 39
4F1
sOE
PD
1
2
1F0
TA = 85°C
TA = 55°C
W
33
32
31
30
29
28
27
26
25
24
23
DS1
1.1
DS0
3
TSTG
Storage Temperature Range
–65 to +150
°C
PE
LOCK
VDDQ
VDDQ
1Q0
4
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
VDDQ
VDDQ
4Q1
5
6
7
1Q1
4Q0
8
GND
GND
GND
GND
GND
GND
9
10
11
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ.
Max.
Unit
12 13 14 15
17 18 19 20 21 22
16
CIN
InputCapacitance
5
7
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].
TQFP
TOP VIEW
PINDESCRIPTION
Pin Name
REF
Type
IN
Description
ReferenceClockInput
FeedbackInput
FB
IN
TEST(1)
IN
WhenMIDorHIGH, disablesPLL(exceptforconditionsofNote1). REFgoestoalloutputs. SkewSelections(SeeControlSummary
Table)remainineffect. SetLOWfornormaloperation.
sOE(1)
IN
IN
SynchronousOutputEnable. WhenHIGH,itstopsclockoutputs(except2Q0 and2Q1)inaLOWstate(forPE=H)-2Q0 and2Q1may
beusedasthefeedbacksignaltomaintainphaselock. WhenTESTisheldatMIDlevelandsOEisHIGH,thenF[1:0]pinsactasoutput
disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).
PE
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock(hasinternalpull-up).
nF[1:0]
FS
IN
IN
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeeProgrammableSkewRange.)
Fourbanksoftwooutputswithprogrammableskew
nQ[1:0]
DS[1:0]
PD
OUT
IN
3-levelinputsforfeedbackdividerselection
IN
Powerdowncontrol. ShutsoffentirechipwhenLOW(hasinternalpull-up).
PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtothe
inputs. (FormoreinformationonapplicationspecificuseoftheLOCKpin,pleaseseeAN237.)
Powersupplyforoutputbuffers
LOCK
OUT
VDDQ
VDD
PWR
PWR
PWR
Powersupplyforphaselockedloop,lockoutput,andotherinternalcircuitry
Ground
GND
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
2
IDT5T995/A
INDUSTRIALTEMPERATURERANGE
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate figurations are chosen by the nF1:0 control pins. In order to minimize the
for PCB trace delays, backplane propagation delays or to accommodate number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they
requirements for special timing relationships between clocked compo- are intended for but not restricted to hard-wiring. Undriven 3-level in-
nents. Skew is selectable as a multiple of a time unit (tU) which ranges puts default to the MID level. Where programmable skew is not a re-
from 782ps to 1.5625ns for Standard version and 6.25ps to 1.3ns for A quirement, the control pins can be left open for the zero skew default
version (see Programmable Skew Range and Resolution Table). There setting. The Control Summary Table shows how to select specific skew
are nine skew configurations available for each output pair. These con- taps by using the nF1:0 control pins.
EXTERNALFEEDBACK
By providing external feedback, the IDT5T995 gives users flexibility
An internal loop filter moderates the response of the VCO to the
with regard to skew adjustment. The FB signal is compared with the phase detector. The loop filter transfer function has been chosen to
input REF signal at the phase detector in order to drive the VCO. Phase provide minimal jitter (or frequency variation) while still providing accu-
differences cause the VCO of the PLL to adjust upwards or downwards rate responses to input frequency changes.
accordingly.
PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE
IDT5T995
FS = MID
IDT5T995A
FS = MID
FS = LOW
1/(32 x FNOM)
24 to 40MHz
FS = HIGH
1/(8 x FNOM)
80 to 160MHz
FS = LOW
FS = HIGH
Comments
TimingUnitCalculation(tU)
VCOFrequencyRange(FNOM)(1,2)
SkewAdjustmentRange(3)
MaxAdjustment:
1/(16 x FNOM)
40 to 80MHz
1/(32 x FNOM) 1/(16 x FNOM) 1/(8 x FNOM)
24 to 50MHz 48 to 100MHz 96 to 200MHz
±7.8125ns
±9.375ns
±9.375ns
±7.8125ns
±67.5°
±18.75%
tU = 1.25ns
tU =0.833ns
tU =0.625ns
—
±7.8125ns
±135°
±7.8125ns
±270°
±75%
—
ns
±67.5°
±135°
±270°
PhaseDegrees
% of Cycle Time
±18.75%
±37.5%
±75%
±37.5%
—
Example 1, FNOM = 25MHz
Example 2, FNOM = 37.5MHz
Example 3, FNOM = 50MHz
Example 4, FNOM = 75MHz
Example 5, FNOM = 100MHz
Example 6, FNOM = 150MHz
Example 7, FNOM = 200MHz
tU = 1.25ns
—
—
tU =0.833ns
—
—
—
—
—
—
—
—
—
tU = 1.25ns
—
—
tU = 1.25ns
tU =0.833ns
tU =0.625ns
—
—
tU =0.833ns
—
—
—
—
tU = 1.25ns
tU =0.833ns
—
—
tU = 1.25ns
tU =0.833ns
tU =0.625ns
—
—
—
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be FNOM when the output connected to FB is undivided
and DS[1:0] = MM. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the
FB input and setting DS[1:0] = MM. Using the DS[1:0] inputs allows a different method for frequency multiplication (see Divide Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ±6tU skew adjustment is possible and at the lowest FNOM value.
3
IDT5T995/A
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
INDUSTRIALTEMPERATURERANGE
DIVIDESELECTIONTABLE
(1)
DS [1:0]
LL
FB Divide-by-n
Permitted Output Divide-by-n connected to FBIN
2
3
1 or 2
1
LM
LH
4
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
ML
5
MM
M H
HL
1
6
8
H M
H H
10
12
1
NOTE:
1. Permissible output division ratios connected to FB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided
output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS
nF1:0
LL(1)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Skew (Pair #4)
Divide by 2
–6tU
–4tU
–3tU
Divide by 2
–6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
M H
HL
Zero Skew
1tU
Zero Skew
2tU
Zero Skew
2tU
2tU
4tU
4tU
H M
H H
3tU
6tU
6tU
Inverted(2)
4tU
Divide by 4
NOTES:
1. LL disables outputs if TEST = MID and sOE = HIGH.
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.
RECOMMENDEDOPERATINGRANGE
Symbol
VDD/VDDQ
TA
Description
Min.
2.3
Typ.
2.5
Max.
Unit
V
Power Supply Voltage
AmbientOperatingTemperature
2.7
-40
+25
+85
°C
4
IDT5T995/A
INDUSTRIALTEMPERATURERANGE
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
Min.
Max.
Unit
V
VIH
Input HIGH Voltage
2
—
—
0.7
VIL
InputLOWVoltage
V
VIHH
VIMM
VILL
IIN
Input HIGH Voltage(1)
InputMIDVoltage(1)
InputLOWVoltage(1)
InputLeakageCurrent
(REF, FB Inputs Only)
VDD−0.4
VDD/2−0.2
—
—
V
3-Level Inputs Only
VDD/2+0.2
0.4
V
3-Level Inputs Only
V
VIN = VDD or GND
−5
+5
μA
VDD = Max.
VIN = VDD
HIGH Level
MID Level
LOW Level
—
−50
−200
−25
—
+200
+50
—
I3
3-LevelInputDCCurrent
(TEST, FS, nF[1:0], DS[1:0])
Input Pull-Up Current (PE, PD)
InputPull-DownCurrent(sOE)
Output HIGH Voltage
VIN = VDD/2
μA
VIN = GND
IPU
IPD
VDD = Max., VIN = GND
VDD = Max., VIN = VDD
—
μA
μA
V
+100
—
VOH
VDD = Min., IOH = −2mA (LOCK Output)
VDDQ = Min., IOH = −12mA (nQ[1:0] Outputs)
VDD = Min., IOL = 2mA (LOCK Output)
VDDQ = Min., IOL = 12mA (nQ[1:0] Outputs)
2
2
—
VOL
OutputLOWVoltage
—
0.4
0.4
V
—
NOTE:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWERSUPPLYCHARACTERISTICS
5T995
Typ.(2)
5T995A
Max. Typ.(2)
Symbol
Parameter
TestConditions(1)
VDD = Max., TEST = MID, REF = LOW,
PE = LOW, sOE = LOW, PD = HIGH
FS = MID, All outputs unloaded
VDD = Max., PD = LOW, SOE = LOW
PE = HIGH, TEST = HIGH, FS = HIGH
nF[1:0] = HH, DS[1:0] = HH
Max.
Unit
IDDQ
Quiescent Power Supply Current
20
—
1
30
25
30
20
30
mA
IDDPD
ΔIDD
IDDD
Power Down Current
—
1
25
30
μA
μA
Power Supply Current per Input HIGH
(REF and FB inputs only)
VIN = 2.3V, VDD = Max., PD = LOW
TEST = HIGH
FS = L
190
150
130
49
290
230
200
—
190
150
130
—
290
230
200
—
Dynamic Power Supply Current per Output FS = M
μA/MHz
FS = H
FS = L
FVCO = 40MHz, CL = 0pF
FVCO = 50MHz, CL = 0pF
FVCO = 80MHz, CL = 0pF
FVCO = 100MHz, CL = 0pF
FVCO = 160MHz, CL = 0pF
FVCO = 200MHz, CL = 0pF
—
—
56
—
ITOT
TotalPowerSupplyCurrent
FS = M
FS = H
66
—
—
—
mA
—
—
80
—
103
—
—
—
—
—
125
—
NOTES:
1. Measurements are for divide-by-1 outputs, nF[1:0] = MM, and DS[1:0] = MM.
2. For nominal voltage and temperature.
5
IDT5T995/A
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
INDUSTRIALTEMPERATURERANGE
INPUTTIMINGREQUIREMENTS
5T995
5T995A
Symbol
tR, tF
tPWC
Description(1)
Maximum input rise and fall times, 0.7V to 1.7V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
—
Max.
10
Min.
—
2
Max.
10
Unit
ns/V
ns
2
—
—
DH
10
90
10
2
90
%
FS = LOW
2
40
50
FREF
Referenceclockinputfrequency
FS = MID
3.33
6.67
80
4
100
200
MHz
FS = HIGH
160
8
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
6
IDT5T995/A
INDUSTRIALTEMPERATURERANGE
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
5T995
5T995A
Typ.
Symbol
FNOM
tRPWH
tRPWL
tU
Parameter
Min.
Typ.
Max.
Min.
Max.
Unit
VCO Frequency Range
REF Pulse Width HIGH(1)
REF Pulse Width LOW(1)
SeeProgrammableSkewRangeandResolutionTable
2
2
—
—
—
—
2
2
—
—
—
—
ns
ns
ProgrammableSkewTimeUnit
SeeControlSummaryTable
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3)
ZeroOutputSkew(AllOutputs)(4)
—
—
50
0.1
0.1
0.2
0.15
0.3
—
185
0.25
0.25
0.5
0.5
0.9
0.75
0.3
0.5
0.7
0.7
1
—
—
50
0.1
0.1
0.2
0.15
0.3
—
185
0.25
0.25
0.5
0.5
0.9
0.75
0.25
0.25
0.5
0.7
1
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5)
OutputSkew(Rise-Fall,Nominal-Inverted,Divided-Divided)(5)
OutputSkew(Rise-Rise,Fall-Fall,DifferentClassOutputs)(5)
OutputSkew(Rise-Fall,Nominal-Divided,Divided-Inverted)(2)
Device-to-Device Skew(2,6)
Static Phase Offset (FS = L, M, H) (FB Divide-by-n = 1, 2, 3)(7)
Static Phase Offset (FS = H)(7)
Static Phase Offset (FS = M)(7)
Static Phase Offset (FS = L) (FB Divide-by-n = 1, 2, 3, 4, 5, 6)(7)
Static Phase Offset (FS = L) (FB Divide-by-n = 8, 10, 12)(7)
Output Duty Cycle Variation from 50%
Output HIGH Time Deviation from 50%(8)
OutputLOWTimeDeviationfrom50%(9)
OutputRiseTime
—
—
—
—
—
—
—
—
—
—
t(φ)1-3
−0.3
−0.5
−0.7
−0.7
−1
−1
—
—
−0.25
−0.25
−0.5
−0.7
−1
−1
—
—
t(φ)H
—
—
t(φ)M
—
—
t(φ)L1-6
t(φ)L8-12
tODCV
tPWH
—
—
—
—
—
1
—
1
—
1.5
2
—
1.5
2
tPWL
—
—
—
—
tORISE
tOFALL
tLOCK
tCCJH
0.15
0.15
—
0.7
0.7
—
1.5
1.5
0.5
100
0.15
0.15
—
0.7
0.7
—
1.5
1.5
0.5
100
OutputFallTime
PLLLockTime(10,11)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=any)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = M)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = L, FREF > 3MHz)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = L, FREF < 3MHz)
—
—
—
—
tCCJHA
tCCJM
tCCJL
—
—
—
—
—
—
—
—
150
200
200
300
—
—
—
—
—
—
—
—
150
150
200
300
ps
tCCJLA
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSK(0) is the skew between outputs when they are selected for 0tU.
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode). Test condition: nF0:1=MM is set on unused outputs.
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
7. tφ is measured with REF input rise and fall times (from 0.7V to 1.7V) of 0.5ns. Measured from 1.25V on REF to 1.25V on FB.
8. Measured at 1.7V.
9. Measured at 0.7V.
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
11. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.
7
IDT5T995/A
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
INDUSTRIALTEMPERATURERANGE
AC TEST LOADS AND WAVEFORMS
VDDQ
150Ω
Output
Output
150Ω
20pF
20pF
For LOCK output
For all other outputs
tOFALL
tORISE
1.7V
tPWH
VTH = 1.25V
0.7V
tPWL
2.5V Output Waveform
≤1ns
≤1ns
2.5V
1.7V
VTH = 1.25V
0.7V
0V
LVTTL Input Test Waveform
8
IDT5T995/A
INDUSTRIALTEMPERATURERANGE
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
AC TIMING DIAGRAM
tRPWL
tREF
tRPWH
REF
t(φ)
tODCV
tODCV
FB
Q
tCCJ H, HA,
M, L, LA
tSKEWPR
tSKEW0, 1
tSKEWPR
tSKEW0, 1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3, 4
tSKEW3, 4
tSKEW3, 4
tSKEW2, 4
REF DIVIDED BY 2
REF DIVIDED BY 4
tSKEW1, 3, 4
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75Ω to VDDQ/2.
tSKEWPR:
tSKEW0:
tDEV:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
The skew between outputs when they are selected for 0tU
.
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tODCV:
tPWH is measured at 1.7V.
tPWL is measured at 0.7V.
tORISE and tOFALL are measured between 0.7V and 1.7V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9
IDT5T995/A
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XXXXX
XX
IDT
Package
Package
Device Type
I
-40°C to +85°C (Industrial)
Thin Quad Flat Pack
TQFP - Green
PF
PFG
5T995
5T995A
2.5V Programmable Skew PLL Clock
Driver TurboClock II
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10
相关型号：
5THZ52
SILICON DIFFUSED TYPE (HORIZONTAL DEFLECTION OUTPUT FOR HIGH RESOLUTION DISPLAY, COLOR TV)
TOSHIBA
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