5V49EE502NLGI [IDT]
EEPROM PROGRAMMABLE CLOCK GENERATOR;
| 型号： | 5V49EE502NLGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | EEPROM PROGRAMMABLE CLOCK GENERATOR 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 驱动 逻辑集成电路 |
| 文件： | 总34页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE502
Description
Features
The 5V49EE502 is a programmable clock generator
intended for high performance data-communications,
telecommunications, consumer, and networking
applications. There are four internal PLLs, each individually
programmable, allowing for four unique non-integer-related
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from one of
the two redundant clock inputs. Automatic or manual
switchover function allows any one of the redundant clocks
to be selected during normal operation.
• Four internal PLLs
• Internal non-volatile EEPROM
2
• Fast (400kHz) mode I C serial interface
• Input frequency range: 1MHz to 200MHz
• Output frequency range: 4.9kHz to 500MHz
• Reference crystal input with programmable linear load
capacitance
— Crystal frequency range: 8MHz to 50MHz
The 5V49EE502 is in-system, programmable and can be
2
• Two independently controlled VDDO (1.8V to 3.3V)
programmed through the use of I C interface. An internal
• Each PLL has a 7-bit reference divider and a 12-bit
feedback-divider
EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
• 8-bit output-divider blocks
• Fractional division capability on one PLL
Each of the four PLLs has an 7-bit reference divider and a
12-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation
and/or fractional divides are allowed on two of the PLLs.
• Two of the PLLs support spread spectrum generation
capability
• I/O standards:
— Outputs: 1.8V to 3.3 V LVTTL/ LVCMOS
— Outputs: LVPECL, LVDS and HCSL
— Inputs: 3.3 V LVTTL/ LVCMOS
• Programmable slew rate control
• Programmable loop bandwidth
There are a total of four 8-bit output dividers. Each output
bank can be configured to support LVTTL, LVPECL, LVDS
or HCSL logic levels. Out0 (Output 0) supports 3.3V
single-ended standard only. The outputs are connected to
the PLLs via a switch matrix. The switch matrix allows the
user to route the PLL outputs to any output bank. This
feature can be used to simplify and optimize the board
layout. In addition, each output's slew rate and
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with auto and manual switchover
options
• Individual output enable/disable
• Power-down mode
enable/disable function is programmable.
• 3.3V core V
DD
• Available in 24-QFN package
• -40° to +85°C industrial temperature operation
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Block Diagram
S
R
C
0
OUT0
XIN/REF
XOUT
S
R
C
1
S1
PLL0 (SS)
/DIV1
/DIV2
OUT1
OUT2
S
R
C
2
CLKIN
PLL1
PLL2
CLKSEL
S
R
C
3
S3
/DIV3
/DIV6
PLL3 (SS)
OUT3
OUT6
S
R
C
6
SD/OE
SDA
SCL
Control
Logic
SEL[2:0]
1. OUT1 & OUT2 and OUT3 & OUT6 pairs can be configured to be LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs.
2. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors.
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Pin Configuration
19
1
VDDO3
OUT3
VDD
XOUT
OUT6
XIN/REF
VDDx
GND
CLKIN
AVDD
CLKSEL
13
GND
7
24-pin QFN
Pin Descriptions
Pin#
Pin Name
VDD
I/O
Pin Type
Power
Pin Description
Device power supply. Connect to 3.3V.
1
2
3
XOUT
O
I
LVTTL
CRYSTAL_OUT – Reference crystal feedback.
XIN / REF
LVTTL
CRYSTAL_IN – Reference crystal input or external reference clock
input.
4
Power
Crystal oscillator power supply. Connect to 3.3V through 5
resistor. Use filtered analog power supply if available.
VDDx
5
6
7
8
9
CLKIN
GND
I
LVTTL
Power
Input clock. Weak internal pull down resistor.
Connect to Ground.
OUT1
O
O
Adjustable1
Adjustable1
Power
Configurable clock output 1.
Configurable clock output 2.
OUT2
Device power supply. Connect to 1.8 to 3.3V. Sets output voltage
levels for OUT1and OUT2.
VDDO1
10
11
VDD
Power
Device power supply. Connect to 3.3V.
SDAT
I/O
Open Drain
Bidirectional I2C data. An external pull-up resistor is required. See
I2C specification for pull-up value recommendation.
12
SCLK
I
I
LVTTL
I2C clock. An external pull-up resistor is required. See I2C
specification for pull-up value recommendation.
13
14
CLKSEL
AVDD
LVTTL
Power
Input clock selector. Weak internal pull down resistor.
Device analog power supply. Connect to 3.3V. Use filtered analog
power supply if available.
15
16
GND
Power
Connect to Ground.
OUT6
O
Adjustable1
Configurable clock output 6.
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Pin#
17
Pin Name
OUT3
I/O
Pin Type
Adjustable1
Power
Pin Description
O
Configurable clock output 3.
18
Device power supply. Connect to 1.8 to 3.3V. Sets output voltage
levels for OUT3 and OUT6.
VDDO3
19
20
21
22
SEL2
SEL1
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Configuration select pin. Weak internal pull down resistor.
Configuration select pin. Weak internal pull down resistor.
Configuration select pin. Weak internal pull down resistor.
SEL0
SD/OE
Enables/disables the outputs or powers down the chip. The SP bit
(0x02) controls the polarity of the signal to be either active HIGH or
LOW. (Default is active LOW.) Weak internal pull down resistor.
23
24
OUT0
GND
O
Adjustable1
Power
Configurable clock output 0.
Connect to Ground.
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
3. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
4. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
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PLL Features and Descriptions
7-bit
D
VCO
4-bit
A
12-bit
N
Sigma-Delta
Modulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
Multiplier
Programmable
Spread Spectrum
(D)1 Values (M)2 Values Loop Bandwidth Generation Capability
PLL0
PLL1
PLL2
PLL3
1 - 127
1 - 127
1 - 127
3 - 127
10 - 8206
1 - 4095
1 - 4095
12 - 4095
Yes
Yes
Yes
Yes
Yes
No
No
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
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XTAL load cap = 3.5pF + XTAL[4:0] * 0.125pF (Eq. 1)
Reference Clock Input Pins and
Selection
Parameter
Bits
Step (pF)
Min (pF)
Max (pF)
The 5V49EE502 supports up to two clock inputs. One of the
clock inputs (XIN/ REF) can be driven by either an external
crystal or a reference clock. The second clock input (CLKIN)
can only be driven from an external reference clock. The
CLKSEL pin selects the input clock from either XTAL/REF or
CLKIN.
XTAL
8
0.125
0
4
When using an external reference clock instead of a crystal
on the XTAL/REF pin, the input load capacitors may be
completely bypassed. This allows for the input frequency to
be up to 200MHz. When using an external reference clock,
the XOUT pin must be left floating, XTAL must be
programmed to the default value of “00h”, and the crystal
drive strength bit, XDRV (0x06), must be set to the default
value of “11h”.
Either clock input can be set as the primary clock. The
primary clock designation is to establish which is the main
reference clock to the PLLs. The non-primary clock is
designated as the secondary clock in case the primary clock
goes absent and a backup is needed. The PRIMSRC bit
(0xBE through 0xC3) determines which clock input will be
selected as primary clock. When PRIMSRC bit is “0”,
XIN/REF is selected as the primary clock, and when “1”,
CLKIN as the primary clock.
Switchover Modes
The 5V49EE502 features redundant clock inputs which
supports both Automatic and Manual switchover mode.
These two modes are determined by the configuration bits,
SM (0xBE through 0xC3). The primary clock source can be
programmed, via the PRIMSRC bit, to be either XIN/REF or
CLKIN. The other clock input will be considered as the
secondary source. Note that the switchover modes are
asynchronous. If the reference clocks are directly routed to
OUTx with no phase relationship, short pulses can be
generated during switchover. The automatic switchover
mode will work only when the primary clock source is
XIN/REF. Switchover modes are not supported for crystal
input configurations.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits (0xBE through 0xC3)
must be set to "0x" for manual switchover which is detailed
in SWITCHOVER MODES section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
When the XIN/REF pin is driven by a crystal, it is important
to set the internal inverter oscillator drive strength and
tuning/load capacitor values correctly to achieve the best
clock performance. These values are programmable
Manual Switchover Mode
When SM[1:0] is "0x", the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to
switch between the primary and secondary clock sources.
As previously mentioned, the primary and secondary clock
source setting is determined by the PRIMSRC bit. During
the switchover, no glitches will occur at the output of the
device, although there may be frequency and phase drift,
depending on the exact phase and frequency relationship
between the primary and secondary clocks.
2
through I C interface to allow for maximum compatibility
with crystals from various manufacturers, processes,
performances, and qualities. The internal load capacitors
are true parallel-plate capacitors for ultra-linear
performance. Parallel-plate capacitors were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and
temperature changes. External non-linear crystal load
capacitors should not be used for applications that are
sensitive to absolute frequency requirements. The value of
the internal load capacitors are determined by XTAL[4:0]
bits. The load capacitance can be set with a resolution of
0.125pF for a total crystal load ranging from 3.5pF to 7.5pF.
Check with the crystal vendor's load capacitance
specification for the exact setting to tune the internal load
capacitor. The following equation governs how the total
internal load capacitance is set.
Automatic Switchover Mode
The redundant inputs are in automatic switchover mode.
Automatic switchover mode has revertive functionality. The
input clock selection will switch to the secondary clock
source when there are no transitions on the primary clock
source for two secondary clock cycles. If both reference
clocks are at different frequencies, the device will always
remain on the primary clock unless it is absent for two
secondary clock cycles. The secondary clock must always
run at a frequency less than or equal to the primary clock
frequency.
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Reference Divider, Feedback Divider, and
Output Divider
Q[6:0]
PM
0
Output Divider
Each PLL incorporates a 7-bit reference divider (D[6:0]) and
a 12-bit feedback divider (N[11:0]) that allows the user to
generate four unique non-integer-related frequencies. Each
output divide supports 8-bit output-divider (PM and Q[7:0]).
The following equation governs how the output frequency is
calculated.
111 1111
Disabled
1
/1
<111 1111
0
/2
1
/((Q[6:0] + 2) * 2)
M
Note that the actual 7-bit Q-divider value has a 2 added to
the integer value Q and the outputs are routed through
another div/2 block. The output divider should never be
disabled unless the output bank will never be used during
normal operation. The output frequency range for LVTTL
outputs are from 4.9kHz to 200MHz. The output frequency
for LVPECL/LVDS/HCSL outputs range from 4.9kHz to
500MHz.
F *
=
FOUT
( D )
IN
(Eq. 1)
ODIV
Where FIN is the reference frequency, M is the total
feedback-divider value, D is the reference divider value,
ODIV is the total output-divider value, and FOUT is the
resulting output frequency.
For PLL0,
Spread Spectrum Generation (PLL0)
PLL0 supports spread spectrum generation capability,
which users have the option of turning on or off. Spread
spectrum profile, frequency, and spread amplitude are fully
programmable. The programmable spread spectrum
generation parameters are TSSC[3:0], NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], DITH, and X2 bits. These bits
are in the memory address from 0xAC to 0xBD for PLL0.
The spread spectrum generation on PLL0 can be
enabled/disabled using the TSSC[3:0] bits. To enable
spread spectrum, set TSSC > '0' and set NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M
value) accordingly. To disable spread spectrum generation,
set TSSC = '0'.
M = 2 * N + A + 1 (for A>0)
M = 2 * N (for A = 0)
For PLL1, PLL2 and PLL3,
M = N
PM and Q[6:0] are the bits used to program the 8-bit
output-dividers for outputs OUT1-6. OUT0 does not have
any output divide along its path. The 8-bit output-dividers
will bypass or divide down the output banks' frequency with
even integer values ranging from 2 to 256.
TSSC[3:0]
There is the option to choose between disabling the
output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider
by using the PM bit. If the output is disabled, it will be driven
High, Low or High Impedance, depending on OEM[1:0].
Each bank, except for OUT0, has a PM bit. When disabled,
no clocks will appear at the output of the divider, but will
remain powered on. The output divides selection table is
shown below.
These bits are used to determine the number of
phase/frequency detector cycles per spread spectrum cycle
(ssc) steps. The modulation frequency can be calculated
with the TSSC bits in conjunction with the NSSC bits. Valid
TSSC integer values for the modulation frequency range
from 5 to 14. Values of 0 – 4 and 15 should not be used.
NSSC[2:0]
These bits are used to determine the number of
delta-encoded samples used for a single quadrant of the
spread spectrum waveform. All four quadrants of the spread
spectrum waveform are mirror images of each other. The
modulation frequency is also calculated based on the NSSC
bits in conjunction with the TSSC bits. Valid NSSC integer
values range from 1 to 6. Values of 0 and 7 should not be
used.
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SS_OFFSET[5:0]
Modulation frequency:
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of 0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
FPFD = FIN / D (Eq. 6)
FVCO = FPFD * MNOM (Eq. 7)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)
Spread:
= SD0 + SD1 + SD2 + …+ SD11
the number of samples used depends on the NSSC value
63 - SS_OFFSET
SD[3:0]
Spread% = (* 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 2)
NSSC = NSSC[2:0] * 2 (Eq. 3)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)
where SJ is the unencoded sample out of a possible 12 and
SDK is the delta-encoded sample out of a possible 12.
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
if 1 < Amplitude < 2, then set X2 bit to '1'.
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Tssc = 14 + 2 = 16
Nssc = 6 × 2 = 12
Nssc × Tssc = 192
Profile:
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ,
SS_OFFSET + SDJ+1, etc.
Spread Spectrum Using Sinusoidal Profile
Use Eq.10 to determine the value of the
sigma-delta-encoded samples.
2% = * 100)/(64 × 48)
= 61.4
Either round up or down to the nearest integer value.
Therefore, we end up with 61 or 62 for sigma-delta-encoded
samples. Since the sigma-delta-encoded samples must not
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within
the limits. It is the discretion of the user to define the shape
of the profile that is better suited for the intended application.
Using Eq. 9 again, the actual spread for the
sigma-delta-encoded samples of 56 and 57 are 1.99% and
2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 × (1.99 or 2.02) / 100/2 = 0.48 < 1
Therefore, the X2 = '0 '. The dither bit is left to the discretion
of the user.
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33kHz with center
spread of 2%. Find the necessary spread spectrum
register settings.
The example above was of a center spread using spread
spectrum. For down spread, the nominal M value can be set
one integer value lower to 47.
Since the spread is center, the SS_OFFSET can be set to
'0'. Solve for the nominal M value; keep in mind that the
nominal M should be chosen to maximize
Note that the 5V49EE502 should not be programmed with
TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to
prevent an unstable state in the modulator.
the VCO. Start with D = 1, using Eq.6 and Eq.7.
MNOM = 1200MHz / 25MHz = 48
The PLL loop bandwidth must be at least 10x the
modulation frequency along with higher damping (larger
uz) to prevent the spread spectrum from being filtered and
reduce extraneous noise. Refer to the LOOP FILTER
section for more detail on uz. The A[3:0] must be used for
spread spectrum, even if the total multiplier value is an even
integer.
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we
have the nominal M value, we can determine TSSC and
NSSC by using Eq.8.
Nssc × Tssc = 25MHz / (33kHz × 4) = 190
However, using Eq. 2 and Eq.3, we find that the closest
value is when TSSC = 14 and NSSC = 6. Keep in mind to
maximize the number of samples used to enhance the
profile of the spread spectrum waveform.
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Zero capacitor (Cz) = 196pF + CZ × 217pF
Pole capacitor (Cp) = 15pF
Spread Spectrum Generation (PLL3)
PLL3 support spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The technique is different from
that used in PLL0. The programmable spread spectrum
generation parameters are SS_D3[7:0], SSVCO[15:0],
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the
memory address range of 0x4C to 0x85 for PLL3. The
spread spectrum generation on PLL3 can be
Charge pump (Ip) = 6 × (IP[0] + 2 × IP[1]+4 × IP[2]) uA
VCO gain (KVCO) = 900 MHz/V × 2
The following equations govern how the loop filter is set for
PLL3:
enabled/disabled using the SSENB bit. To enable spread
spectrum, set SSENB = '1'.
For Non-Spread Spectrum Operation:
(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
Resistor(Rz)=
kOhms (Eq. 12)
kOhms (Eq. 13)
* RZ[0] +6*(1–RZ[0])
For Spread Enabled:
Spread spectrum is configured using SS_D3(spread
spectrum reference divide)
For Spread Spectrum Operation:
(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
F
IN
(Eq. 10)
=
SS_D3
Resistor(Rz)=
4 * F
* RZ[0] +6*(1–RZ[0])
MOD
and SSVCO (spread spectrum loop feedback counter).
Zero capacitor (Cz) = 250pF
Pole capacitor (Cp) = 15pF
F
VCO
( 1 + SS/400) + 5]
(Eq. 11)
SSVCO [0.5 *
*
=
F
MOD
For Non-Spread Spectrum Operation:
SS is the total Spread Spectrum amount (I.e. center spread
+0.5% has a total spread of 1.0% and down spread -0.5%
has a total spread of 0.5%.)
24* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))
Charge
ꢀA (Eq. 14)
ꢀA (Eq. 14)
=
pump (Ip)
3+(5* IP[3]) +(11* IP[4])
Loop Filter
For Spread Spectrum Operation:
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low-jitter
frequency generation. The specific loop filter components
that can be programmed are the resistor via the RZ[3:0] bits,
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and
the charge pump current via the IP[2:0] bits (for PLL0, PLL1
and PLL2) or IP[3:0] (for PLL3).
12* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))
Charge
pump (Ip)
=
27+(5* IP[3]) +(11* IP[4])
VCO gain (KVCO) = 900 MHz/V × 2
The following equations govern how the loop filter is set for
PLL0 - PLL2:
Resistor (Rz) = (RZ[0] + 2 × RZ[1]+4 × RZ[2] + 8 × RZ[3]) ×
4.0kOhm
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PLL Loop Bandwidth:
Charge pump gain (K) = Ip / 2
VCO gain (KVCO) = 900 MHz/V × 2
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
c = (Rz × K× KVCO × Cz)/(M × (Cz + Cp))
Fc = c / 2
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (m)
needs to be calculated as follows.
Phase Margin:
z = 1 / (Rz × Cz)
p = (Cz + Cp)/(Rz × Cz × Cp)
m = (360 / 2) * [tan-1(c/ z) - tan-1(c/ p)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
11
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
SEL[2:0] Function
The 5V49EE502 can support up to six unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[2:0]
pins. Alternatively, users may use I C interface to configure
these registers on-the-fly.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to
be either active HIGH or LOW with the SP bit (0x02). When
SP is “0” (default), the pin becomes active LOW and when
SP is “1”, the pin becomes active HIGH. The SD/OE pin can
be configured as either to shutdown the PLLs or to
enable/disable the outputs.
2
SEL2 SEL1 SEL0
Configuration Selections
Select CONFIG0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OUTn
Select CONFIG1
Select CONFIG2
Select CONFIG3
Select CONFIG4
Select CONFIG5
Reserved (Do not use)
Reserved (Do not use)
SP
SD/OE Input
OE
OS
Global Shutdown
SH
Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
OUTn
High-Z2
Enabled
Enabled
Suspended
Crystal/Clock Selection
0
0
0
0
0
0
0
0
0
1
1
1
x
0
1
1
x
x
0
1
XTCLKSEL bit is used to bypass a crystal oscillator circuit
when external clock source is used.
PRIMSRC bit is used to select a primary clock from
XIN/REF and CLKIN.
0
0
0
0
1
1
1
1
0
1
1
1
x
0
1
1
x
x
0
1
High-Z2
Enabled
Suspended
Enabled
High-Z2
Enabled
Enabled
High-Z2
Enabled
Suspended
Suspended 1
PRIMSRC bit Primary Secondary
0
1
XIN/REF CLKIN
1
1
1
0
0
0
0
1
1
x
0
1
0
0
0
CLKIN
XIN/REF
CLKSEL input
Clock Source
1
1
1
1
1
1
0
1
1
x
0
1
0
0
0
0
1
Primary Clock Source
Secondary Clock Source
1
x
x
x
1
CLKSEL
PRIMSRC Reference Clock
0
0
1
1
0
1
0
1
XIN/REF
CLKIN
CLKIN
Note 1 : Global Shutdown
Note 2 : Hi-Z regardless of OEM bits
XIN/REF
Configuration OUTx IO Standard
Primary to Secondary to
Secondary Primary
SMx[1:0] Switching Mode
Users can configure the individual output IO standard from
a specified 1.8V to 3.3V power supplies. Each output can
support 1.8V to 3.3V LVTTL. Each output pair can support
LVDS, LVPECL or HCSL from the specified 3.3V power
supply. OUT0 can only be 3.3V single-ended output.
0x
10
11
Manual
Auto
Auto-Revertive
No
Yes
Yes
No
No
Yes
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
The frame formats are shown in the following illustration.
Programming the Device
2
I C may be used to program the 5V49EE502.
– Device (slave) address = 7'b1101010
I2C Programming
2
The 5V49EE502 is programmed through an I C-Bus serial
2
interface, and is an I C slave device. The read and write
transfer formats are supported. The first byte of data after a
write frame to the correct slave address is interpreted as the
register address; this address auto-increments after each
byte written or read.
Framing
Each frame starts with a “Start Condition” and ends with an “End Condition”. These are both generated by the Master
device.
MSB
LSB
1
1
0
1
0
1
0
R/W
7-bit slave address
R/W
0 – Slave will be written by master
1 – Slave will be read by master
ACK from Slave
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a “1” bit.
2
First Byte Transmitted on I C Bus
External I2C Interface Condition
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
Progwrite
S
Address R/W
7-bits
ACK Command Code ACK
1-bit 8-bits: xxxx xx00 1-bit
Register
ACK
Data ACK
P
0
8-bits
1-bit
8-bits 1-bit
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
S
Address R/W
7-bits
ACK Command Code ACK
1-bit 8-bits: xxxx xx00 1-bit
Register
ACK
P
0
8-bits
1-bit
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
S
Address R/W ACK ID Byte ACK Data_1 ACK Data_2 ACK Data_last NACK
7-bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit
P
1
Progread Command Frame
Progsave
S
Address R/W
7-bits
ACK Command Code ACK
1-bit 8-bits: xxxx xx01 1-bit
P
0
Note:
PROGWRITE is for writing to the 5V49EE502 registers.
PROGREAD is for reading the 5V49EE502 registers.
PROGSAVE is for saving all the contents of the 5V49EE502 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V49EE502 registers.
Progrestore
S
Address R/W
7-bits
ACK Command Code ACK
1-bit 8-bits: xxxx xx10 1-bit
P
0
EEPROM Interface
The 5V49EE502 can also store its configuration in an internal EEPROM. The contents of the device's internal programming
registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal
programming registers by issuing a restore instruction (ProgRestore).
2
To initiate a save or restore using I C, only two bytes are transferred. The Device Address is issued with the read/write bit
set to “0”, followed by the appropriate command code. The save or restore instruction executes after the STOP condition is
issued by the Master, during which time the 5V49EE502 will not generate Acknowledge bits. The 5V49EE502 will
2
acknowledge the instructions after it has completed execution of them. During that time, the I C bus should be interpreted
as busy by all other users of the bus.
On power-up of the 5V49EE502, an automatic restore is performed to load the EEPROM contents into the internal
programming registers. The 5V49EE502 will be ready to accept a programming instruction once it acknowledges its 7-bit I C
address.
2
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
I2C Bus DC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
V
Input HIGH Level
0.7xV
IH
DD
V
Input LOW Level
0.3xV
V
IL
DD
V
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
0.05xV
V
HYS
DD
I
1.0
0.4
µA
V
IN
V
I
= 3 mA
OL
OL
I2C Bus AC Characteristics for Standard Mode
Symbol
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Min
0
Typ
Max
Unit
F
100
kHz
µs
µs
µs
ns
µs
µs
pF
ns
ns
µs
µs
µs
SCLK
t
4.7
4.7
4
BUF
t
SU:START
HD:START
t
Hold Time, START
t
Setup Time, data input (SDA)
250
0
SU:DATA
1
t
Hold Time, data input (SDA)
HD:DATA
t
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDAT, SCLK)
Fall Time, data and clock (SDAT, SCLK)
HIGH Time, clock (SCLK)
3.45
400
OVD
C
B
t
1000
300
R
t
F
t
4
4.7
4
HIGH
t
LOW Time, clock (SCLK)
LOW
t
Setup Time, STOP
SU:STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDAT signal (referred to the V (MIN)
IH
of the SCLK signal) to bridge the undefined region of the falling edge of SCLK.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
I2C Bus AC Characteristics for Fast Mode
Symbol
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Min
0
Typ
Max
Unit
kHz
µs
F
400
SCLK
t
1.3
0.6
0.6
100
0
BUF
t
µs
SU:START
HD:START
t
Hold Time, START
µs
t
Setup Time, data input (SDA)
ns
SU:DATA
1
t
Hold Time, data input (SDA)
µs
HD:DATA
t
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCL)
Fall Time, data and clock (SDA, SCL)
HIGH Time, clock (SCL)
0.9
400
300
300
µs
OVD
C
pF
ns
B
t
20 + 0.1xC
20 + 0.1xC
0.6
R
B
t
ns
F
B
t
µs
HIGH
t
LOW Time, clock (SCL)
1.3
µs
LOW
t
Setup Time, STOP
0.6
µs
SU:STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V (MIN)
IH
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5V49EE502. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Symbol
Description
Min
-0.5
-0.5
-0.5
Max
+4.6
+4.6
Unit
V
V
Internal Power Supply Voltage
DD
1
V
Input Voltage
V
I
1
V
Output Voltage (not to exceed 4.6V)
Junction Temperature
V
+0.5
DD
V
O
T
150
°C
°C
J
T
Storage Temperature
-65
150
STG
1.Input negative and output voltage ratings may be exceeded if the input and output current ratings are observed.
Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
V
Power supply voltage for V pins supporting core and
DD
outputs
3.135
3.3
3.465
V
V
V
DD
V
Power supply voltage for crystal oscillator. Use filtered
analog power supply if available.
3.135
3.135
3.3
3.3
3.465
3.465
DDX
AV
Analog power supply voltage. Use filtered analog
power supply if available.
DD
V
3.3V VDDO Range
3.0
2.25
1.7
3.3
2.5
1.8
3.3
3.6
2.75
1.9
V
V
V
V
DDOX
2.5V VDDO Range for 2.5V LVTTL
1.8V VDDO Range for 1.8V LVTTL
Power supply voltage for V pins supporting
DD
LVDS/LVPECL/HCSL outputs
3.135
3.465
T
Operating temperature, ambient
-40
+85
15
8
°C
pF
A
C
Maximum load capacitance (3.3V LVTTL only)
Maximum load capacitance (1.8V/2.5V LVTTL only)
External reference crystal
LOAD_OUT
pF
F
8
1
50
200
5
MHz
IN
External reference clock CLKIN
t
Power up time for all V s to reach minimum specified
DD
voltage (power ramps must be monotonic)
0.05
ms
PU
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Capacitance (T = +25 °C)
A
Symbol
Parameter
Min
Typ
Max
Unit
C
Input Capacitance (CLKIN, CLKSEL, SD/OE,
SDA, SCL, SEL[2:0])
3
7
pF
IN
Pull-down
Resistor
CLKIN, CLKSEL, SD/OE, SEL[2:0]
180
k
Crystal Specifications
XTAL_FREQ Crystal frequency
8
50
MHz
pF
pF
V
XTAL_MIN
Minimum crystal load capacitance
3.5
XTAL_MAX Maximum crystal load capacitance
35.5
3.2
XTAL_V
Voltage swing (peak-to-peak, nominal)
1.5
2.3
PP
DC Electrical Characteristics for 3.3-V LVTTL 1
Symbol
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
Typ
Max
Unit
V
V
2.4
V
DD
OH
V
0.4
V
OL
V
2
V
IH
V
0.8
10
V
IL
OZDD
I
Output Leakage Current 3-state outputs. V = V or GND,
DD
µA
O
V
= 3.6V
DD
Note 1: See “Recommended Operating Conditions” table.
Power Supply Characteristics for PLLs and LVTTL Outputs
Total Supply Current Vs PLL Frequency
Supply current Vs Output Frequency
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
0
200
400
600
800
1000
1200
0
25
50
75
100
125
150
175
200
PLL Frequency(MHz)
Output Frequency(MHz)
No outputs
4 outputs on
REF output on
5 outputs on
2 outputs on
3 outputs on
PLL0 ON IDD(mA)
PLL0+PLL1 On IDD(mA)
All Plls ON IDD(mA)
PLL0+PLL1+PLL2 on IDD(mA)
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
DC Electrical Characteristics for LVDS
Symbol
Parameter
Min
247
Typ
Max
454
-454
50
Unit
mV
mV
mV
V
V
(+) Differential Output Voltage for the TRUE binary state
(-) Differential Output Voltage for the FALSE binary state
OT
V
-247
OT
V
Change in V between Complimentary Output States
OT
OT
V
Output Common Mode Voltage (Offset Voltage)
1.125
1.2
1.375
50
OS
V
Change in V between Complimentary Output States
OS
mV
mA
mA
OS
I
Outputs Short Circuit Current, V
+ or V
- = 0V or V
+ = V
9
6
24
OS
OUT
OUT
DD
I
Differential Outputs Short Circuit Current, V
-
12
OSD
OUT
OUT
Power Supply Characteristics for LVDS Outputs 1
Symbol
Parameter
Test Conditions 2
Typ
Max
Unit
I
Quiescent V Power
DD
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68
90
mA
µA/MHz
mA
DDQ
I
Dynamic V Power Supply
DD
Current per Output
V
= Max., C = 0pF
DD L
30
45
DDD
I
Total Power V Supply
DD
Current
F
= 100MHz, C = 2pF
L
86
130
150
190
TOT
REFERENCE CLOCK
REFERENCE CLOCK
REFERENCE CLOCK
F
F
= 200MHz, C = 2pF
L
100
122
= 400MHz, C = 2pF
L
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for LVPECL
Symbol
Parameter
Min
Typ
Max
Unit
V
Output Voltage HIGH, terminated through 50 tied to V - 2V
DD
V
- 1.2
V - 0.9
DD
V
V
V
OH
DD
V
Output Voltage LOW, terminated through 50 tied to V - 2V
DD
V
- 1.95
V
- 1.61
DD
OL
DD
V
Peak-to-Peak Output Voltage Swing
0.55
0.93
SWING
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Power Supply Characteristics for LVPECL Outputs 1
Symbol
Parameter
Test Conditions 2
Typ
Max
Unit
I
Quiescent V Power
DD
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
86
110
mA
DDQ
I
Dynamic V Power Supply
DD
Current per Output
V
= Max., C = 0pF
L
35
50
µA/MHz
mA
DDD
DD
I
Total Power V Supply
DD
Current
F
F
F
= 100MHz, C = 2pF
L
120
130
140
180
190
210
TOT
REFERENCE CLOCK
REFERENCE CLOCK
REFERENCE CLOCK
= 200MHz, C = 2pF
L
= 400MHz, C = 2pF
L
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for HCSL
Symbol
Parameter
Min
660
-150
250
Typ
Max
Unit
mV
V
Output Voltage HIGH
Output Voltage LOW
Absolute
700
0
850
27
OH
V
mV
OL
Crossing Point
Voltage
350
550
mV
Power Supply Characteristics for HCSL Outputs 1
Symbol
Parameter
Test Conditions 2
Typ
Max
Unit
I
Quiescent V Power
DD
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68
90
mA
DDQ
I
Dynamic V Power Supply
DD
Current per Output
V
= Max., C = 0pF
L
30
45
µA/MHz
mA
DDD
DD
I
Total Power V Supply
DD
Current
F
= 100MHz, C = 2pF
L
86
130
150
190
TOT
REFERENCE CLOCK
REFERENCE CLOCK
REFERENCE CLOCK
F
F
= 200MHz, C = 2pF
L
100
122
= 400MHz, C = 2pF
L
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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EEPROM PROGRAMMABLE CLOCK GENERATOR
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
Parameter
Test Conditions
Input frequency limit (CLKIN)
Min. Typ. Max. Units
1
fIN
1
200
100
200
500
MHz
MHz
MHz
Input Frequency
Input frequency limit (XIN/REF)
Single ended clock output limit (LVTTL)
8
1 / t1
Output Frequency
0.001
0.001
Differential clock output limit (LVPECL/
LVDS/HCSL)
fVCO
fPFD
fBW
VCO Frequency
PFD Frequency
Loop Bandwidth
VCO operating frequency range
PFD operating frequency range
100
0.5 1
0.01
1200
100
10
MHz
MHz
MHz
Based on loop filter resistor and capacitor
values
t2
t3
Input Duty Cycle
Duty Cycle for input
40
45
60
55
%
%
Output Duty Cycle
Measured at V /2, all outputs except
DD
Reference output
Measured at V /2, Reference output
DD
40
60
%
t4 2
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 5pF)
3.5
2.75
2
V/ns
DD
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 5pF)
DD
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 5pF)
DD
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 5pF)
1.25
DD
t5
Rise Times
Fall Times
Rise Times
Fall Times
Rise Times
Fall Times
Clock Jitter 6
LVDS, 20% to 80%
600
600
600
600
400
400
80
ps
ps
ps
LVDS, 80% to 20%
LVPECL, 20% to 80%
LVPECL, 80% to 20%
HCSL, From 0.175 V to 0.525 V
HCSL, From 0.525 V to 0.175 V
175
175
700
700
100
t7
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
ps
ps
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs3
200
60
270
80
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
120
160
ps
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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JUNE 18, 2018
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
t8
Output Skew
Skew between output to output on the same
bank
75
ps
t9 4
Lock Time
Lock Time
PLL lock time from power-up
10
20
2
ms
ms
t10 5
PLL lock time from shutdown mode
1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27MHz, 48MHz, 24.576MHz, 74.25MHz and 25MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
6. Not guaranteed until customer specific configuration is approved by IDT.
Spread Spectrum Generation Specifications
Symbol
Parameter
Description
Min Typ Max
Unit
MHz
kHz
1
f
Input Frequency Input Frequency Limit
Mod Frequency Modulation Frequency
1
400
120
-4.0
2.0
IN
f
33
MOD
2
f
Spread Value
Amount of Spread Value (programmable) – Down Spread
Amount of Spread Value (programmable) – Center Spread
-0.5
%f
OUT
SPREAD
0.25
1.Practical lower frequency is determined by loop filter settings.
2. Not guaranteed until customer specific configuration is approved by IDT.
Test Circuits and Conditions
VDDOx
VDD
0.1µF
OUTx
CLKOUT
0.1µF
CL
GND
Test Circuits for DC Outputs
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Other Termination Scheme (Block Diagram)
2 pF
CLKOUT
OUTx
OUTx
CLKOUT
5 pF
CLKOUT
2 pF
GND
GND
LVTTL: 5 pF for each output
LVDS: 100 between differential outputs
VDD-2V
49.9 Ohm
2 pF
33 Ohm
49.9 Ohm
2 pF
CLKOUT
CLKOUT
OUTx
OUTx
33 Ohm
CLKOUT
2 pF
CLKOUT
2 pF
49.9 Ohm
49.9 Ohm
GND
GND
GND
VDD-2V
LVPECL
HCSL
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
23
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Programming Registers Table
Default
Register
Addr
Bit #
Description
Hex
Value
00
7
6
5
4
3
2
1
0
Reserved
HW/SW
0x00
0x01
0x02
Hardware/Software Mode control
HW/SW - 0=HW, 1=SW
Reserved
OE5
SEL[2:0]
OE1
00
02
SEL[2:0] - selects configuration in
SW mode
SP
OE6
OE4
OE3
OE2
OE0
OEx=Output Power Suspend
function for OUTx (‘1’=OUTx will be
suspended on SD/OE pin. Disable
mode is defined by OEMx bits),
‘0’=outputs enabled and no
association with OE pin (default).
Reserved
SH
0x03
0x04
02
0F
OS*[6:0]
OS*[6:0] - output suspend, active
low. Overwrites OE setting.
Reserved
PLLS*[3:0]
PLLS*[3:0] - PLL Suspend, active
low
SH - shutdown/OE configuration
Reserved
Reserved
XTCLKSEL
Reserved
0x05
04
XTCLKSEL - crystal/clock select.
0=crystal, 1=ICLK
Reserved
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
00
00
00
00
10
10
10
10
10
10
00
00
00
00
00
00
01
01
01
01
01
01
00
00
00
00
00
00
10
10
10
10
10
10
XTAL[4:0]
XTAL[4:0] - crystal cap
PLL0 loop parameter
Reserved
Reserved
CZ0_CFG4
CZ0_CFG5
CZ0_CFG0
CZ0_CFG1
CZ0_CFG2
CZ0_CFG3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IP0[2:0]_CFG4
IP0[2:0]_CFG5
IP0[2:0]_CFG0
IP0[2:0]_CFG1
IP0[2:0]_CFG2
IP0[2:0]_CFG3
RZ0[3:0]_CFG4
RZ0[3:0]_CFG5
RZ0[3:0]_CFG0
RZ0[3:0]_CFG1
RZ0[3:0]_CFG2
RZ0[3:0]_CFG3
D0[6:0]_CFG0
PLL0 input divider and input sell
D0[6:0] - 127 step Ref Div
D0 = 0 means power down.
D0[6:0]_CFG1
D0[6:0]_CFG2
D0[6:0]_CFG3
D0[6:0]_CFG4
D0[6:0]_CFG5
N0[7:0]_CFG4
N - Feedback Divider
2 - 4095 (values of “0” and “1” are
not allowed) Total feedback with A,
using provided calculation
N0[7:0]_CFG5
N0[7:0]_CFG0
N0[7:0]_CFG1
N0[7:0]_CFG2
N0[7:0]_CFG3
A0[3:0]_CFG0
N0[11:8]_CFG0
N0[11:8]_CFG1
N0[11:8]_CFG2
N0[11:8]_CFG3
N0[11:8]_CFG4
N0[11:8]_CFG5
RZ1[3:0]_CFG4
RZ1[3:0]_CFG5
RZ1[3:0]_CFG0
RZ1[3:0]_CFG1
RZ1[3:0]_CFG2
RZ1[3:0]_CFG3
A0[3:0]_CFG1
A0[3:0]_CFG2
A0[3:0]_CFG3
A0[3:0]_CFG4
A0[3:0]_CFG5
CZ1_CFG4
CZ1_CFG5
CZ1_CFG0
CZ1_CFG1
CZ1_CFG2
CZ1_CFG3
IP1[2:0]_CFG4
PLL1 Loop Parameter
IP1[2:0]_CFG5
IP1[2:0]_CFG0
IP1[2:0]_CFG1
IP1[2:0]_CFG2
IP1[2:0]_CFG3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
24
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Bit #
Addr
Description
Hex
Value
00
00
00
00
00
00
01
01
01
01
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
01
01
01
01
80
80
80
80
80
80
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D1[6:0]_CFG0
D1[6:0]_CFG1
D1[6:0]_CFG2
D1[6:0]_CFG3
D1[6:0]_CFG4
D1[6:0]_CFG5
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
N1[7:0]_CFG4
N - Feedback Divider
2 - 4095 (value of “0” is not allowed)
Total feedback with A, using
provided calculation
N1[7:0]_CFG5
N1[7:0]_CFG0
N1[7:0]_CFG1
N1[7:0]_CFG2
N1[7:0]_CFG3
N3[11:8]_CFG0
N1[11:8]_CFG0
N1[11:8]_CFG1
N1[11:8]_CFG2
N1[11:8]_CFG3
N1[11:8]_CFG4
N1[11:8]_CFG5
RZ2[3:0]_CFG4
RZ2[3:0]_CFG5
RZ2[3:0]_CFG0
RZ2[3:0]_CFG1
RZ2[3:0]_CFG2
RZ2[3:0]_CFG3
PLL3 Feedback Divider
N3[11:8]_CFG1
N3[11:8]_CFG2
N3[11:8]_CFG3
N3[11:8]_CFG4
N3[11:8]_CFG5
CZ2_CFG4
CZ2_CFG5
CZ2_CFG0
CZ2_CFG1
CZ2_CFG2
CZ2_CFG3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IP2[2:0]_CFG4
PLL2 Loop Parameter
IP2[2:0]_CFG5
IP2[2:0]_CFG0
IP2[2:0]_CFG1
IP2[2:0]_CFG2
IP2[2:0]_CFG3
D2[6:0]_CFG0
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
D2[6:0]_CFG1
D2[6:0]_CFG2
D2[6:0]_CFG3
D2[6:0]_CFG4
D2[6:0]_CFG5
N2[7:0]_CFG4
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
N2[7:0]_CFG5
N2[7:0]_CFG0
N2[7:0]_CFG1
N2[7:0]_CFG2
N2[7:0]_CFG3
(See Addr 0x4C:0x51 for N2[15:8])
SSENB_CFG0
SSENB_CFG1
SSENB_CFG2
SSENB_CFG3
SSENB_CFG4
SSENB_CFG5
0
0
0
0
0
0
0
0
0
0
0
0
N2[11:8]_CFG0
N2[11:8]_CFG1
N2[11:8]_CFG2
N2[11:8]_CFG3
N2[11:8]_CFG4
N2[11:8]_CFG5
IP3[4]_CFG0
IP3[4]_CFG1
IP3[4]_CFG2
IP3[4]_CFG3
IP3[4]_CFG4
IP3[4]_CFG5
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
1
Reserved
XX
1
Reserved
Reserved
Reserved
XX
1
XX
1
XX
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
25
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Bit #
Addr
Description
Hex
Value
00
7
6
5
4
3
2
1
0
IP3[3:0]_CFG4
RZ3[3:0]_CFG4
RZ3[3:0]_CFG5
RZ3[3:0]_CFG0
RZ3[3:0]_CFG1
RZ3[3:0]_CFG2
RZ3[3:0]_CFG3
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
PLL3 Loop Parameter
IP3[3:0]_CFG5
IP3[3:0]_CFG0
IP3[3:0]_CFG1
IP3[3:0]_CFG2
IP3[3:0]_CFG3
00
00
00
00
00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D3[6:0]_CFG0
D3[6:0]_CFG1
D3[6:0]_CFG2
D3[6:0]_CFG3
D3[6:0]_CFG4
D3[6:0]_CFG5
03
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
03
03
03
03
03
N3[7:0]_CFG4
0C
0C
0C
0C
0C
0C
00
N - Feedback Divider
12 - 4095 (values of “0” through “11”
are not allowed)
N3[7:0]_CFG5
N3[7:0]_CFG0
N3[7:0]_CFG1
N3[7:0]_CFG2
N3[7:0]_CFG3
SSVCO[7:0]_CFG0
SSVCO[7:0]_CFG1
SSVCO[7:0]_CFG2
SSVCO[7:0]_CFG3
SSVCO[7:0]_CFG4
SSVCO[7:0]_CFG5
SS_D3[7:0]_CFG4
SS_D3[7:0]_CFG5
SS_D3[7:0]_CFG0
SS_D3[7:0]_CFG1
SS_D3[7:0]_CFG2
SS_D3[7:0]_CFG3
Reserved
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
00
00
00
00
00
00
SS_D[7:0] - PLL3 Spread Spectrum
Reference Divide
00
00
00
00
00
01
Reserved
OEM0[1:0]
SLEW0[1:0]
INV0
Reserved
S1
S3
03
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
SLEW# - LVTTL only
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
OEM1[1:0]
SLEW1[1:0]
INV1[1:0]
LVL1[1:0]
0x76
00
Output Controls
LVL1[1:0] - output pair OUT1/OUT2
[00] - LVTTL
[01] - LVDS
[10] - LVPECL
[11] - HCSL
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OIT1/OUT2
SLEW2[1:0]
CMEN3
CMEN1
0x77
00
CMEN# - common mode enable
Set to 1 for LVDS
Set to 0 for LVTTL, LVPECL, HCSL
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
26
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Bit #
Addr
Description
Hex
Value
00
7
6
5
4
3
2
1
0
OEM3[1:0]
SLEW3[1:0]
SLEW6[1:0]
INV3[1:0]
LVL3[1:0]
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
OEM3 controls OUT3 and OUT6
Reserved
Reserved
Reserved
00
00
Reserved
CMEN5
CMEN4
00
1
Reserved
Reserved
Reserved
Reserved
XX
Reserved
Reserved
Reserved
Reserved
1
XX
1
XX
1
XX
SSVCO[15:8]_CFG0
SSVCO[15:8]_CFG1
SSVCO[15:8]_CFG2
SSVCO[15:8]_CFG3
SSVCO[15:8]_CFG4
SSVCO[15:8]_CFG5
Reserved
00
00
00
00
00
00
00
00
FF
FF
FF
FF
FF
FF
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
7F
PLL3 Spread Spectrum Feedback
Counter
Reserved
Reserved
Reserved
PM1_CFG0
PM1_CFG1
PM1_CFG2
PM1_CFG3
PM1_CFG4
PM1_CFG5
PM2_CFG4
PM2_CFG5
PM2_CFG0
PM2_CFG1
PM2_CFG2
PM2_CFG3
PM3_CFG0
PM3_CFG1
PM3_CFG2
PM3_CFG3
PM3_CFG4
PM3_CFG5
PM4_CFG4
PM4_CFG5
PM4_CFG0
PM4_CFG1
PM4_CFG2
PM4_CFG3
PM5_CFG0
PM5_CFG1
PM5_CFG2
PM5_CFG3
PM5_CFG4
PM5_CFG5
PM6_CFG4
Q1[6:0]_CFG0
Output Divides
for Q<>111111,
PM=0 - Divide by 2
PM=1, (Q+2)*2
for Q=1111111
PM=0, disable the output divider
PM=1, bypass the output divide,
(divide by 1)
Q1[6:0]_CFG1
Q1[6:0]_CFG2
Q1[6:0]_CFG3
Q1[6:0]_CFG4
Q1[6:0]_CFG5
Q2[6:0]_CFG4
Q2[6:0]_CFG5
Q2[6:0]_CFG0
Q2[6:0]_CFG1
Q2[6:0]_CFG2
Q2[6:0]_CFG3
Q3[6:0]_CFG0
Q3[6:0]_CFG1
Q3[6:0]_CFG2
Q3[6:0]_CFG3
Q3[6:0]_CFG4
Q3[6:0]_CFG5
Q4[6:0]_CFG4
Q4[6:0]_CFG5
Q4[6:0]_CFG0
Q4[6:0]_CFG1
Q4[6:0]_CFG2
Q4[6:0]_CFG3
Q5[6:0]_CFG0
Q5[6:0]_CFG1
Q5[6:0]_CFG2
Q5[6:0]_CFG3
Q5[6:0]_CFG4
Q5[6:0]_CFG5
Q6[6:0]_CFG4
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
27
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Bit #
Addr
Description
Hex
Value
7F
7
6
5
4
3
2
1
0
PM6_CFG5
PM6_CFG0
PM6_CFG1
PM6_CFG2
PM6_CFG3
Q6[6:0]_CFG5
Q6[6:0]_CFG0
Q6[6:0]_CFG1
Q6[6:0]_CFG2
Q6[6:0]_CFG3
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
7F
7F
7F
7F
TSSC[3:0]_CFG0
TSSC[3:0]_CFG1
TSSC[3:0]_CFG2
TSSC[3:0]_CFG3
TSSC[3:0]_CFG4
TSSC[3:0]_CFG5
NSSC[3:0]_CFG0
NSSC[3:0]_CFG1
NSSC[3:0]_CFG2
NSSC[3:0]_CFG3
NSSC[3:0]_CFG4
NSSC[3:0]_CFG5
00
PLL0 Spread Spectrum Control
00
00
00
00
00
DITH_CFG4
DITH_CFG5
DITH_CFG0
DITH_CFG1
DITH_CFG2
DITH_CFG3
X2_CFG4
SSOFFSET[5:0]_CFG4
SSOFFSET[5:0]_CFG5
SSOFFSET[5:0]_CFG0
SSOFFSET[5:0]_CFG1
SSOFFSET[5:0]_CFG2
SSOFFSET[5:0]_CFG3
00
X2_CFG5
X2_CFG0
X2_CFG1
X2_CFG2
X2_CFG3
00
00
00
00
00
SD1[3:0]_CFG0
SD0[3:0]_CFG0
11
SD1[3:0]_CFG1
SD1[3:0]_CFG2
SD1[3:0]_CFG3
SD1[3:0]_CFG4
SD1[3:0]_CFG5
SD0[3:0]_CFG1
SD0[3:0]_CFG2
SD0[3:0]_CFG3
SD0[3:0]_CFG4
SD0[3:0]_CFG5
SM[1:0]_CFG4
SM[1:0]_CFG5
11
11
11
11
11
SRC1[1:0]_CFG4
SRC0[1:0]_CFG4
SRC0[1:0]_CFG5
PDPL3_CFG4
PDPL3_CFG5
PRIMSRC_CFG4
PRIMSRC_CFG5
AE
AE
Output Divide Source Selection
SRC1[1:0]_CFG5
PRIMSRC - primary source - crystal
or ICLOCK
0 = crystal/REFIN
1 = CLKIN
SRC1[1:0]_CFG0
SRC0[1:0]_CFG0
PDPL3_CFG0
SM[1:0]_CFG0
PRIMSRC_CFG0
0xC0
AE
SM = switch mode
0x = manual
10 = reserved
11 = auto-revertive
SRC1[1:0]_CFG1
SRC1[1:0]_CFG2
SRC0[1:0]_CFG1
SRC0[1:0]_CFG2
PDPL3_CFG1
PDPL3_CFG2
SM[1:0]_CFG1
SM[1:0]_CFG2
PRIMSRC_CFG1
PRIMSRC_CFG2
0xC1
0xC2
AE
AE
PDPL3 - PLL3 shutdown
0 = normal
1 = shut down
SRC = MUX control bit prior to DIV#
SRC0[1:0]
00 - DIV1
01 - DIV3
10 - Reference input
SRC1[1:0]_CFG3
SRC0[1:0]_CFG3
PDPL3_CFG3
SM[1:0]_CFG3
PRIMSRC_CFG3
SRC1[2]_CFG0
0xC3
0xC4
AE
24
SRC4[0]_CFG
0
SRC3[2:0]_CFG0
SRC2[2:0]_CFG0
SRC1/SRC2/SRC3.SRC5
000 - DIV1
001 - DIV3
010 - Reference input
011 - Reserved
100 - PLL0
101 - PLL1
110 - PLL2
111 - PLL3
SRC4[0]_CFG
1
SRC3[2:0]_CFG1
SRC3[2:0]_CFG2
SRC3[2:0]_CFG3
SRC3[2:0]_CFG4
SRC3[2:0]_CFG5
SRC2[2:0]_CFG1
SRC2[2:0]_CFG2
SRC2[2:0]_CFG3
SRC2[2:0]_CFG4
SRC2[2:0]_CFG5
SRC1[2]_CFG1
SRC1[2]_CFG2
SRC1[2]_CFG3
SRC1[2]_CFG4
SRC1[2]_CFG5
0xC5
0xC6
0xC7
0xC8
0xC9
24
24
24
24
24
SRC4[0]_CFG
2
SRC4[0]_CFG
3
SRC4[0]_CFG
4
SRC4[0]_CFG
5
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
28
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Bit #
Addr
Description
Hex
Value
49
7
6
5
4
3
2
1
0
SRC6[2:0]_CFG4
SRC6[2:0]_CFG5
SRC6[2:0]_CFG0
SRC6[2:0]_CFG1
SRC6[2:0]_CFG2
SRC6[2:0]_CFG3
SRC5[2:0]_CFG4
SRC5[2:0]_CFG5
SRC5[2:0]_CFG0
SRC5[2:0]_CFG1
SRC5[2:0]_CFG2
SRC5[2:0]_CFG3
SRC4[2:1]_CFG4
SRC4[2:1]_CFG5
SRC4[2:1]_CFG0
SRC4[2:1]_CFG1
SRC4[2:1]_CFG2
SRC4[2:1]_CFG3
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
SRC6
000 - Reserved
001 - Reserved
010 - Reference input
011 - Reserved
100 - Reserved
101 - PLL1
110 - Reserved
111 - Reserved
Quiet MUX
49
49
49
49
49
Default Configuration: OUT1 = Reference Clock output, all other outputs turned off.
1
. Memory bytes do not exist. Readback will be last value in shift register. If reading sequentially, value in 0x51 will be
returned.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
29
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Marking Diagram
4502LI
#YYWW$
Notes:
1. “#” is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “$” is the assembly mark code.
4. “I” indicates industrial temperature range.
Thermal Characteristics for 24-QFN
Parameter
Symbol
Conditions
Min.
Typ.
47.6
42.4
39.9
60.7
Max.
Units
C/W
C/W
C/W
C/W
Thermal Resistance Junction to
Ambient
Still air
JA
JA
JA
JC
1 m/s air flow
2.5 m/s air flow
Thermal Resistance Junction to Case
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The
package information is the most current data available.
www.idt.com/document/psc/nlnlg24p1-package-outline-40-x-40-mm-body-05-mm-pitch-qfn-epad-size-245-x-245-mm
Ordering Information
Part / Order Number
5V49EE502NLGI
Shipping Packaging
Package
4 × 4 mm 24-QFN
4 × 4 mm 24-QFN
Temperature
-40 to +85 C
-40 to +85 C
Tray
Reel
5V49EE502NLGI8
“G” after the two-letter package code denote Pb-Free configuration, RoHS compliant.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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Revision History
Date
Description of Change
September 24, 2012 Change differential outputs from 5pF loads to 2pF loads so that they are consistent with the industry.
Capacitive loads were also added to the test circuit diagrams for HCSL outputs. Slew Rate (t4) Output Load
test conditions were changed from 15pF to 5pF.
July 10. 2015
Added the following note under AC Timing Electrical Characteristics table:
“Not guaranteed until customer specific configuration is approved by IDT.”
August 3, 2016
June 18, 2018
Changed 5V49EE502NLGI shipping packaging from tray to tube.
1. Changed shipping packaging from tube to tray.
2. Updated package outline drawings.
3. Updated legal disclaimer.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
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Fax: 408-284-2775
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Tech Support
www.IDT.com/go/support
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www.idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products
and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the
described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of
others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where
the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product
in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other
countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of
common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm
NLG24P1, PSC-4192-01, Rev 02, Page 1
© Integrated Device Technology, Inc.
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm
NLG24P1, PSC-4192-01, Rev 02, Page 2
Package Revision History
Description
Date Created Rev No.
Sept 9, 2016
Rev 01 Add Chamfer on Epad
Sept 13, 2018 Rev 02 New Format, Recalculate Land Pattern Change QFN to VFQFPN
© Integrated Device Technology, Inc.
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