5V9352PFGI [IDT]
TQFP-32, Tray;
| 型号： | 5V9352PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-32, Tray 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK
DRIVER ZERO DELAY BUFFER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCT 28, 2014
FEATURES:
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
dividecircuitryallowsforoutputfrequencyratiosof1:1, 2:1, 3:1, and3:2:1.
The output frequency relationship is controlled by the fSEL frequency
control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL
compatibleinputs
• Phase-lock loop clock distribution for high performance clock
tree applications
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
• No external RC network required for PLL loop stability
• Operates at 3.3V/2.5V VCC
• Spread Spectrum Compatible
BecauseitisbasedonPLLcircuitry, the5V9352requiresastabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the PLL_EN to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
• Operating frequency up to 200MHz
• Compatible with Motorola MPC9352
• Available in 32-pin TQFP package
• Use replacement part: 87952AYILF
DESCRIPTION:
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
preciselyalign, inbothfrequencyandphase. The5V9352operatesat2.5V
and 3.3V.
FUNCTIONALBLOCKDIAGRAM
BANK A
QA0
CCLK
1
1
0
1
0
6
4
2
2
REFCLK
FBIN
REF
FB
QA1
QA2
VCO
0
PLL
QA3
QA4
PLL_En
VCO_SEL
fSELA
BANK B
QB0
QB1
QB2
QB3
1
0
fSELB
fSELC
BANK C
1
QC0
QC1
0
MR/OE
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2013
1
c
2003 Integrated Device Technology, Inc.
DSC 5973/19
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
VCO_SEL
fSELC
GND
QB1
QB0
VCC
VCC
QA4
QA3
GND
fSELB
fSELA
MR/OE
REFCLK
GND
18
17
FBIN
9
10 11 12 13 14 15 16
TQFP
TOP VIEW
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE
Parameter Description
Min.
⎯
Typ. Max.
Unit
pF
Symbol
VCC
Rating
Max.
–0.3to+3.6
–0.3toVCC+0.3
±20
Unit
V
CIN
InputCapacitance
4
⎯
⎯
SupplyVoltageRange
InputVoltageRange
InputCurrent
CPD
PowerDissipation
Capacitance
⎯
10
pF
VI
V
IIN
mA
mA
°C
IOUT
TSTG
DCOutputCurrent
StorageTemperatureRange
±50
–65to+125
NOTE:
LOGICDIAGRAM(1,2)
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress rating only, and functional
operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
RF
VCCA
VCC
10nF
CF
GENERALSPECIFICATIONS
VCC
Symbol Description
Min. Typ. Max. Unit
VTT
HBM
LU
OutputTerminationVoltage
ESDProtection(humanbodymodel) 2000
Latch-UpImmunity 200
VCC/2
V
V
33...100nF
mA
NOTES:
1. IDT5V9352 requires an external RC filter for the analog power supply pin VCCA.
2. For VCC = 2.5V, RF = 9-10Ω, CF = 22μF.
For VCC = 3.3V, RF = 5-15Ω, CF = 22μF.
2
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLES
Control Pin
VCO_SEL
MR/OE
Logic 0
fVCO
Logic 1
fVCO / 2
fSELA
QAn
÷4
fSELB
QBn
÷4
fSELC
QCn
÷2
0
1
0
1
0
1
OutputEnable
Outputsdisable(high-impedancestate)and
resetofthedevice.
DisablePLL
÷6
÷2
÷4
PLL_En
EnablePLL
NOTE:
1. IDT5V9352 requires reset at power up and after any loss of PLL lock. Length of reset
pulse should be greater than two REF CLK cycles (REFCLK).
PINDESCRIPTION
Terminal
Name
REFCLK
FBIN
No.
6
Type
Description
I
I
Referenceclockinput
Feedbackinput.
8
VCCA
10
PWR
Analogpowersupply
Negative power supply
GND
7, 13, 17, 24, Ground
28,29
VCO_SEL
MR/OE
QA(0:4)
1
5
I
I
AllowsforthechoiceoftwoVCOrangestooptimizePLLstabilityandjitterperformance
AllowstheusertoforcetheoutputsintoHIGHimpedenceforboardleveltest
12, 14, 15,
18,19
QB(0:3)
QC(0:1)
VCC
22, 23, 26, 27
30,31
O
Clock outputs. These outputs provide low skew copies of REFCLK or can be at different frequencies than REFCLK.
Positive power supply for I/O and core
11, 16, 20, 21, PWR
25,32
PLL_EN
9
I
I
PLL enable input. When set LOW, PLL is enabled. When set HIGH, PLL is disabled.
Frequencycontrolpin
fSEL(C:A)
2, 3, 4
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C, VCC = 3.3V ± 5%
Parameter
VIH
Description
Input HIGH Level
Test Conditions
Min.
Typ.(1)
Max.
VCC + 0.3
0.8
Unit
V
2
VIL
InputLOWLevel
V
VOH
HIGH Level Output Voltage
LOWLevelOutputVoltage
IOH = –24mA
IOL = 12mA
IOL = 24mA
2.4
V
VOL
0.3
V
0.55
ZOUT
II
OutputImpedance
InputCurrent(2)
MaximumQuiescentSupplyCurrent(3) All VCC pins
14 - 17
3
Ω
VI = VCC or GND
±200
µA
mA
mA
ICC
1
5
ICCA
PLL Supply Current VCCA pin
NOTES:
1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
2. Inputs have pull-down resistors affecting the input current.
3. Icc is the DC current consumption of the device with all outputs open in high-impedance state and the inputs in its default state or open.
3
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
INPUTTIMINGREQUIREMENTS
TA = –40°C to +85°C, VCC = 3.3V ± 5%
Symbol
Description
Min.
50
Max.
100
66.6
50
Unit
÷4feedback
÷6feedback
÷8feedback
÷12feedback
33.3
25
REF
ReferenceCLKinputinPLLmode(1)
MHz
16.67
33.3
250
75
ReferenceCLKinputinPLLbypassmode(2)
Input clock duty cycle
d H
25
%
tR, tF
Maximum input rise and fall times, 0.8V to 2V
⎯
1
ns
NOTES:
1. PLL mode requires PLL_EN = 0 to enable the PLL and zero delay operation.
2. In PLL bypass mode, the IDT5V9352 divides the input reference clock.
4
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS(1)
TA = –40°C to +85°C, VCC = 3.3V ± 5%
Symbol
Characteristic
OutputRise/FallTime
Test Conditions
0.55V to 2.4V
Min.
Typ.
Max.
1
Unit
tR,tF
0.1
ns
AllOutputs, anyfrequency
withinQA outputbank
withinQB outputbank
withinQC outputbank
200
200
100
100
400
200
100
66.6
50
tSK(O)
fVCO
fMAX
OutputtoOutputSkew
ps
PLL VCO Lock Range(2)
MaximumOutputFrequency
200
100
50
MHz
MHz
÷2output
÷4output
÷6output
÷8output
÷12output
33.3
25
16.67
47
33.3
53
tPW
tPD
Output Duty Cycle
50
%
REFCLK to FBIN Delay
PLLLocked
fREF < 40MHz
-200
-50
+150
+150
8
ps
fREF > 40MHz, PLL locked
tPLZ
tPHZ
tPZL
tPZH
OutputDisableTime
ns
ns
MR/OE (LOW-HIGH) to any Q
OutputEnableTime
10
MR/OE (HIGH-LOW) to any Q
Outputfrequenciesmixed
Outputsinany÷4and÷6combination
Alloutputssamefrequency
Outputfrequenciesmixed
Outputsinany÷4and÷6combination
Alloutputssamefrequency
÷4 feedback divider RMS (1σ)
÷6 feedback divider RMS (1σ)
÷8 feedback divider RMS (1σ)
÷12feedbackdividerRMS(1σ)
÷4feedback
400
250
100
200
150
75
tJ
Cycle-to-CycleJitter
PeriodJitter
ps
ps
ps
tJ(PER)
tJ(φ)
15
I/O Phase Jitter
20
18-20
25
3 - 10
1.5 - 6
1 - 3.5
0.5 - 2
BW
PLLClosedLoopBandwidth
Maximum PLL Lock Time
÷6feedback
MHz
ms
÷8feedback
÷12feedback
tLOCK
10
NOTES:
1. AC characteristics apply for parallel output termination of 50Ω to VTT.
2. The input frequency on CCLK must match the VCO frequency range divided by the feedback divide ratio FB: freq. = fvco ÷ FB.
5
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C, VCC = 2.5V ± 5%
Parameter
VIH
Description
Input HIGH Level
Test Conditions
Min.
1.7
Typ.(1)
Max.
VCC + 0.3
0.7
Unit
V
LVCMOS
VIL
InputLOWLevel
LVCMOS
–0.3
1.8
V
VOH
HIGH Level Output Voltage
LOWLevelOutputVoltage
OutputImpedance
IOH = –15mA
IOL = 15mA
V
VOL
0.6
V
ZOUT
17 - 20
2
Ω
(2)
II
InputCurrent
VI = VCC or GND
±200
µA
mA
mA
(3)
ICC
Maximum Quiescent Supply Current
PLL Supply Current
1
5
ICCA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
2. Inputs have pull-down resistors affecting the input current.
3. Icc is the DC current consumption of the device with all outputs open in High-Impedance state and the inputs in its default state (or open).
INPUTTIMINGREQUIREMENTS
TA = –40°C to +85°C, VCC = 2.5V ± 5%
Symbol
Description
Min.
50
Max.
Unit
÷4feedback
÷6feedback
÷8feedback
÷12feedback
100
66.6
50
REF
ReferenceCLKinput(1)
33.3
25
MHz
16.67
33.3
250
75
ReferenceCLKinputinPLLbypassmode(2)
Input clock duty cycle
d H
25
%
tR, tF
Maximum input rise and fall times, 0.8V to 2V
⎯
1
ns
NOTES:
1. Maximum and minimum input reference is limited by the VCO clock range and the feedback divider.
2. In PLL bypass mode, the 5V9352 divides the input reference clock.
6
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS(1)
TA = –40°C to +85°C, VCC = 2.5V ± 5%
Symbol
Characteristic
OutputRise/FallTime
Test Conditions
0.6V to 1.8V
Min.
Typ.
Max.
1
Unit
tR,tF
0.1
ns
AllOutputs, anyfrequency
withinQA outputbank
withinQB outputbank
withinQCoutputbank
200
200
100
100
400
200
100
66.6
50
tSK(O)
fVCO
fMAX
OutputtoOutputSkew
PLL VCO Lock Range
MaximumOutputFrequency
ps
200
100
50
MHz
MHz
÷2output
÷4output
÷6output
÷8output
÷12output
33.3
25
16.67
47
33.3
53
tPW
tPD
Output Duty Cycle
50
%
REFCLK to FBIN Delay
PLLLocked
fREF < 40MHz
fREF > 40MHz
-200
-50
+150
+150
8
ps
tPLZ
tPHZ
tPZL
tPZH
OutputDisableTime
ns
ns
MR/OE (LOW-HIGH) to any Q
OutputEnableTime
10
MR/OE (HIGH-LOW) to any Q
Outputfrequenciesmixed
Outputsinany÷4and÷6combination
Alloutputssamefrequency
Outputfrequenciesmixed
Outputsinany÷4and÷6combination
Alloutputssamefrequency
÷4 feedback divider RMS (1σ)
÷6 feedback divider RMS (1σ)
÷8 feedback divider RMS (1σ)
÷12feedbackdividerRMS(1σ)
÷4feedback
400
250
100
200
150
75
tJ
Cycle-to-CycleJitter
PeriodJitter
ps
ps
ps
tJ(PER)
tJ(φ)
15
20
I/O Phase Jitter
18-20
25
1 - 8
BW
PLLClosedLoopBandwidth
Maximum PLL Lock Time
÷6feedback
0.7 - 3
0.5 - 2.5
0.4 - 1
MHz
ms
÷8feedback
÷12feedback
tLOCK
10
NOTE:
1. AC characteristics apply for parallel output termination of 50Ω to VTT.
7
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
IDT5V9352 D.U.T.
ZO = 50
ZO = 50
Pulse
Generator
Z = 50
RT = 50
RT = 50
VTT
VTT
AC Test Reference for VCC = 2.5V and VCC = 3.3V
VCC
2V
2V
VCC/2
0.8V
0V
REF CLK
FBIN
0.8V
Input
1ns
1ns
tPD
Input Characteristics for 3.3V
Prop Delay
VCC
1.7V
1.7V
VCC/2
0.7V
0V
0.7V
Input
Any Q
Any Q
1ns
1ns
tSK
Input Characteristics for 2.5V
Skew Calculations
VOH
1.8V
VOH
2.4V
1.8V
2.4V
VCC/2
VCC/2
0.6V
VOL
0.6V
tR
0.55V
VOL
0.55V
tR
Output
Output
tF
tF
Output Test Conditions for VCC = 2.5V ± 5%
Output Test Conditions for VCC = 3.3V ± 5%
8
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
CCLK
FBIN
TJ(0) = T0 - T1 MEAN
I/O Jitter
VCC
VCC/2
GND
tP
T0
tPW = tP/T0 x 100%
Output Duty Cycle
TJ = Tn - Tn+1
Tn+1
Tn
Cycle-to-Cycle Jitter
TJ(PER) = Tn - 1/f0
T0
Period Jitter
9
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
-40°C to +85°C (Industrial)
I
Thin Quad Flat Pack
TQFP - Green
PF
PFG
5V9352 3.3V/2.5V Phase-Lock Loop Clock Driver
Zero Delay Buffer
10
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
REVISIONHISTORY
Rev
Table
Page
Discription of Change
Date
A
1
NRND - Not Recommended for New Designs
5/20/13
PDN - Product Discontinuation Notice - Last Time Buy Expires
October 28, 2014 - PDN# CQ-13-02
A
1
12/19/13
11
IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
We’ve Got Your Timing Solution.
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San Jose, CA 95138
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information
in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express
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their respective third party owners.
Copyright 2013. All rights reserved.
12
相关型号：
5V9352PFGI8
PLL Based Clock Driver, 5V Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32
IDT
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