5V9888PFGI [IDT]
Clock Generator, PQFP32;
| 型号： | 5V9888PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PQFP32 |
| 文件： | 总37页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT5V9888
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
FEATURES:
DESCRIPTION:
• Three internal PLLs
The IDT5V9888 is a programmable clock generator intended for high
performancedata-communications,telecommunications,consumer,and
networking applications. There are three internal PLLs, each individually
programmable,allowingforthreeuniquenon-integer-relatedfrequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
− LVTTL: up to 200MHz
− LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
− Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation
capability
• I/O Standards:
− Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
− Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual
switchover options
TheIDT5V9888canbeprogrammedthroughtheuseoftheI2CorJTAG
interfaces. The programming interface enables the device to be pro-
grammedwhenitisinnormaloperationorwhatiscommonlyknownasin-
systemprogrammable. AninternalEEPROMallowstheusertosaveand
restore the configuration of the device without having to reprogram it on
power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. Thisallowstheusertogeneratethreeuniquenon-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
totailorthePLLresponsetotheapplication. Forinstance,theusercantune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3VVDD
• Available in TQFP and VFQFPN packages
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 2007
1
c
2007 Integrated Device Technology, Inc.
DSC 7044/13
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
FUNCTIONALBLOCKDIAGRAM
XTALOUT
OSC.
XTALIN/REFIN
OUT1
P2 Divider
10-Bit
/2
/2
OUT2
OUT3
P3 Divider
10-Bit
PLL 0
CLKIN
OUT4 (1)
OUT4 (1)
P4 Divider
10-Bit
PLL 1
PLL 2
/2
OUT5(1)
OUT5 (1)
P5 Divider
10-Bit
SHUTDOWN/OE
WRITE ENABLE
/2
/2
P6 Divider
10-Bit
EEPROM
OUT6
GOUT0/TDO/
LOSS_LOCK
GIN4/CLK_SEL
I 2 C/JTAG
Control Block for
Multi-Purpose I/O, Programming, Features
GOUT1/
LOSS_CLKIN
NOTE:
1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. As LVTTL, OUT4 and OUT5 can be configured to be non-inverting.
2
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
PINCONFIGURATION
32 31 30 29 28 27 26 25
28 27 26 25 24 23 22
CLKIN
GND
GIN2/TMS
VDD
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
21
20
19
18
17
16
15
CLKIN
GND
GIN2/TMS
VDD
1
2
3
4
5
6
7
GOUT1/LOSS_CLKIN
XTALIN/REFIN
I 2C/JTAG
GOUT1/LOSS_CLKIN
XTALIN/REFIN
I 2C/JTAG
GIN4/CLK_SEL
GND
GIN4/CLK_SEL
XTALOUT
OUT1
VDD
GIN1/SCLK/TCLK
GIN0/SDA/TDI
GND
XTALOUT
OUT1
GIN1/SCLK/TCLK
GIN0/SDA/TDI
VDD
OUT3
VDD
OUT3
8
9
10 11 12 13 14
9
10 11 12 13 14 15 16
VFQFPN
TQFP
TOP VIEW
TOP VIEW
3
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
PF32
Pin#
NL28
Pin#
Pin Name
CLKIN
I/O
Type
LVTTL
Description
1
4
1
4
I
I
InputClock
XTALIN/REFIN
XTALOUT
LVTTL
CRYSTAL_IN-Referencecrystalinputorexternalreferenceclockinput
5
5
O
I
LVTTL
CRYSTAL_OUT-Referencecrystalfeedback
GIN0/SDAT/TDI
GIN1/SCLK/TCK
GIN2/TMS
19
20
24
27
16
17
21
24
LVTTL(3)
LVTTL(3)
LVTTL(3)
LVTTL(3)
Multi-purposeinputs. CanbeusedforFrequencyControl,SDAT(I2C),orTDI(JTAG).
Multi-Purposeinputs. CanbeusedforFrequencyControl,SCLK(I2C),orTCK(JTAG).
Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG).
I
I
WRITE ENABLE
I
Write Enable pin. This pin must be pulled HIGH during normal operation. HIGH =
normal operation, LOW = Enable writing to internal EEPROM.
GIN3/TRST
GIN4/CLK_SEL
SHUTDOWN/OE
25
21
28
22
18
23
I
I
I
LVTTL(3)
LVTTL(3)
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or TRST (JTAG).
Multi-Purposeinputs. CanbeusedforFrequencyControlorinputclockselector.
Enables/disablestheoutputsorpowersdownthechip.TheSPbit(0x1C)controlsthe
polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)
I2C/JTAG
OUT1
22
6
19
6
I
3-level(2)
LVTTL
I2C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW).
Configurableclockoutput1.Canalsobeusedtobufferthereferenceclock.
Configurableclockoutput2
O
O
O
O
O
OUT2
29
8
25
7
LVTTL
OUT3
LVTTL
Configurableclockoutput3
OUT4
10
11
8
Adjustable(1)
Adjustable(1)
Configurableclockoutput4,Single-EndedorDifferentialwhencombinedwithOUT4
OUT4
9
Configurable complementary clock output 4, Single-Ended or Differential when
combinedwithOUT4
OUT5
15
16
13
14
O
O
Adjustable(1)
Adjustable(1)
Configurableclockoutput5,Single-EndedorDifferentialwhencombinedwithOUT5
OUT5
Configurable complementary clock output 5, Single-Ended or Differential when
combinedwithOUT5
OUT6
13
31
11
27
O
O
LVTTL
LVTTL(3)
Configurableclockoutput6
GOUT0/TDO/LOSS_LOCK
Multi-PurposeOutput.CanbeprogrammedtouseasPLLLOCKsignal,LOSS_LOCK
or TDO in JTAG mode.
GOUT1/LOSS_CLKIN
3
3
O
LVTTL
Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN.
3.3V Power Supply
VDD
7,12,17, 10,15,20
23,26,32
28
GND
2,9,14,
18,30
2,12,26
Ground
NOTES:
1. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.
3. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I2C (SCLK and SDAT) signals share the same pins with GIN signals.
4
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
PLLFEATURESANDDESCRIPTIONS
D0 Divider
VCO
M0 Multiplier
Spread
Spectrum
Modulation
PLL0 Block Diagram
D1 Divider
VCO
M1 Multiplier
Spread
Spectrum
Modulation
PLL1 Block Diagram
D2 Divider
VCO
M2 Multiplier
PLL2 Block Diagram
5
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
Spread Spectrum
Pre-Divider (D) Values
Multiplier (M) Values
Programmable Loop Bandwidth
GenerationCapability
PLL0
PLL1
PLL2
1 - 255
1 - 255
1 - 255
2 - 8190
2 - 8190
1 - 4095
yes
yes
yes
yes
yes
no
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)
REFERENCE CLOCK INPUT PINS AND
SELECTION
Parameter
Bits
Step
Min
Max
Units
XTALCAP
8
0.125
0
32
pF
The5V9888supportsuptotwoclockinputs.Oneoftheclockinputs(XTALIN/
REFIN) can be driven by either an external crystal or a reference clock. The
secondclockinput(CLKIN)canonlybedrivenfromanexternalreferenceclock.
Either clock input can be set as a the primary clock. The primary clock
designation istoestablishwhichisthemainreferenceclocktothePLLs. The
non-primaryclockisdesignatedasthesecondaryclockincasetheprimaryclock
goes absent and a backup is needed. The PRIMCLK bit (0x34) determines
whichclockinputwillbetheprimaryclock. WhenPRIMCLKbitis"0",itwillselect
XTALIN/REFINastheprimary,andwhen"1",itwillselectCLKINastheprimary.
Thetwoexternalreferenceclockscanbemanuallyselected using theGIN4/
CLK_SEL pin, except in Manual Frequency Control (MFC) mode 2, or via
programmingbyhardwiringtheCLK_SELpinandtogglingthePRIMCLKbit.
For more details on the MFC modes, refer to the CONFIGURING MULTI-
PURPOSEI/Ossection. WhenCLK_SELisLOW,theprimaryclockisselected
andwhenHIGH,thesecondaryclockisselected. TheSMbits(0x34)mustbe
setto"0x"formanualswitchoverwhichisdetailedinSWITCHOVERMODES
section.
When using an external reference clock instead of a crystal on the XTAL/
REFINpin,theinputloadcapacitorsmaybecompletelybypassed.Thisallows
fortheinputfrequencytobeupto200MHz. Whenusinganexternalreference
clock,theXTALOUTpinmustbeleftfloating,XTALCAPmustbeprogrammed
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must
be set to the default value of "11".
CLKIN Pin
CLKIN pin is a regular clock input pin, and can be driven up to 400MHz.
PRE-SCALER,FEEDBACK-DIVIDER,AND
POST-DIVIDER
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider
whichallowstheusertogeneratethreeuniquenon-integer-relatedfrequencies.
For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The
following equation governs how the frequency on output banks OUT2-6 is
calculated.
GIN4/CLK_SEL
Selected Clock Input
L
Primary
FOUT = FIN *(MD )
H
Secondary
(Eq. 2)
P * 2
WhereFIN isthereferencefrequency,Misthetotalfeedback-dividervalue,
Disthepre-scalervalue,Pisthetotalpost-dividervalue,andFOUTistheresulting
output bank frequency. The value 2 in the denominator is due to the divide-
by-2oneachoftheoutputbanksOUT2-6. NotethatOUT1doesnothaveany
typeofpost-divider. Also,programminganyofthedividersmaycauseglitches
ontheoutputs.
Crystal Input (XTALIN/REFIN)
Thecrystaloscillatorsshouldbefundamentalmodequartzcrystals:overtone
crystals are not suitable. Crystal frequency should be specified for parallel
resonancewith50Ωmaximumequivalentseriesresonance.
WhentheXTALIN/REFINpinisdrivenbyacrystal,itisimportanttosetthe
internal oscillator inverter drive strength and internal tuning/load capacitor
values correctly to achieve the best clock performance. These values are
programmable through either I2C or JTAG interface to allow for maximum
compatibilitywithcrystalsfromvariousmanufacturers,processes,performances,
andqualities.Theinternalloadcapacitorsaretrueparallel-platecapacitorsfor
ultra-linearperformance. Parallel-platecapacitorswerechosentoreducethe
frequencyshiftthatoccurswhennon-linearloadcapacitanceinteractswithload,
bias, supply, and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are sensitive to absolute
frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined
byXTALCAP[7:0]bits,(0x07).Theloadcapacitancecanbesetwitharesolution
of 0.125 pF for a total crystal load range of 3.5pF to 35.4pF. Check with the
vendor'scrystalloadcapacitancespecificationfortheexactsettingtotunethe
internalloadcapacitor. Thefollowingequationgovernshowthetotalinternal
loadcapacitanceisset.
Pre-Scaler
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the
referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter,
thedivideddownclockmustbehigherthan400KHz;itisbesttousethesmallest
Ddividervaluepossible. IfDissetto'0x00',thenthiswillpowerdownthePLL
andalltheoutputsassociatedwiththatPLL.
6
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Feedback-Divider
N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled
foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM
GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional
divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread
spectrumgenerationandfractionaldividescapability. The12-bitfeedback-dividerintegervaluesrangefrom1to4095.
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2
PLL0 and PLL1:
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled)
(Eq. 3)
(Eq. 4)
A[3:0] = 0000 = -1
= 0001 = 1
= 0010 = 2
= 0011 = 3
.
.
.
= 1111 = 15
Note: A[3:0] < (N[11:0] - 5), must be met when using A. N cannot be programmed with a value of 4, 8, or 16 when using A.
PLL2:
M = N[11:0]
(Eq. 5)
TheusercanachieveanevenoroddintegerdivideratioforbothPLL0andPLL1bysettingtheA[3:0]bitsaccordinglyanddisablingthespreadspectrum.
AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL
DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1200MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample,
if thereferenceclockis100MHzanda200MHzclockisrequired,toachievethebestjitterperformance,multiplythe100MHzby12togettheVCOrunningat
thehighestpossiblefrequencyof1200MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply
the25MHzby40togettheVCOrunningat1000MHzandthendivideitdowntoget20MHz. IfNissetto'0x00', theVCOwillslewtotheminimumfrequency.
Post-Divider
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.
Thereistheoptiontochoosebetweendisablingthepost-divider, utilizingadiv/1, adiv/2, orthe10-bitpost-dividerbyusingthePM[1:0]bits.. Eachbank,
exceptforOUT1,hasasetofPMbits. Whendisablingthepost-divider,noclockwillappearattheoutputs,butwillremainpoweredon. Thevaluesarelisted
inthetablebelow.
P
00
01
PM[1:0]
00
P Post-Divider
disabled
To Outputs
VCO
/2
10
11
/2
01
div/1
/ (Q+2)
10
div/2
11
Q[9:0] + 2 (Eq. 6)
PM[1:0]
Post-Divider Diagram
7
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
Notethattheactual10-bitpost-dividervaluehasa2addedtotheintegervalueQandtheoutputsareroutedthroughanotherdiv/2block. Thepost-divider
shouldneverbedisabledunlesstheoutputbankwillneverbeusedduringnormaloperation. TheoutputfrequencyrangeforLVTTLoutputsarefrom4.9KHz
to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.
SPREADSPECTRUMGENERATION
PLL0andPLL1supportspreadspectrumgenerationcapability,whichusershavetheoptionofturningonandoff. Spreadspectrumprofile,frequency,and
spreadarefullyprogrammable(withinlimits). TheprogrammablespreadspectrumgenerationparametersareTSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],
SD[3:0],DITH,andX2bits. Thesebitsareinthememoryaddressrangeof0x60to0x67forPLL0and0x68to0x6FforPLL1. Thespreadspectrumgeneration
on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the
A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.
TSSC[3:0]
Thesebitsareusedtodeterminethenumberofphase/frequencydetectorcyclesperspreadspectrumcycle(ssc)steps. Themodulationfrequencycanbe
calculatedwiththeTSSCbitsinconjunctionwiththeNSSCbits. ValidTSSCintegervaluesforthemodulationfrequencyrange from5to14.
NSSC[3:0]
Thesebitsareusedtodeterminethenumberofdelta-encodedsamplesusedforasinglequadrantof thespreadspectrumwaveform. Allfourquadrants
ofthespreadspectrumwaveformaremirrorimagesofeachother. ThemodulationfrequencyisalsocalculatedbasedofftheNSSCbitsinconjunctionwiththe
TSSC bits. Valid NSSC integer values range from 1 to 6.
SS_OFFSET[5:0]
ThesebitsareusedtoprogramthefractionaloffsetwithrespecttothenominalMintegervalue. Forcenterspread,theSS_OFFSETshouldbesetto'0'so
thespreadspectrumwaveformisaboutthenominalM(Mnom)value. Fordownspread,theSS_OFFSET>'0'sothespreadspectrumwavformisaboutthe
(Mideal-1=Mnom)value. Thedownspreadpercentagecanbethoughtofintermsofcenterspread. Forexample,adownspreadof-1%canalsobeconsidered
as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.
SD[3:0]
Thesebitsareusedtoshapetheprofileofthespreadspectrumwaveform. Thesearedelta-encodedsamplesofthewaveform. Therearetwelvesetsof
SDsamplesforeachPLL. TheNSSCbitsdeterminehowmanyofthesesamplesareusedforthewaveform. Thesumofthesedelta-encodedsamples(sigma-
delta-encodedsamples)determinetheamountofspreadandshouldnotexceed(63-SS_OFFSET). Themaximumspreadisinversely proportionaltothe
nominalMintegervalue.
DITH
Thisbitisforditheringthesigma-delta-encodedsamples. Thiswillrandomizetheleast-significantbitoftheinputtothespreadspectrummodulator. Setthe
bitto'1'toenabledithering.
X2
Thisbitwilldoublethetotalvalueofthesigma-delta-encoded-sampleswhichwillincreasetheamplitudeofthespreadspectrumwaveformbyafactoroftwo.
WhenX2is'0', theamplituderemainsnominalbutifsetto'1', theamplitudeisincreasedbyx2.
Thefollowingequationsgovernhowthespreadspectrumisset:
TSSC = TSSC[3:0] + 2 (Eq. 7)
NSSC = NSSC[3:0] * 2 (Eq. 8)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 9)
where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12.
Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100
(Eq. 10)
2
if 1 < Amp < 2, then set X2 bit to '1'.
8
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Modulation frequency:
FPFD = FIN / D (Eq. 11)
FVCO = FPFD * MNOM (Eq. 12)
FSSC = FPFD / (4 * Nssc * Tssc)
(Eq. 13)
Spread:
ΣΔ = SD0 + SD1 + SD2 + … + SD11
the number of samples used depends on the NSSC value
ΣΔ ≤ 63 - SS_OFFSET
±Spread% =
ΣΔ * 100
64 * (2*N[11:0] + A{3:0} + 1)
(Eq. 14)
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
Profile:
WaveformstartswithSS_OFFSET, SS_OFFSET+SDJ, SS_OFFSET+SDJ+1, etc.
Spread Spectrum Using Sinusoidal Profile
9
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.
Sincethespreadiscenter,theSS_OFFSETcanbesetto'0'. SolveforthenominalMvalue;keepinmindthatthenominalMshouldbechosentomaximize
the VCO. Start with D = 1, using Eq.10 and Eq.11.
MNOM = 1100MHz / 25MHz = 44
Using Eq.4, we arbitrarily choose N = 20, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used
toenhancetheprofileofthespreadspectrumwaveform.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
UseEq.14todeterminethevalueofthesigma-delta-encodedsamples.
±2% = ΣΔ * 100
64 * 44
ΣΔ = 56.32
Eitherroundupordowntothenearestintegervalue. Therefore,weendupwith56or57forsigma-delta-encodedsamples. Sincethesigma-delta-encoded
samplesmustnotexceed63with SS_OFFSETsetto'0', 56or57iswellwithinthelimits. Itisthediscretionoftheuserto definetheshapeof theprofilethat
isbettersuitedfortheintendedapplication.
Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 56 and 57 are ±1.99% and ±2.02%, respectively.
UseEq.10todetermineiftheX2bitneedstobeset;
Amplitude = 44 * (1.99 or 2.02) / 100 = 0.44 < 1
2
Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.
The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.
Notethatthe5V9888shouldnotbeprogrammedwithTSSC>'0',SS_OFFSET='0',andSD='0'inordertopreventanunstablestateinthemodulator. The
PLLloopbandwidthmustbeatleast10xthemodulationfrequencyalongwithhigherdamping(largerωuz)topreventthespreadspectrumfrombeingfiltered
andreduceextraneousnoise. RefertotheLOOPFILTERsectionformoredetailonωuz.TheA[3:0]mustbeusedforspreadspectrum,evenifthetotalmultiplier
value is an even integer.
FRACTIONALDIVIDER
There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the
SS_OFFSETbitswoulddeterminethefractionaldividevalue.SeetheSPREADSPECTRUMGENERATIONsectionformoredetailsontheTSSC,SD,and
SS_OFFSET bits. The following equation governs how the fractional divide value is set.
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64
10
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Thespreadspectrumparameterssuchasthemodulationfrequencyandprofilewillnotbeenablednorwillithaveanyimpacton thePLLoutputwhenthe
PLLisprogrammedforfractionaldivide.
Thefollowingisanexampleofhowtosetthefractionaldivider.
Example
FIN = 20MHz, FOUT1 = 168.75MHz, FOUT2 = 350MHz
Solving for 350MHz using Eq.2 and Eq.3 with PLL0 and spread spectrum off,
350MHz = 20MHz * (M / D)
P * 2
Forbetterjitterperformance,keepDassmallaspossible
350MHz * 2 = M = 35
20MHz
P
1
Therefore, we have D = 1, M = 35 (N = 16, A = 2) for PLL0 with P = 1 on output bank4 resulting in 350MHz.
Solving for 168.75MHz with PLL1 and fractional divide enabled:
168.75MHz = 20MHz * (M / D)
P * 2
168.75MHz * 2 = M = 16.875 or 33.75
20MHz
P
1
2
The 33.75 value is chosen to achieve the highest VCO frequency possible. Next step is to figure out the setting for the fractional divide using Eq.3.
33.75 = 2*N + A + 1 + SS_OFFSET * 1/64
Integer value 33 can be determined by N and A, thus leaving 0.75 left to be solved.
2*N + A + 1 = 33
SS_OFFSET = 64 * 0.75 = 48
Therefore, we have D=1, M=33.75 (N=15, A=2, SS_OFFSET=48) for PLL1 with P=2 on an output bank resulting in 168.75MHz.
Thefractionaldividercanbedeterminedifitisneededbyfollowingthestepsinthepreviousexample. Notethatthe5V9888shouldnotbeprogrammedwith
TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The A[3:0] must be used and set to be greater than '2' for
amoreaccuratefractionaldivide.
11
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
LOOPFILTER
TheloopfilterforeachPLLcanbeprogrammedtooptimizethejitterperformance. Thelow-passfrequencyresponseofthePLListhemechanismthatdictates
thejittertransfercharacteristics. Theloopbandwidthcanbeextractedfromthejittertransfer. Anarrowloopbandwidthisgoodforjitterattenuationwhileawide
loopbandwidthisbestforlowjittergeneration. ThespecificloopfiltercomponentsthatcanbeprogrammedaretheresistorviatheRZ[3:0]bits,polecapacitor
via the CZ[3:0] bits, zero capacitor via the CP[3:0] bits, and the charge pump current via the IP[2:0] bits.
Thefollowingequationsgovernhowtheloopfilterisset.
VDD
Ip
UP
To VCO
From PFD
DOWN
Rz
Ip
Cp
Cz
Charge Pump and Loop Filter Configuration
Resistor (Rz) = 0.3KΩ + RZ[3:0] * 1KΩ
(Eq. 15)
Zero capacitor (Cz) = 6pF + CZ[3:0] * 27.2pF (Eq. 16)
Pole capacitor (Cp) = 1.3pF + CP[3:0] * 0.75pF (Eq. 17)
Charge pump current (Ip) = 5 * 2IP[2:0] μA
(Eq. 18)
Parameter
Bits
4
Step
Min
0.3
6
Max
15.3
414
Units
K Ω
pF
RZ
CZ
C P
IP
1
4
27.2
0.75
2n
4
1.3
5
12.55
640
pF
3
μA
PLLloopfilterdesignisbeyondthescopeofthisdatasheet. Refertodesignproceduresfor3-ordercharge-pumpbasedPLLs. Forthesakeofsimplicity,
thefastestandeasiestwaytocalculatethePLLloopbandwidth(Fc)giventheprogrammableloopfilterparametersisasfollows.
PLL Loop Bandwidth:
Charge pump gain (Kφ) = Ip / 2π
(Eq. 19)
VCO gain (KVCO) = 950MHz/V * 2π (Eq. 20)
M=Totalmultipliervalue(SeethePRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERSsectionformoredetail)
ωc = Rz * Kφ * KVCO * Cz (Eq. 21)
M * (Cz + Cp)
Fc = ωc / 2π
(Eq. 22)
Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your
phasemarginthuscompromisingloopstability.
12
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Todetermineiftheloopisstable, thephasemargin(ωm)wouldneedtobecalculatedasfollows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = Cz + Cp
Rz * Cz * Cp
(Eq. 23)
(Eq. 24)
φm = (360 / 2π ) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
(Eq. 25)
Toensurestabilityintheloop,thephasemarginisrecommendedtobe>60°buttoohighwillresultinthelocktimebeingexcessivelylong. Certainloopfilter
parameterswouldneedtobecompromisedtonotonlymeetarequiredloopbandwidthbuttoalsomaintainloopstability.
Example
Fc=150KHzisthedesiredloopbandwidth. ThetotalMvalueis850. Theratioofωp/ωc shouldbeatleast4. Aruleofthumbthatwillhelptoaidtheway,
theωp/ωcratioshouldbeatleast4. GivenFcandM,anoptimalloopfiltersettingneedstobesolvedforthatwillmeetboththePLLloopbandwidthandmaintain
loopstability.
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.
Ip = 40uA .
Kφ * KVCO = 950MHz/V * 40uA = 38000A/Vs
LoopBandwidths
ωc = 2π * Fc = 9.42x105 s-1
ωuz = ωp / ωc = 4
ωc2 = ωp * ωz
(Eq. 26)
(Eq. 27)
ωp = Cz + Cp = ωz (1 + Cz / Cp)
Rz * Cz * Cp
Solving for Cz, Cp, and Rz
Knowing ωc = Rz * Kφ * KVCO * Cz and substituting in the equations from above,
M * (Cz + Cp)
Cz >>> Cp, therefore, we can easily derive Cp to be
Cp = Kφ * KVCO
= 12.60pF
M * ωc2 * ωuz
Similarly for Cz and Rz
Cz = Kφ * KVCO * (ωuz2 - 1) = Cp * (ωuz2 - 1) = 189pF
M * ωc2 * ωuz
Rz =
M * ωc * ωuz2
= 22.48KΩ
Kφ * KVCO * (ωuz2 - 1)
Basedontheloopfilterparameterequationsfromabove,sincetherearenopossiblevaluesof12.60pFforCp,189pFforCz,and22.48KΩforRz,thenext
possiblevalueswithintheloopfiltersettingsare12.55pF(CP[3:0]=1111),196.4pF(CZ[3:0]=0111),and15.3KΩ(RZ[3:0]=1111),respectively. Thisloopfilter
settingwillyieldaloopbandwidthofabout102KHz. Thephasemarginmustbecheckedforloopstability.
φm = (360 / 2π ) * [tan-1 (6.41x105 s-1 / 3.33x105 s-1) - tan-1 (6.41x105 s-1 / 5.54x106 s-1)] = 56°
Althoughslightlybelow60°, thephasemarginwouldbeacceptablewithafairlystableloop.
13
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
CONFIGURINGTHEMULTI-PURPOSEI/Os
The 5V9888 can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I2C/JTAG pin. The general purpose I/O pins
(GIN0, GIN1, GIN2, GIN3, GIN4) have different uses depending on the mode of operation. The four available modes of operation are:
1)
2)
3)
4)
Manual Frequency Control (MFC) Mode for PLL0 Only
Manual Frequency Control (MFC) Mode for all three PLLs
I2CProgrammingMode
JTAGProgrammingMode
AlongwiththeGINxpinsarealsoGOUTxoutputpinsthatcantakeupadifferentfunctiondependingonthemodeofoperation. Seetablebelowfordescription.
Multi-Purpose Pins
GIN0
Other Signal Functions
SDAT / TDI
Signal Description
I2C serial data input / JTAG serial data input
I2C clock input / JTAG clock input
GIN1
SCLK / TCK
TMS
GIN2
JTAGcontrolsignaltotheTAPcontrollerstatemachine
JTAG active LOW input to asynchronously reset the BST
Reference clock select between XTALIN/REFIN and CLKIN
JTAG serial data output / Detects loss of PLL lock(1)
Detectslossoftheselectedclocksource(1)
GIN3
TRST
CLK_SEL
GIN4
GOUT0
GOUT1
TDO / LOSS_LOCK
LOSS_CLKIN
NOTE:
1. LOSS_LOCK and LOSS_CLKIN cannot be used as reliable inputs to other devices.
EachPLL'sprogrammingregisterscanstoreuptofourdifferentDxandMxconfigurationsincombinationwithtwodifferent PconfigurationsinMFCmodes.
The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's
loopfiltersettingsalsohasfourdifferentconfigurationstostoreandselectfrom. ThiswillbeexplainedintheMODE1andMODE2sections. TheuseoftheGINx
pinsinMFCmodecontroltheselectionoftheseconfigurations.
MODE1 - Manual Frequency Control (MFC) Mode for PLL0 Only
Inthismode,onlytheconfigurationofPLL0canbechangedduringoperation.. PLL1andPLL2haveonlyonefixedconfigurationinthismode. TheGIN0,
GIN1andGIN2pinscontroltheselectionofuptoeightdifferentD0, M0, P, RZ0, CZ0, PZ0, andIP0storedconfigurations. GIN3isnotavailabletousersand
GIN4 becomes CLK_SEL pin. The output GOUT0 will become an indicator for loss of PLL lock (LOSS_LOCK).
GOUT1pinwillbecomeanindicatorforlossoftheselectedclock(LOSS_CLKIN).
PLL0itselfonlyhasfourdifferentconfigurationstochoosefrombutinthismode,itborrowstwoconfigurations(Config2andConfig3)frombothPLL1andPLL2,
toprovideeightdifferentstoredconfigurations. PLL1andPLL2willstillbefullyoperationalbutthedefaultconfigurationwillbeConfig0. Theoutputbankswill
eachhavetwoPconfigurationsthatcanbeassociatedwitheachofthePLLconfigurations. EachofthetwoPconfigurationshasitsownsetofPMbits(Seethe
PRE-SCALERS,FEEDBACK-DIVIDERS,POST-DIVIDERSsectionformoredetailonthePMbits). UsetheODIVbittochoosewhichpost-dividerconfiguration
toassociatewithaspecificPLLconfiguration. Forexample,ifODIV0_CONFIG0=1,thenwhenConfig0isselectedQx[9:0]_CONFIG1isselectedasthepost-
dividervaluetobeused. OrifODIV2_CONFIG3=0,thenwhenCONFIG7isselected,Qx[9:0]_CONFIG0isselected. NotethatthereisanODIVxbitforeach
ofthePLLconfigurations. Inthisway, thepost-dividervaluescanchangewiththeconfiguration.
Toenterthismode, usersmustsetMFCbitto"1", andI2C/JTAGpinmustbeleftfloating.
GIN2 Pin
GIN1 Pin
GIN0 Pin
PLL0 Configuration Selection (Mode 1)
0
0
0
Configuration 0: D0_CONFIG0, M0_CONFIG0, and ODIV0_CONFIG0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Configuration 1: D0_CONFIG1, M0_CONFIG1, and ODIV0_CONFIG1
Configuration 2: D0_CONFIG2, M0_CONFIG2, and ODIV0_CONFIG2
Configuration 3: D0_CONFIG3, M0_CONFIG3, and ODIV0_CONFIG3
Configuration 4: D1_CONFIG2, M1_CONFIG2, and ODIV1_CONFIG2
Configuration 5: D1_CONFIG3, M1_CONFIG3, and ODIV1_CONFIG3
Configuration 6: D2_CONFIG2, M2_CONFIG2, and ODIV2_CONFIG2
Configuration 7: D2_CONFIG3, M2_CONFIG3, and ODIV2_CONFIG3
14
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
MODE2 - Manual Frequency Control (MFC) Mode for all PLLs
Inthismode,theconfigurationofPLL0,PLL1,andPLL2canbechangedduringoperation. TheGINxpinsareusedtocontroltheselectionofuptofourdifferent
Dx,Mx,P,RZx,CZx,CPx,andIPxconfigurationsforeachPLL.GIN0andGIN1becomeconfigurationselectionpinsforD0andM0ofPLL0,GIN2andGIN3
becomeconfigurationselectionpinsforD1andM1ofPLL1,andGIN3andGIN4becomeconfigurationselectionpinsforD2andM2ofPLL2. TheoutputGOUT0
willbecomeanindicatorforlossofPLLlock(LOSS_LOCK). GOUT1pinwillbecomeanindicatorforlossoftheselectedclock(LOSS_CLKIN).
TheoutputbankswillhavetwodifferentPconfigurationstochoosefromforeachofthefourPLLconfigurations. EachofthetwoPconfigurationshasitsown
setofPMbits(SeethePRE-SCALERS,FEEDBACK-DIVIDERS,POST-DIVIDERSsectionformoredetailonthePMbits). UsetheODIVbittochoosewhich
post-dividerconfigurationtoassociatewithaspecificPLLconfiguration. Forexample,ifODIV2_CONFIG2=1,thenwhenConfig2isselectedQx[9:0]_CONFIG1
isselectedasthepost-dividervaluetobeused. NotethatthereisanODIVxbitforeachofthePLLconfigurations. Inthisway,thepost-dividervaluescanchange
withtheconfiguration.
Toenterthismode, usersmustsetMFCbitto"0", andI2C/JTAGpinmustbeleftfloating.
GIN4 Pin GIN3 Pin
PLL2 Configuration Selection (Mode 2)
Configuration0
GIN1 Pin GIN0 Pin
PLL0 Configuration Selection (Mode 2)
Configuration0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Configuration1
Configuration1
Configuration2
Configuration2
Configuration3
Configuration3
GIN2 Pin
PLL1 Configuration Selection (Mode 2)
Configuration0
0
1
Configuration1
MODE3 - I2C Programming Mode
Inthismode, GIN0, GIN1, andGIN4becomeSDAT(I2Cdata), SCLK(I2Cclock),andCLK_SELsignalpins,respectively.TheoutputGOUT0willbecome
an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the selected clock (LOSS_CLKIN). GIN2 and GIN3 are not
availabletousers.
To enter this mode, I2C/JTAG pin must be set HIGH.
MODE4 - JTAG Programming Mode
Inthismode,GIN0,GIN1,GIN2,GIN3,andGIN4willbecomeTDI(JTAGdatain),TCK(JTAGclock),TMS(JTAGcontrolsignal),TRST(JTAGreset)and
CLK_SELsignalpins,respectively.TheoutputGOUT0willbecomeJTAGTDOsignal,andGOUT1willbeanindicatorforlossoftheselectedclock(LOSS_CLKIN).
Toenterthismode, I2C/JTAGpinmustbesetLOW.
Manual Frequency Control modes
Multi-Purpose pins
GIN0
Mode1
GIN0
Mode2
GIN0
JTAG
TDI
I2C
SDAT
GIN1
GIN1
GIN1
TCK
SCLK
GIN2
GIN2
GIN2
TMS
n/a
GIN3
n/a
GIN3
GIN4(1)
TRST
CLK_SEL
n/a
GIN4
CLK_SEL
LOSS_LOCK
LOSS_CLKIN
CLK_SEL
LOSS_LOCK
LOSS_CLKIN
GOUT0
GOUT1
LOSS_LOCK
LOSS_CLKIN
TDO
LOSS_CLKIN
NOTE:
1. The PLL(s) will lock onto the primary clock and the manual switchover can be controlled by the PRIMCLK bit.
15
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
Understanding the GIN Signals
Duringpowerup,thepartwillvirtuallybeinMFCmode2,therefore,thevaluesofGIN3,GIN2,GIN1andGIN0willbelatchedandusedforPLLconfiguration
selection,regardlessofthestateoftheI2C/JTAG pin. GIN4isnotlatched,andwillassumetheLOWstateinternallywheninprogrammingmode. Thismeans
thatwheninprogrammingmode,thePLLconfigurationcanonlybechangedbywritingdirectlytotheregistersofthecurrentlyselectedconfiguration.When
inMFCmode2, configuration0or1(GIN4=0)shouldbeselectedifyoudonotwanttochangeconfigurationswhenenteringorleavingprogrammingmode.
The GIN pins should be held LOW during power up to select configuration0 as default.
When not in programming mode, the GIN inputs directly control the selected configuration. The internal GINx signals can be individually disabled via
programmingtheGINENbits(0x06). WhendisabledbysettingGINENxto"0",theGINxinputsmaybeleftfloating,butduringpowerup,theGINpinswillstill
latch. DisabledinputsareinterpretedasLOWbytheinternalstatemachines. Evenifdisabled, GIN2, GIN1, GIN0andGIN3pins willbeenabledifrequired
forI2CorJTAGprogrammingfunctionswheninprogrammingmode. TheCLK_SELfunctionontheGIN4pinwillberenderedcompletelynon-functionalwhen
disabled.
SHUTDOWN/ENABLEOFOUTPUTS
TheSHUTDOWN/OEpin,alongwithinternalbits,controlstheenabling/disablingoftheoutputbanks. TheSHUTDOWN/OEpincanbeprogrammedtofunction
asanoutputenableorglobalshutdown. ThepolarityoftheSHUTDOWN/OEsignalpincanbeprogrammedtobeeitheractiveHIGHorLOWwiththeSPbit
(0x1C). When SP is "0", the pin becomes active HIGH and when SP is "1", the pin becomes active LOW. The SH bit(0x1C) determines the function of the
SHUTDOWN/OEsignalpin. IfSHis"1", thesignalpinisSHUTDOWNand functionsasaglobalshutdown. ThiswilloverridetheOEx(0x1C), OSx(0x1D),
and PLLSx (0x1E) bits. If SH is "0", the signal pin is OE and functions as an enable/disable of the output banks. If used as an output enable/disable, each
outputbankcanbeindividuallyprogrammedtobeenabledordisabledbytheOEpin.bysettingOExbitsto"1". IftheOEsignalpinisasserted,theoutputbanks
thathastheircorrespondingOExbitsetto"1"willbedisabled.TheOEMxbitsdeterminetheoutputs'disablestate. Whensetto"0x"theoutputswillbetristated.
Whensetto"10", theoutputswillbepulledlow. Whensetto"11", theoutputswillbepulledhigh. Invertedoutputswillbe parkedintheoppositestate. Ifthe
OExbitsaresetto"0",thestatesofthecorrespondingoutputbankswillnotbeimpactedbythestateoftheOEpin. Toindividuallyenable/disableviaprogramming
insteadoftheOEpin,hardwiretheOEpintoVddorGND(dependingifitisactiveHIGHorLOW)asiftodisabletheoutputs. ThentoggletheOExbitstoeither
"0" to enable or "1" to disable.
When the chip is in shutdown, the outputs, the reference oscillator, and the I2C /JTAG pin are powered down. The outputs will be tristated and the I2C
/JTAGpinwillbesettoMFCmode(MIDlevel). Programmingwillnotbeallowed. TheGINxpinsandclockinputsremainoperational. ThePLLisnotdisabled.
The SHUTDOWN pin must be reasserted in order to program the part or to resume operation.
16
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
MANUALFREQUENCYCONTROL(MFC)BLOCKDIAGRAM
OUTPUT MUX
PLL0
Prescaler "D"
CONFIG0
VCO
CONFIG1
CONFIG2
CONFIG3
Output Divider P2
CONFIG0
CONFIG1
Multiplier "M"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
ODIV
Output Divider P3
CONFIG0
CONFIG1
PLL1
ODIV
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
VCO
Multiplier "M"
CONFIG0
ODIV
ODIV
CONFIG1
PLL2
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
VCO
Multiplier "M"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
MFC = 0
NOTES:
This illustration shows how the configurations are arranged for each PLL. There is an ODIV bit associated with each of the four configurations.
-
-
-
-
GIN0 and GIN1 control four configurations from PLL0.
GIN2 controls four configurations from PLL1.
GIN3 and GIN4 control four configurations from PLL2.
ODIV from each configuration determines the selection of two Output Divider Px Configurations.
17
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
MANUALFREQUENCYCONTROL(MFC)BLOCKDIAGRAM
OUTPUT MUX
PLL0
Prescaler "D"
CONFIG0
VCO
CONFIG1
CONFIG2
CONFIG3
Output Divider P2
CONFIG0
CONFIG1
Multiplier "M"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
ODIV
Output Divider P3
CONFIG0
CONFIG1
PLL1
ODIV
Prescaler "D"
CONFIG0
VCO
CONFIG4
CONFIG5
Multiplier "M"
CONFIG0
ODIV
CONFIG4
CONFIG5
ODIV
ODIV
PLL2
Prescaler "D"
CONFIG0
VCO
CONFIG6
CONFIG7
Multiplier "M"
CONFIG0
ODIV
CONFIG6
CONFIG7
ODIV
ODIV
MFC = 1
NOTES:
This illustration shows how the configurations are arranged for PLL0. Config_4 and Config_5 are taken from PLL1, and Config_6 and Config_7 are taken from PLL2. There is an
ODIV bit associated with each of the four configurations.
-
-
GIN0, GIN1, and GIN2 control eight shaded configurations for PLL0.
ODIV from each configuration determines the selection of two Output Divider Px Configurations.
18
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
BLOCKDIAGRAMFORSHUTDOWN/OECONTROLSIGNAL
OUT1
OUT2
PM2
OE1
01
10
11
/2
/2
Q2
+ 2
OE2
01
10
11
/2
/2
OUT3
OUT4
Q3
+ 2
OE3
PM3
MUX
01
10
11
/2
/2
Q4
+ 2
OUT4
OUT5
PM4
OE4
PM5
01
10
11
/2
/2
Q5
+ 2
OUT5
PM6
OE5
01
10
11
/2
OUT6
/2
Q6
+ 2
OE6
OE MODE
SHUTDOWN/OE
Global SHUTDOWN Mode:
Assert to Shutdown power on the outputs
and 3-Level Pin
SP
SH
NOTE:
This illustration shows the internal logic behind the SHUTDOWN/OE pin and the bits associated with it.
19
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
POWER UP AND POWER SAVING FEATURES
Ifaglobalshutdownisenabled,SHUTDOWNpinasserted,mostofthechipexceptforthePLLswillbepowereddown. Notethattheregisterbitswillnotlose
theirstateintheeventofachippower-down. Theonlypossibilitythattheregisterbitswilllosetheirstateisifthepartwaspower-cycled. Aftercomingoutof shutdown
mode,thePLLswillrequiretimetorelock.
Duringpowerup,thevaluesofGIN3,GIN2,GIN1andGIN0willbelatchedandusedforPLLconfigurationselection,regardlessofthestateoftheI2C/JTAG
pinandGINxbeingdisabledviatheGINENxbits. GIN4willhaveaninternalstateofLOW. TheGINpinsshouldbeheldLOWduringpoweruptoselectconfiguration0
as default. The output levels will be at an undefined state during power up.
Thepost-dividershouldneverbedisabledviaPMbitsafter powerup, orelseitwillrendertheoutputbankcompletelynon-functionalduringnormaloperation,
(unlesstheoutputbankitselfwillnotbeusedatall).
Duringpowerup, theVDD rampmustbemonotonic.
LOSS OF LOCK AND INPUT CLOCK
Thedeviceemploysalossoflockandlossofinputclockdetectioncircuitry. TheGIN0/LOSS_LOCKandGIN1/LOSS_CLKINaretheoutputsthatindicate
such failures. LOSS_LOCK signal will be asserted if any of the three powered up PLLs loses frequency lock for any event other than PLL shutdown. Lock
isdeterminedbycheckingthatthereferenceandfeedbackclocksarewithin1/2periodofeachother. LOSS_LOCKisalsoassertedforatleasttwoclockcycles
ofthenewlyselectedclockwhenswitchingovertoadifferentclocksource(manualorautomatic).
LOSS_CLKINisassertedwhenthecurrentlyselectedclockislostorisassertedwhenbothclocksarelost. Intheeventoftheselectedclockbeingabsent
uponpowerup,thelossoftheselectedclockdetectioncircuitrywillreferenceaninternaloscillator. LOSS_LOCKandLOSS_CLKINcannotbeusedasreliable
inputstootherdevices.
SWITCHOVERMODES
TheIDT5V9888featuresredundantclockinputswhichsupportsbothAutomaticandManualswitchovermode. Thesetwomodesaredeterminedbythe
configurationbits,SM(0x34). Theprimaryclocksourcecanbeprogrammed,viathePRIMCLKbit,tobeeitherXTALIN/REFINorCLKIN,whichisdetermined
bythePRIMCLKbit.Theotherclocksourceinputwillbeconsideredasthesecondarysource. Thisismoredetailedinthe'REFERENCECLOCKINPUTPINS
ANDSELECTION'. Notethattheswitchovermodesareasynchronous. IfthereferenceclocksaredirectlyroutedtoOUTxwithnophaserelationship, short
pulses can be generated during switchover. The automatic switchover mode will work only when the primary clock source is XTALIN/REFIN.
MANUAL SWITCHOVER MODE
WhenSM[1:0]is"0x",theredundantinputsareinmanualswitchovermode. Inthismode, CLK_SELpinisusedtoswitchbetweentheprimaryandsecondary
clocksources.Aspreviouslymentioned,theprimaryandsecondaryclocksourcesettingisdeterminedbythePRIMCLKbit.Duringtheswitchover,noglitches
willoccurattheoutputofthedevice,althoughtheremaybefrequencyandphasedrift,dependingontheexactphaseandfrequencyrelationshipbetweenthe
primaryandsecondaryclocks.TheLOSS_LOCKsignalwillbeassertedforaminimumoftwoinputclockcyclesofthenewlyselectedclock,evenifthetwoinputs
areexactlyinphase. GOUT1isusedasLOSS_CLKIN, whichindicatesthelossofthecurrentlyusedselectedclock.
AUTOMATICSWITCHOVERMODE
When SM[1:0] is "1x", the redundant inputs are in automatic switchover mode. Automatic switchover mode supports both revertive and non-revertive
functionalities. These two functions are determined by the SM bits being set to "10" for non-revertive and "11" for revertive.
Non-Revertive
Theinputclockselectionwillswitchtothesecondaryclocksourcewhentherearenotransitionsontheprimaryclocksourcefortwosecondaryclockcycles.
LOSS_LOCKandLOSS_CLKINsignalswillbeassertedforaminimumoftwosecondaryclockcycles.LOSS_LOCKwillremainasserteduntilthePLLachieves
lock,aspreviouslydefined,tothenewinputclock. Iftherearenotransitionsonbothclocksources,theLOSS_LOCKsignalandLOSS_CLKINsignalwillbe
asserted. Inthismode,oncethesecondaryclockisselected,itwillnotautomaticallyre-selecttheprimaryclockastheinputclock,evenifthesecondaryclock
goes away and the primary clock is functional. The CLK_SEL pin must be toggled to re-select the primary clock source as the input clock.
20
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Revertive
Theinputclockselectionwillswitchtothesecondaryclocksourcewhentherearenotransitionsontheprimaryclocksourcefortwosecondaryclockcycles.
LOSS_LOCKandLOSS_CLKINsignalswillbeasserted. LOSS_LOCKwillremainasserteduntilthePLLachieveslock,aspreviouslydefined,tothenewinput
clock. Iftherearenotransitionsonbothclocksources,theLOSS_LOCKsignalandLOSS_CLKINsignalwillbeasserted. Afterastableandvalidprimaryclock
sourceispresentforeither8or1024primaryclockcycles,theinputclockselectionwillautomaticallyswitchbacktotheprimaryclocksourceandLOSS_CLKIN
signalwillbedeasserted.TheCLK_SELpincanbeleftfloatinginthisauto-revertivemode. TheOKCbit(0x1D)determinesthenumberofvalidprimaryclock
cycles of either 8 or 1024 before switching back to the primary clock source. If OKC is set to "0", the primary clock will be re-selected as the input clock if the
primaryclockispresentfor8primaryclockcycles. IfOKCissetto"1",there-selectthresholdis1024primaryclockcycles. (Actualswitchovertimeswillvary.)
Notethatbothclockinputsmustbeatthesamefrequencyinorderfortheauto-revertiveswitchovertofunctionproperly. Ifbothreferenceclocksareatdifferent
frequencies, thedevicewillalwaysremainontheprimaryclockunlessitisabsentfortwosecondaryclockcycles.
Inallswitchovermodes,LOSS_LOCKsignalisassertedforatleasttwoinputclockcyclesofthenewlyselectedclockwhenswitchingclocksources(manually
orautomatic).
CLOCK SWITCH MATRIX AND OUTPUTS
AllthreePLLoutputsandthecurrentlyselectedinputclocksourceareroutedintoandthroughaclockmatrix.TheuserisabletoselectwhichPLLoutputand
clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for more
information. NotethatOUT1willbebasedoffthereferenceclockandtheonlyoutputbanktogglingunderthedefaultRAMbitsettings.
Outputs 1, 2 and 3 are 3.3V LVTTL. Outputs banks 4 and 5 can be 3.3V LVTTL, LVPECL or LVDS. The LVDS and LVPECL selection is determined by
theLVLxbits(0x54,0x58). Eachoutputbankhasindividualslew-ratecontrol(SLEWxbits). Eachoutputcanbeindividuallyinverted(INVxbits);whenusing
LVPECLorLVDSmodes,oneoftheoutputsineachLVPECL/LVDSpairshouldbeinverted. AlloutputbanksexceptOUT1haveaprogrammable10-bitpost-
divider(Qxbits)withtwoselectabledivideconfigurationsviatheODIVxbits.
Therearefoursettingsfortheprogrammableslewrate,0.7V/ns,1.25V/ns,2V/ns,and2.75V/ns;thisonlyappliestothe3.3VLVTTLoutputs. Thedifferential
outputsarenotslewrateprogrammable inLVPECLorLVDSmodes. SLEW4and/orSLEW5mustbesetto2.75V/nsforstableoutputoperation. ForLVTTL
outputfrequencyrateshigherthan100MHz, aslewrateof2V/nsorgreatershouldbeselected. Thepost-dividerscanbedisabledusingthePMxbit, which
isdescribedinthePRE-SCALER,FEEDBACK-DIVIDER,ANDPOST-DIVIDERsection. Eachoutputcanalsobeenabled/disabled,whichisdescribedinthe
'SHUTDOWN/ENABLEof OUTPUTS'section. RefertotheRAMtableforallbinarysettings.
HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME
I/Os
I/Os
Non-Volatile
Configuration
PLLs and Control
Blocks
EEPROM
Cell
Volatile
Configuration
I 2C or JTAG
interface
Write Enable
Programming
Interface Block
NOTE: Diagram does not represent actual number of die on chip.
21
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
PROGRAMMINGTHEDEVICE
I2C and JTAG may be used to program the 5V9888. The I2C/JTAG pin selects the I2C when HIGH and JTAG when LOW. Note that the TRST pin needs
to be LOW for I2C mode.
Hardwired Parameters for the IDT5V9888
JTAGidentificationnumber=32'b0000_0000001110101100_00000110011_1
Device (slave) address = 7'b1101010
ID Byte for the 5V9888 = 8'b00010000
I2C PROGRAMMING
The 5v9888 is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first
byteofdataafterawriteframetothecorrectslaveaddressisinterpretedastheregisteraddress;thisaddressauto-incrementsaftereachbytewrittenorread.
Theframeformatsareshownbelow.
SDA
SCL
SDA
SCL
P
S
Data Frame
Data is stable during
clock HIGH
Stop
Condition
Start
Condition
Figure 1: Framing
Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.
MSB
1
LSB
1
0
1
0
1
0
R/W
7-bit slave address
R/W
ACK from Slave
0 - Slave will be written by master
1 - Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a "1" bit.
Figure 2: First Byte Transmittetd on I2C Bus
22
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
EXTERNAL I2C INTERFACE CONDITION
KEY:
From Master to Slave
FromMastertoSlave, butcanbeomittediffollowedbythecorrectsequence
NormallydatatransferisterminatedbyaSTOPconditiongeneratedbytheMaster. However,iftheMasterstillwishestocommunicateonthebus,itcan
generatearepeatedSTARTcondition, andaddressanotherSlaveaddresswithoutfirstgeneratingaSTOPcondition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDA LOW)
NACK - Not Acknowledge (SDA HIGH)
Sr-RepeatedStartCondition
S - START Condition
P - STOP Condition
PROGWRITE
S
Address R/W ACK Command Code ACK Register ACK Data ACK
7-bits 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit
P
0
Figure 3: Progwrite Command Frame
WritescancontinueaslongasaStopconditionisnotsentandeachbytewillincrementtheregisteraddress.
PROGREAD
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address
priortoareadoperationbyissuingthefollowingcommand:
S
Address R/W ACK Command Code ACK Register ACK
7-bits 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit
P
0
Figure 4a: Prior to Progread Command Set Register Address
TheusercanignoretheSTOPconditionaboveandusearepeatedSTARTconditioninstead,straightaftertheslaveacknowledgementbit(i.e.,followedby
theProgreadcommand):
Data_1
8-bits
Data_2
8-bits
Data_last
8-bits
P
Sr Address R/W ACK ID Byte ACK
7-bits 1-bit 8 bits
ACK
1-bit
ACK
1-bit
NACK
1-bit
1
1-bit
Figure 4b: Progread Command Frame
Note:Figure4babovebyitselfistheProgreadcommandformat. TheIDbyteforthe5V9888is10hex. Eachbyterecievedincrementstheregisteraddress.
23
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
PROGSAVE
JTAGINSTRUCTIONREGISTER
DESCRIPTION
To save configuration into EEPROM, WRITE ENABLE pin must be set LOW
P
S
Address R/W ACK Command Code ACK
7-bits 1-bit 8-bits:xxxxxx01 1-bit
IR (3)
IR (2)
IR (1)
IR (0)
Instructions
EXTEST(1)
SAMPLE/PRELOAD(1)
IDCODE(1)
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
NOTE:
PROGWRITE is for writing to the 5V9888 registers.
PROGREAD is for reading the 5V9888 registers.
PROGSAVE is for saving all the contents of the 5V9888 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V9888 registers.
REGADDR(2)
REGDATAW / PROGWRITE(3)
REGDATAR / PROGREAD(4)
PROGSAVE(5)
PROGRESTORE(6)
CLAMP(1)
HIGHZ(1,7)
BYPASS(1)
PROGRESTORE
P
S
Address R/W ACK Command Code ACK
7-bits 1-bit 8-bits:xxxxxx10 1-bit
NOTES:
1. IEEE 1149.1 definition
0
2. REGADDR is for setting a specific 5V9888 register address.
3. REGDATAW/PROGWRITE is for writing to the 5V9888 registers.
4. REGDATAR/PROGREAD is for reading the 5V9888 registers.
5. PROGSAVE is for saving all the contents of the 5V9888 registers to the EEPROM.
WRITE ENABLE pin must be asserted LOW.
6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9888 registers.
7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction
JTAGINTERFACE
InadditiontotheIEEE1149.1instructionsEXTEST,SAMPLE/PRELOAD,
CLAMP, HIGH-Z and BYPASS, the 5V9888 allows access to internal
programmingregistersusingtheREGADDR(setregisteraddress),REGDATAR
(read register) and REGDATW (write register instructions. Data is always
accessedbybyte,andtheregisteraddressincrementsaftereachreadorwrite.
Thefullinstructionsetfollows. TheIDT5V9888willbeupdatingtheregisters
duringprogramming.
The JTAG TAP controller can be reset in one of four ways:
1) Power up in JTAG mode
2) PowerupinI2CmodeandthengointoJTAGmode,orgooutofandback
intoJTAGmodewiththeI2C/JTAGpin
3) Apply TRST while in JTAG mode
4) Apply five rising edges of TCK with TMS high while in JTAG mode
EEPROMINTERFACE
TheIDT5V9888canalsostoreitsconfigurationinaninternalEEPROM. Thecontentsofthedevice'sinternalprogrammingregisterscanbesavedtothe
EEPROMbyissuingasaveinstruction(ProgSave)andassertingtheWRITEENABLEpinLOW. Theycanbeloadedbacktotheinternalprogrammingregisters
byissuingarestoreinstruction(ProgRestore).
ToinitiateasaveorrestoreusingI2C,onlytwobytesaretransferred.TheDeviceAddressisissuedwiththeread/writebitsetto"0",followedbytheappropriate
commandcode.ThesaveorrestoreinstructionexecutesaftertheSTOPconditionisissuedbytheMaster,duringwhichtimetheIDT5V9888willnotgenerate
Acknowledgebits. The5V9888willacknowledgetheinstructionsafterithascompletedexecutionofthem. Duringthattime,theI2Cbusshouldbeinterpreted
as busy by all other users of the bus.
UsingJTAG,theProgSaveandProgRestoreinstructionsselectstheBYPASSregisterpathforshiftingthedatafromTDItoTDOduringthedataregisterscanning.
DuringtheexecutionofaProgSaveorProgRestoreinstruction,theIDT5V9888willnotacceptanewprogramminginstruction(read,write,save,orrestore).
Allnon-programmingJTAGinstructionswillfunctionproperly,buttheusershouldwaituntilthesaveorrestoreiscompletebeforeissuinganewprogramming
instruction. Ifanewprogramminginstructionisissuedbeforethesaveorrestorecompletes,thenewinstructionisignored,andtheBYPASSregisterpathremains
ineffectforshiftingdatafromTDItoTDOduringdataregisterscanning.
Thetimeittakesforthesave(TSAVE)andrestore(TRESTORE)instructionstocompleteis:
TSAVE = 100ms max, TRESTORE = 10 ms max
WRITEENABLEshouldstaylowforatleast10msafterthecompletionofasaveinstruction.
24
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Inorderforthesaveandrestoreinstructionstofunctionproperly,theIDT5V9888mustnotbeinshutdownmode(SHUTDOWNpinasserted). Intheevent
ofaninterruptofsomesortsuchasapowerdownofthepartinthemiddleofasaveorrestoreoperation,thecontentstoorfromtheEEPROMwillbepartially
loaded, and a CRC error will be generated. The CERR bit (0x81) will be asserted to indicate that an error has occurred. The LOSS_LOCK signal will also
beasserted.
Onpower-upoftheIDT5V9888,anautomaticrestoreisperformedtoloadtheEEPROMcontentsintotheinternalprogrammingregisters. Theauto-restore
willnotfunctionproperlyifthedeviceisinshutdownmode(SHUTDOWNpinasserted). TheIDT5V9888willbereadytoacceptaprogramminginstructiononce
itacknowledgesits7-bitI2Caddress.
tTCLK
t4
t2
t1
TCLK
t3
TDI/TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
t5
Standard JTAG Timing
NOTE:
t1 = tTCLKLOW
t2 = tTCLKHIGH
t3 = tTCLKFALL
t4 = tTCLKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
JTAG
SYSTEMINTERFACEPARAMETERS
ACELECTRICALCHARACTERISTICS
Symbol
Parameter
DataOutput(1)
Min.
Max.
Units
tDO
—
20
ns
Symbol
Parameter
Min.
100
40
Max.
Units
tDOH
tDS
DataOutputHold(1)
DataInput, tRISE =3ns
DataInput, tFALL =3ns
0
—
ns
tTCLK
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
—
ns
10
—
ns
tTCLKHIGH
tTCLKLOW
tTCLKRISE
tTCLKFALL
tRST
—
ns
tDH
10
—
ns
40
—
ns
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAGReset
—
5(1)
5(1)
—
ns
NOTE:
1. 50pF loading on external output signals.
—
ns
50
ns
tRSR
JTAG Reset Recovery
50
—
ns
NOTE:
1. Guaranteed by design.
25
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
I2C BUS DC CHARACTERISTICS
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
Unit
V
Input HIGH Level
InputLOWLevel
Hysteresis of Inputs
InputLeakageCurrent
OutputLOWVoltage
0.7 * VDD
VIL
0.3 * VDD
V
VHYS
IIN
0.05 * VDD
V
±1.0
0.4
μA
V
VOL
IOL = 3 mA
I2C BUS AC CHARACTERISTICS FOR STANDARD MODE
Symbol
FSCLK
tBUF
Parameter
Min
0
Typ
Max
Unit
KHz
μs
μs
μs
ns
Serial Clock Frequency (SCLK)
Bus free time between STOP and START
SetupTime,START
100
4.7
4.7
4
tSU:START
tHD:START
tSU:DATA
tHD:DATA
tOVD
HoldTime, START
SetupTime,datainput(SDAT)
HoldTime, datainput(SDAT)(1)
Outputdatavalidfromclock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDAT, SCLK)
Fall Time, data and clock (SDAT, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
250
0
μs
μs
pF
3.45
400
CB
tR
1000
300
ns
tF
ns
tHIGH
4
4.7
4
μs
μs
μs
tLOW
tSU:STOP
SetupTime, STOP
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge
of SCLK.
I2C BUS AC CHARACTERISTICS FOR FAST MODE
Symbol
FSCLK
tBUF
Parameter
Min
0
Typ
Max
Unit
KHz
μs
μs
μs
ns
Serial Clock Frequency (SCLK)
Bus free time between STOP and START
SetupTime,START
400
1.3
0.6
0.6
100
0
tSU:START
tHD:START
tSU:DATA
tHD:DATA
tOVD
HoldTime, START
SetupTime,datainput(SDAT)
HoldTime, datainput(SDAT)(1)
Outputdatavalidfromclock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDAT, SCLK)
Fall Time, data and clock (SDAT, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
μs
μs
pF
0.9
400
300
300
CB
tR
20 + 0.1 * CB
ns
tF
20 + 0.1 * CB
ns
tHIGH
0.6
1.3
0.6
μs
μs
μs
tLOW
tSU:STOP
SetupTime, STOP
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge
of SCLK.
26
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDD
Description
Internal Power Supply Voltage
Input Voltage
Max
-0.5 to +4.6
-0.5 to +4.6
-0.5 to VDD + 0.5
150
Unit
V
VI
V
VO
Output Voltage(2)
V
TJ
Junction Temperature
Storage Temperature
°C
°C
TSTG
–65 to +150
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Not to exceed 4.6V.
(1)
CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
CIN
Input Capacitance
—
4
—
pF
Crystal Specifications
XTAL_FREQ
XTAL_MIN
XTAL_MAX
Crystal Frequency
8
—
3.5
50
—
—
—
—
MHz
pF
Minimum Crystal Load Capacitance
Maximum Crystal Load Capacitance
Crystal Load Capacitance Resolution
Voltage Swing (peak-to-peak, nominal)
—
—
—
—
35.4
0.125
2.3
pF
XTAL_VPP
V
NOTE:
1. Capacitance levels characterized but not tested.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Description
Min.
3
Typ.
Max.
Unit
VDD
PowerSupplyVoltageforLVTTL
Power Supply Voltage for LVDS/LVPECL
OperatingTemperature,Ambient
MaximumLoadCapacitance(LVTTLonly)
ExternalReferenceCrystal
3.3
3.3
—
—
—
—
—
3.6
3.465
+85
15
V
3.135
–40
—
TA
CLOAD_OUT
FIN
°C
pF
8
50
MHz
ExternalReferenceClock,Industrial
1
400
5
tPU
Power-uptimeforallVDDstoreachminimumspecifiedvoltage
(powerrampsmustbemonotonic)
0.05
ms
27
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
VIHH
Parameter
Test Conditions
I2C/JTAG 3-Level Input
Min.
Typ.
—
Max.
Unit
V
Input HIGH Voltage Level(1)
Input MID Voltage Level(1)
InputLOWVoltageLevel(1)
VDD – 0.4
—
VIMM
I2C/JTAG 3-Level Input
I2C/JTAG 3-Level Input
VIN = VDD
VDD/2 – 0.2
—
VDD/2 + 0.2
V
VILL
—
—
—
0.4
200
+50
—
V
HIGH Level
MID Level
LOW Level
—
I3
3-LevelInputDCCurrent
VIN = VDD/2
–50
–200
—
—
μA
mA
mA
VIN = GND
—
IDD
IDDS
TotalPowerSupplyCurrent
(3.3V Supply, VDD)
2 outputs @166MHz; 4 outputs @ 83MHz
2 outputs @20MHz; 4 outputs @ 40MHz
120
40
—
—
—
Total Power Supply Current in
ShutdownMode(2)
GlobalShutdownMode
—
2
—
(PLLs, dividers, outputs, etc. powereddown)
NOTES:
1. These inputs are normally wired to VDD, GND, or left floating. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and
the PLL may require additional tAQ time before all datasheet limits are achieved.
2. Dividers must reload reprogrammed values via power-on reset or terminal count reload in order to ensure low-power mode.
DCELECTRICALCHARACTERISTICSFOR3.3VLVTTL(1)
Symbol
IOH
Parameter
Output HIGH Current
OutputLOWCurrent
Input Voltage HIGH
InputVoltageLOW
Test Conditions
Min.
12
12
2
Typ.
24
Max.
—
Unit
mA
mA
V
VOH = VDD - 0.5, VDD = 3.3V ± 0.3V
VOL = 0.5V, VDD = 3.3V ± 0.3V
IOL
24
—
VIH
—
—
VIL
—
—
—
—
—
0.8
10
V
IIH
Input HIGH Current
InputLOWCurrent
VIN = VDD
VIN = 0V
—
μA
μA
μA
IIL
—
10
IOZD
OutputLeakageCurrent
3-stateoutputs
—
10
NOTE:
1. See RECOMMENDED OPERATING RANGE table.
POWERSUPPLYCHARACTERISTICSFORLVTTLOUTPUTS
Symbol
Parameter
Test Conditions
REF = LOW
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
6
12
mA
Outputsenabled,Alloutputsunloaded
VDD = Max., CL = 0pF
IDDD
Dynamic VDD Power Supply
CurrentperOutput
40
60
μA/MHz
FREFERENCE CLOCK = 33MHz, CL = 15pf
FREFERENCE CLOCK = 133MHz, CL = 15pf
FREFERENCE CLOCK = 200MHz, CL = 15pf
26
80
40
ITOT
Total Power VDD Supply Current
120
170
mA
112
28
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
DCELECTRICALCHARACTERISTICSFORLVDS
Symbol
VOT (+)
VOT (-)
Δ VOT
VOS
Parameter
Min.
247
-247
—
Typ.
—
—
—
1.2
—
9
Max
454
-454
50
Unit
mV
mV
mV
V
DifferentialOutputVoltagefortheTRUEbinarystate
DifferentialOutputVoltagefortheFALSEbinarystate
ChangeinVOT betweenComplimentaryOutputStates
OutputCommonModeVoltage(OffsetVoltage)
ChangeinVOS betweenComplimentaryOutputStates
Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD
DifferentialOutputsShortCircuitCurrent,VOUT+=VOUT-
1.125
—
1.375
50
Δ VOS
IOS
mV
mA
mA
—
24
IOSD
—
6
12
POWERSUPPLYCHARACTERISTICSFORLVDSOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
REF = LOW
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
68
90
mA
Outputsenabled,Alloutputsunloaded
VDD = Max., CL = 0pF
IDDD
Dynamic VDD Power Supply
CurrentperOutput
30
45
μA/MHz
FREFERENCE CLOCK = 100MHz, CL = 5pf
FREFERENCE CLOCK = 200MHz, CL = 5pf
FREFERENCE CLOCK = 400MHz, CL = 5pf
86
130
150
190
ITOT
Total Power VDD Supply Current
100
122
mA
NOTES:
1. Output banks 4 and 5 are toggling. Other output banks are powered down.
2. The termination resistors are excluded from these measurements.
DCELECTRICALCHARACTERISTICSFORLVPECL
Symbol
VOH
Parameter
Min.
VDD - 1.2
VDD - 1.95
0.55
Typ.
—
Max
VDD - 0.9
VDD - 1.61
0.93
Unit
V
Output Voltage HIGH, terminated through 50Ωtied to VDD - 2V
OutputVoltageLOW,terminatedthrough50ΩtiedtoVDD -2V
Peak to Peak Output Voltage Swing
VOL
—
V
VSWING
—
V
POWERSUPPLYCHARACTERISTICSFORLVPECLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
REF = LOW
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
86
110
mA
Outputsenabled,Alloutputsunloaded
VDD = Max., CL = 0pF
IDDD
Dynamic VDD Power Supply
CurrentperOutput
35
50
μA/MHz
FREFERENCE CLOCK = 100MHz, CL = 5pf
FREFERENCE CLOCK = 200MHz, CL = 5pf
FREFERENCE CLOCK = 400MHz, CL = 5pf
120
130
140
180
190
210
ITOT
Total Power VDD Supply Current
mA
NOTES:
1. Output banks 4 and 5 are toggling. Other output banks are powered down.
2. The termination resistors are excluded from these measurements.
29
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
ACTIMINGELECTRICALCHARACTERISTICS
(SPREAD SPECTRUM GENERATION = OFF)
Symbol
fIN
Parameter
Test Conditions
Min.
1(1)
Typ.
—
Max
400
200
500
1200
400
40
Unit
MHz
MHz
InputFrequency
OutputFrequency
InputFrequencyLimit
1/t1
SingleEndedClockoutputlimit(LVTTL)
DifferentialClockoutputlimit(LVPECL/LVDS)
VCOoperatingFrequencyRange
0.0049
0.0049
10
0.4(1)
0.03
40
—
—
fVCO
fPFD
fBW
t2
VCO Frequency
PFD Frequency
LoopBandwidth
Input Duty Cycle
Output Duty Cycle
—
MHz
MHz
MHz
%
PFDoperatingFrequencyRange
—
Basedonloopfilterresistorandcapacitorvalues
Duty Cycle for Input
—
—
60
t3
Measured at VDD/2, FOUT ≤ 200MHz
Measured at VDD/2, FOUT > 200MHz
Single-EndedOutputclockriseandfalltime,
20% to 80% of VDD (Output Load = 15pf)
Single-EndedOutputclockriseandfalltime,
20% to 80% of VDD (Output Load = 15pf)
Single-EndedOutputclockriseandfalltime,
20% to 80% of VDD (Output Load = 15pf)
Single-EndedOutputclockriseandfalltime,
20% to 80% of VDD (Output Load = 15pf)
LVDS, 20% to 80%
45
—
55
%
40
—
60
Slew Rate
—
2.75
—
SLEWx(bits) = 00
Slew Rate
—
—
—
2
—
—
—
t4(2)
SLEWx(bits) = 01
Slew Rate
V/ns
1.25
0.75
SLEWx(bits) = 10
Slew Rate
SLEWx(bits) = 11
RiseTimes
—
—
—
—
—
850
850
500
500
—
—
—
t5
FallTimes
ps
RiseTimes
LVPECL, 20% to 80%
—
FallTimes
—
t6
t7
t8
Outputthree-stateTiming
Timeforoutputtoenterorleavethree-statemode
after SHUTDOWN/OE switches
Peak-to-peakperiodjitter,
150 +
1/FOUTX
150
—
ns
ps
ps
ClockJitter(3,7)
OutputSkew
fPFD > 20MHz
fPFD < 20MHz
—
—
—
—
200
—
CLKoutputsmeasuredatVDD/2
Skewbetweenoutputtooutput onthesamebank
(bank 4 and bank 5 only)(4, 5)
150
t9
LockTime
Locktime(8)
PLLLockTimefromPower-up(6)
—
—
10
10
20
—
20
100
—
ms
μs
ms
t10
t11
PLLLocktimefromshutdownmode
Hold Time after TSAVE for WRITE ENABLE signal
Write-ProtectTime
NOTES:
1. Practical lower input frequency is determined by loop filter settings.
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
3. Input frequency is the same as the output with all output banks running at the same frequency.
4. Skew measured between all in-phase outputs in the same bank.
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
7. Guaranteed by design but not production tested.
8. Actual PLL lock time depends on the loop configuration.
SPREADSPECTRUMGENERATIONSPECIFICATIONS
Symbol
fIN
Parameter
Description
Min.
1(1)
Typ.
Max
400
—
Unit
MHz
kHz
InputFrequency
Mod Freq
InputFrequencyLimit
—
33
fMOD
ModulationFrequency
—
fSPREAD
SpreadValue
AmountofSpreadValue(Programmable)-DownSpread
AmountofSpreadValue(Programmable)-CenterSpread
-0.5, -1, -2.5, -3.5, -4
-0.5 to +0.5
%fOUT
NOTE:
1. Practical lower input frequency is determined by loop filter settings.
30
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
TEST CIRCUITS AND CONDITIONS(1)
VDD
CLKOUT
CLOAD
0.1μF
OUTPUTS
GND
NOTE:
1. All VDD pins must be tied together.
Test Circuits for DC Outputs
OTHER TERMINATION SCHEME (BLOCK DIAGRAM)
CLOAD
CLKOUT
CLKOUT
CLKOUT
OUTPUTS
GND
OUTPUTS
GND
CLOAD
RLOAD
CLOAD
LVDS: - 100Ω between differential outputs with 5pF
LVTTL: -15pF for each output
VDD-2V
RLOAD
CLOAD
CLOAD
CLKOUT
OUTPUTS
GND
CLKOUT
RLOAD
VDD-2V
LVPECL: - 50Ω to VDD-2V for each output with 5pF
31
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
RAM(PROGRAMMINGREGISTER)TABLES
BIT #
(Default Settings)
BIT #
Default
ADDR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register
DESCRIPTION
Hex Value
0x00
0x01
0x02
0x03
0x04
No registers exist
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
MFC
Address 0x04, Bits[7:1] are reserved and should bet set to "0".
Address 0x05, Bits 7, 6, and 3 are reserved and should be set to "1'.
0x05
0x06
FF
GINEN4
GINEN3
GINEN2
GINEN1
GINEN0
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-default); When
"11", XTALCAP[7:0] value must also be set to "0".
XDRV[1:0]
0
0
1
1
0
0
0
0
30
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
XTALCAP[7:0]
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
IP0[2:0]_CONFIG0
IP0[2:0]_CONFIG1
IP0[2:0]_CONFIG2
IP0[2:0]_CONFIG3
RZ0[3:0]_CONFIG0
RZ0[3:0]_CONFIG1
RZ0[3:0]_CONFIG2
RZ0[3:0]_CONFIG3
CZ0[3:0]_CONFIG0
CZ0[3:0]_CONFIG1
CZ0[3:0]_CONFIG2
CZ0[3:0]_CONFIG3
ODIV0_CONFIG0
ODIV0_CONFIG1
ODIV0_CONFIG2
ODIV0_CONFIG3
PLL0 LOOP FILTER SETTING
Loop Filter Values for PLL0 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode
ODIV0_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated
with PLL0; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3KΩ + RZ0[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ0[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP0[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP0[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
CP0[3:0]_CONFIG0
CP0[3:0]_CONFIG1
CP0[3:0]_CONFIG2
CP0[3:0]_CONFIG3
D0[7:0]_CONFIG0
D0[7:0]_CONFIG1
D0[7:0]_CONFIG2
D0[7:0]_CONFIG3
N0[7:0]_CONFIG0
N0[7:0]_CONFIG1
N0[7:0]_CONFIG2
N0[7:0]_CONFIG3
PLL0 INPUT DIVIDER D0 SETTING
PLL0 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL0 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N0[11:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x60-0x67
A0[3:0]_CONFIG0
A0[3:0]_CONFIG1
A0[3:0]_CONFIG2
A0[3:0]_CONFIG3
N0[11:8]_CONFIG0
N0[11:8]_CONFIG1
N0[11:8]_CONFIG2
N0[11:8]_CONFIG3
Total Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
0x1C
0x1D
0x1E
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
40
00
SP
SH
OE6
OE5
OE4
OE3
OE2
OE1
SP=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);
OEx=Output Disable Function for OUTx, ("1"=OUTx disabled based on OE pin (Default for OUT2-6, Disable mode is defined by OEMx
bits), "0"= Outputs enabled and no association with OE pin (Default));
SH=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-rides OEx and OSx bits, "0"=Ouput
Enable/Disable (Default))
OKC
OKC=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:
Address 0x1D, Bit 7 [5:0], and Address 0x1E are reserved and should be set to "0"
32
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
RAM(PROGRAMMINGREGISTER)TABLES
BIT #
(Default Settings)
BIT #
Default
ADDR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION
Register
Hex Value
Configuring Output OUT1
INV1=Output Inversion for OUT1 ("0"= Non-Invert (Default), "1"=Invert);
SLEW1=Slew Rate Settings for OUT1 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM1= Output Enable Mode for OUT1 output, when used with OE1 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
OEM1[1;0]
SLEW1[1:0]
0x1F
0
0
0
0
0
0
0
0
00
INV1
Address 0x1F, Bits 3, 1, 0 are reserved and should be set to "0"
IP1[2:0]_CONFIG0
IP1[2:0]_CONFIG1
IP1[2:0]_CONFIG2
IP1[2:0]_CONFIG3
RZ1[3:0]_CONFIG0
RZ1[3:0]_CONFIG1
RZ1[3:0]_CONFIG2
RZ1[3:0]_CONFIG3
CZ1[3:0]_CONFIG0
CZ1[3:0]_CONFIG1
CZ1[3:0]_CONFIG2
CZ1[3:0]_CONFIG3
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ODIV1_CONFIG0
ODIV1_CONFIG1
ODIV1_CONFIG2
ODIV1_CONFIG3
PLL1 LOOP FILTER SETTING
Loop Filter Values for PLL1 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV1_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated
with PLL1; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3KΩ + RZ1[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ1[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP1[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP1[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
CP1[3:0]_CONFIG0
CP1[3:0]_CONFIG1
CP1[3:0]_CONFIG2
CP1[3:0]_CONFIG3
D1[7:0]_CONFIG0
D1[7:0]_CONFIG1
D1[7:0]_CONFIG2
D1[7:0]_CONFIG3
N1[7:0]_CONFIG0
N1[7:0]_CONFIG1
N1[7:0]_CONFIG2
N1[7:0]_CONFIG3
PLL1 INPUT DIVIDER D1 SETTING
PLL1 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL1 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N1[11:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A1[3:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET1[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x68-0x6F
A1[3:0]_CONFIG0
A1[3:0]_CONFIG1
A1[3:0]_CONFIG2
A1[3:0]_CONFIG3
N1[11:8]_CONFIG0
N1[11:8]_CONFIG1
N1[11:8]_CONFIG2
N1[11:8]_CONFIG3
Total Multiplier Value M1 = 2 * N1[11:0] + A1 + 1 + SS_OFFSET1 * 1/64
When A1[3:0] = 0 and spread spectrum disabled, M1= 2 * N1[11:0];
When A1[3:0] > 0 and spread spectrum disabled, M1 = 2 * N1[11:0] + A1 + 1 ;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
PRIMCLK=Priority Selection for Input Clock ("0"=XTALIN/REF_IN becomes Primary (Default), "1"=CLK_IN becomes Primary);
SM = Switchover Mode ("0x"=Manual, "10"= Auto-NonRevertive, "11"=Auto-Revertive (Default));
Bit 3 is reserved and should be set to "0".
SRC2[1:0]
SRC1[1:0]
SM[1:0]
0x34
0x35
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
46
55
PRIMCLK
SRCx[1:0]=Input Source Selection for Output Dividers "Qx" blocks ("00"=Selected Input CLK, "01"=PLL0, "10"=PLL1, "11"=PLL2);
Default on SRC1 is the selected input clock. Default on SRC2-6 is PLL0 which will be powered down.
SRC6[1:0]
SRC5[1:0]
SRC4[1:0]
SRC3[1:0]
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
No Registers Exist
IP2[2:0]_CONFIG0
IP2[2:0]_CONFIG1
IP2[2:0]_CONFIG2
IP2[2:0]_CONFIG3
RZ2[3:0]_CONFIG0
RZ2[3:0]_CONFIG1
RZ2[3:0]_CONFIG2
RZ2[3:0]_CONFIG3
CZ2[3:0]_CONFIG0
CZ2[3:0]_CONFIG1
CZ2[3:0]_CONFIG2
CZ2[3:0]_CONFIG3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
ODIV2_CONFIG0
ODIV2_CONFIG1
ODIV2_CONFIG2
ODIV2_CONFIG3
PLL2 LOOP FILTER SETTING
Loop Filter Values for PLL2 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV2_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with
PLL2; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3KΩ + RZ2[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ2[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP2[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP2[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
CP2[3:0]_CONFIG0
CP2[3:0]_CONFIG1
CP2[3:0]_CONFIG2
CP2[3:0]_CONFIG3
33
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
RAM(PROGRAMMINGREGISTER)TABLES
BIT #
(Default Settings)
BIT #
Default
ADDR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION
Register
Hex Value
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
00
00
00
00
00
00
00
00
00
00
00
00
00
BB
00
00
00
BB
00
00
0C
BB
00
00
0C
BB
00
00
03
BB
00
00
D2[7:0]_CONFIG0
D2[7:0]_CONFIG1
D2[7:0]_CONFIG2
D2[7:0]_CONFIG3
N2[7:0]_CONFIG0
N2[7:0]_CONFIG1
N2[7:0]_CONFIG2
N2[7:0]_CONFIG3
PLL2 INPUT DIVIDER D2 SETTING
PLL2 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL2 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N2[11:0]_CONFIGx - Part of PLL2 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
Total Multiplier Value M2 = N2;
N2[11:8]_CONFIG0
N2[11:8]_CONFIG1
N2[11:8]_CONFIG2
N2[11:8]_CONFIG3
INV2
Bits [7:4] in addresses 0x48, 0x49, 0x4A, and 0x4B are reserved and should be set to "0"
OEM2[1:0]
SLEW2[1:0]
Configuring Output OUT2
INV2=Output Inversion for OUT2 ("0"= Non-Invert (Default), "1"=Invert);
SLEW2=Slew Rate Settings for OUT2 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM2= Output Enable Mode for OUT2output, when used with OE2 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Q2[x:x]=Output Divider "Q2" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM2[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT2, PM2 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Q2[1:0]_CONFIG1
PM2[1:0]_CONFIG1
Q2[1:0]_CONFIG0
PM2[1:0]_CONFIG0
Q2[9:2]_CONFIG0
Address 0x4C, Bits 3, 1, 0 are reserved and should be set to "0"
Q2[9:2]_CONFIG1
OEM3[1:0]
SLEW3[1:0]
INV3
Configuring Output OUT3
INV3=Output Inversion for OUT3 ("0"= Non-Invert (Default), "1"=Invert);
SLEW3=Slew Rate Settings for OUT3 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM3= Output Enable Mode for OUT3 output, when used with OE3 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Q3[x:x]=Output Divider "Q3" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM3[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT3, PM3 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Q3[1:0]_CONFIG1
PM3[1:0]_CONFIG1
Q3[1:0]_CONFIG0
PM3[1:0]_CONFIG0
Q3[9:2]_CONFIG0
Address 0x50, Bits 3, 1, 0 are reserved and should be set to "0"
Q3[9:2]_CONFIG1
OEM4[1:0]
SLEW4[1:0]
LVL4[1:0]
INV4_1
INV4_0
Configuring Output OUT4
INV4_1=Output Inversion for /OUT4 ("0"= Invert , "1"=Non-Invert (Default));
INV4_0=Output Inversion for OUT4 ("0"= Invert , "1"=Non-Invert (Default));
SLEW4=Slew Rate Settings for OUT4 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM4= Output Enable Mode for OUT4 output, when used with OE4 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
LVL4=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);
Q4[x:x]=Output Divider "Q4" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM4[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT4, PM4 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Q4[1:0]_CONFIG1
PM4[1:0]_CONFIG1
Q4[1:0]_CONFIG0
PM4[1:0]_CONFIG0
Q4[9:2]_CONFIG0
When using LVPECL or LVDS outputs, SLEW4 must be set to "00".
Q4[9:2]_CONFIG1
OEM5[1:0]
SLEW5[1:0]
LVL5[1:0]
INV5_1
INV5_0
Configuring Output OUT5
INV5_1=Output Inversion for /OUT5 ("0"= Invert, "1"=Non-Invert (Default));
INV5_0=Output Inversion for OUT5 ("0"= Invert, "1"=Non-Invert (Default));
SLEW5=Slew Rate Settings for OUT5 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM5= Output Enable Mode for OUT5 output, when used with OE5 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
LVL5=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);
Q5[x:x]=Output Divider "Q5" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM5[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT5, PM5 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Q5[1:0]_CONFIG1
PM5[1:0]_CONFIG1
Q5[1:0]_CONFIG0
PM5[1:0]_CONFIG0
Q5[9:2]_CONFIG0
When using LVPECL or LVDS outputs, SLEW5 must be set to "00".
Q5[9:2]_CONFIG1
OEM6[1:0]
SLEW6[1:0]
INV6
Configuring Output OUT6
INV6=Output Inversion for OUT6 ("0"= Non-Invert (Default), "1"=Invert);
SLEW6=Slew Rate Settings for OUT6 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM6= Output Enable Mode for OUT6 output, when used with OE6 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Q6[x:x]=Output Divider "Q6" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM6[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT6, PM6 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Q6[1:0]_CONFIG1
PM6[1:0]_CONFIG1
Q6[1:0]_CONFIG0
PM6[1:0]_CONFIG0
Q6[9:2]_CONFIG0
Address 0x5C, Bits 3 is reserved and should be set to "0"
Address 0x5C, Bits 1, 0 are reserved and should be set to "1"
Q6[9:2]_CONFIG1
34
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
RAM(PROGRAMMINGREGISTER)TABLES
BIT #
(Default Settings)
BIT #
Default
ADDR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION
Register
Hex Value
TSSC0[3:0]
X2_0
NSSC0[3:0]
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
SS_OFFSET0[5:0]
DITH0
SD0[3:0][1]
SD0[3:0][3]
SD0[3:0][5]
SD0[3:0][7]
SD0[3:0][9]
SD0[3:0][11]
TSSC1[3:0]
X2_1
SD0[3:0][0]
SPREAD SPRECTRUM SETTINGS FOR PLL0
SD0[3:0][2]
SD0[3:0][4]
SD0[3:0][6]
SD0[3:0][8]
SS_OFFSET0=SS Fractional Offset/ First Sample (Unsigned);
TSSC0=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC0=# of SS Samples to Use from SS Memory (Default is "0");
DITH0=LSB DITHER on Σ, ("1"=dither on, "0"=off (Default));
X2_0=ΣΔ output x2, ("1"=x2, "0"=normal (Default));
SD0=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET0, then SS_OFFSET0+SD0[0], etc. (Default is "0");
SD0[3:0][10]
NSSC1[3:0]
SS_OFFSET1[5:0]
DITH1
SD1[3:0][1]
SD1[3:0][3]
SD1[3:0][5]
SD1[3:0][7]
SD1[3:0][9]
SD1[3:0][11]
SD1[3:0][0]
SD1[3:0][2]
SD1[3:0][4]
SD1[3:0][6]
SD1[3:0][8]
SD1[3:0][10]
SPREAD SPRECTRUM SETTINGS FOR PLL1
SS_OFFSET1=SS Fractional Offset/ First Sample (Unsigned);
TSSC1=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC1=# of SS Samples to Use from SS Memory (Default is "0");
DITH1=LSB DITHER on ΣΔ, ("1"=dither on, "0"=off (Default));
X2_1=ΣΔ output x2, ("1"=x2, "0"=off (Default));
SD1=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET1, then SS_OFFSET1+SD1[0], etc. (Default is "0");
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
No Registers Exist
CRC error in EEPROM
CERR = CRC error bit indicator ("1`" = CRC error)
CERR
Read-Only
35
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
RECOMMENDEDLANDINGPATTERN
NL 28 pin
NOTE: All dimensions are in millimeters.
36
IDT5V9888
INDUSTRIALTEMPERATURERANGE
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
ORDERINGINFORMATION
XXXXX
XX
X
IDT
Package Process
Device Type
Industrial (-40°C to +85°C)
I
Thin Quad Flat Pack - Green
PFG
Thermally Enhanced Plastic Very Fine Pitch
Quad Flat No Lead Package - Green
NLG
3.3V EEPROM Programmable Clock Generator
5V9888
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
clockhelp@idt.com
www.idt.com
37
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