7006L15FG [IDT]
Dual-Port SRAM, 16KX8, 15ns, CMOS, PQCC68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QFP-68;
| 型号： | 7006L15FG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 16KX8, 15ns, CMOS, PQCC68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QFP-68 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
IDT7006S/L
◆
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Features
◆
True Dual-Ported memory cells which allow simultaneous
◆
◆
◆
reads of the same memory location
High-speed access
◆
– Military:20/25/35/55/70ns(max.)
– Industrial:55ns (max.)
◆
◆
– Commercial:15/17/20/25/35/55ns(max.)
Low-power operation
◆
– IDT7006S
◆
◆
◆
Active:750mW(typ.)
Standby: 5mW (typ.)
– IDT7006L
Active:700mW(typ.)
Standby: 1mW (typ.)
IDT7006 easily expands data bus width to 16 bits or more
◆
◆
◆
using the Master/Slave select when cascading more than
one device
FunctionalBlockDiagram
OE
R
OEL
CE
R/W
R
CE
L
R/W
L
R
I/O0L- I/O7L
I/O0R-I/O7R
I/O
I/O
Control
Control
BUSY (1,2)
L
(1,2)
BUSY
R
A
13L
A
13R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
0R
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
L
CE
OE
R/W
R
R
L
R
L
SEM
R
SEM (2)
L
M/S
(2)
INT
L
INTR
2739 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
OCTOBER 2008
1
©2008IntegratedDeviceTechnology,Inc.
DSC-2739/16
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
a very low standby power mode.
The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT7006isdesignedtobeusedasastand-alone128K-bitDual-PortRAM
orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more
wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error-
freeoperationwithouttheneedforadditionaldiscretelogic.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typically operate on only 750mW of power. Low-power (L)
versionsofferbatterybackupdataretentioncapabilitywithtypicalpower
consumptionof500µWfroma2Vbattery.
TheIDT7006ispackagedinaceramic68-pinPGA, an68-pinquad
flatpack,aPLCC,anda64-pinthinquadflatpack,TQFP.Militarygrade
productismanufacturedincompliancewiththelatestrevisionofMIL-PRF-
38535 QML, Class B, making it ideally suited to military temperature
applicationsdemandingthehighestlevelofperformanceandreliability.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
PinConfigurations(1,2,3)
INDEX
11/06/01
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
IDT7006J or F
J68-1(4)
54
53
52
51
50
49
48
47
46
45
44
INT
L
F68-1(4)
VCC
BUSY
GND
M/S
BUSY
INT
L
GND
I/O0R
I/O1R
I/O2R
68 Pin PLCC / Flatpack
Top View(5)
.
R
R
VCC
A0R
A1R
A2R
A3R
A4R
I/O3R
I/O4R
I/O5R
I/O6R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2739 drw 02
11/06/01
INDEX
A
A
A
A
A
4L
3L
2L
1L
0L
1
2
3
48
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
47
46
4
5
6
45
44
43
INT
L
7006PF
PN-64(4)
BUSY
GND
M/S
L
7
8
9
42
41
40
39
38
37
VCC
64 Pin TQFP
Top View(5)
GND
I/O0R
I/O1R
I/O2R
BUSY
R
10
11
12
INT
R
A
A
A
A
A
0R
13
14
15
16
1R
2R
3R
4R
VCC
36
35
34
NOTES:
I/O3R
I/O4R
I/O5R
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
33
3. J68-1 package body is approximately .95 in x .95 in. x .17 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
2739 drw 03
2
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3)(con't.)
51
50
48
A
46
A
44
42
40
38
36
11/06/01
11
10
09
08
07
A4L
2L
1L
0L BUSY
L
M/S INT
R
A1R
A3R
A
5L
6L
53
A
52
49
47
A
45
INT
43
GND
41
BUSY
39
A
37
35
34
L
R
A4R
7L
A3L
0R
A2R
A
5R
6R
8R
A
55
A
54
32
33
A
A7R
9L
A
8L
57
A
56
A
30
31
A
A9R
11L
10L
12L
13L
59
58
A
28
29
A10R
A11R
IDT7006G
G68-1(4)
V
CC
61
60
A
26
GND
27
06
05
04
03
02
01
A12R
N/C
63
SEM
68-Pin PGA
Top View(5)
62
24
N/C
25
A
L
13R
CE
L
65
OE
64
22
SEM
23
R
CER
L
R/W
L
67
I/O0L
66
20
OE
21
R/WR
R
N/C
1
3
5
GND
7
9
68
11
13
V
15
18
I/O7R
19
N/C
.
GND
I/O7L
CC
I/O1L
I/O4L
I/O2L
I/O1R
I/O4R
2
4
6
8
10
12
14
16
17
I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
V
CC
I/O6L
I/O3L
A
B
C
D
E
F
G
H
J
K
L
INDEX
2739 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A0L - A13L
A0R - A13R
I/O0L - I/O7L
SEM
INT
BUSY
I/O0R - I/O7R
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
L
SEM
INT
BUSY
M/S
R
L
R
L
R
Master or Slave Select
Power
V
CC
GND
Ground
2739 tbl 01
6.42
3
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Outputs
Inputs(1)
R/W
I/O0-7
Mode
CE
H
L
OE
X
SEM
H
X
L
High-Z
DATAIN
Deselected: Power-Down
Write to Memory
X
H
L
H
X
L
H
DATAOUT Read Memory
High-Z Outputs Disabled
X
H
X
2739 tbl 02
NOTE:
1. A0L – A13L is not equal to A0R – A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
R/W
Outputs
I/O0-7
Mode
CE
H
OE
L
SEM
L
H
↑
DATAOUT Read in Semaphore Flag Data Out
H
X
L
DATAIN
Write I/Oo into Semaphore Flag
Not Allowed
____
L
X
X
L
2739 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
RecommendedDCOperating
Conditions
Symbol
Rating
Commercial
& Industrial
Military
Unit
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
(2)
V
TERM
Te rminal Vo ltag e
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
VCC
4.5
5.0
5.5
0
V
V
V
0
0
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
T
BIAS
____
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
VIL
-0.5(1)
V
Storage
Temperature
TSTG
2739 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
DC Output
Current
mA
IOUT
2739 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sec-tions of this specification is not implied. Exposure
to absolute maxi-mum rating conditions for extended periods may affect
reliability.
MaximumOperatingTemperature
andSupplyVoltage(1)
Ambient
Grade
Temperature
-55OC to+125OC
0OC to +70OC
40OC to +85OC
GND
Vcc
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM < Vcc + 10%.
Military
0V
5.0V
+
+
+
10%
Commercial
Industrial
0V
5.0V
5.0V
10%
10%
Capacitance(1) (TA = +25°C, f = 1.0mhz)
0V
Symbol
Parameter
Conditions(2)
Max.
Unit
pF
2739 tbl 07
NOTES:
C
IN
Input Capacitance
VIN = 3dV
9
1. This is the parameter TA. This is the "instant on" case temperature.
Output
Capacitance
VOUT = 3dV
10
pF
COUT
2739 tbl 05
NOTES:
1. These parameters are determined by device characterization, but are not
production tested (TQFP Package Only).
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
4
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the 0perating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7006S
7006L
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
CC = 5.5V, VIN = 0V to VCC
___
___
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
CE = VIH, VOUT = 0V to VCC
VOL
IOL = 4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2739 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
(1)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
___
___
VDR
VCC for Data Retention
V
CC = 2
V
2.0
___
ICCDR
Data Retention Current
µA
CE > VHC
IN > VHC or < VLC
Mil. & Ind.
Com'l.
100
4000
___
V
100
1500
(3)
CDR
___
___
t
Chip Deselect to Data Retention Time
Operation Recovery Time
SEM > VHC
0
ns
(3)
(2)
___
___
t
R
t
RC
ns
2739 tbl 09
NOTES:
1. TA = +25°C, VCC = 2V, and are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
DR > 2V
VCC
4.5V
4.5V
V
tCDR
tR
VDR
CE
VIH
VIH
2739 drw 05
6.42
5
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7006X15
7006X17
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Com'l Only
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2 )
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
170
160
310
260
170
160
310
260
160
150
290
240
155
145
265
220
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
160
150
370
320
155
145
340
280
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
20
10
60
50
20
10
60
50
20
10
60
50
16
10
60
50
mA
mA
CE
SEM
f = fMAX
L
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
____
____
____
____
____
____
____
____
MIL &
IND
S
L
20
10
90
70
16
10
80
65
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
105
95
190
160
105
95
190
160
95
85
180
150
90
80
170
140
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
95
85
240
210
90
80
215
180
SEMR = SEML = VIH
I
SB3
Full Standby Current (Both Both Ports CE
L
and
> VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
Ports - All CMOS Level
Inputs)
CER
V
____
____
____
____
____
____
____
____
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
V
R
L
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
S
L
100
90
170
140
100
90
170
140
90
80
155
130
85
75
145
120
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEM = SEM > VCC - 0.2V
R
L
____
____
____
____
____
____
____
____
MIL &
IND
S
L
90
80
225
200
85
75
200
170
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f = fMAX
2739 tbl 10
7006X35
Com'l &
Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
____
____
____
____
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
L
150
140
250
210
150
140
250
210
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
MIL &
IND
S
L
150
140
300
250
150
140
300
250
140
130
300
250
____
____
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
13
10
60
50
13
10
60
50
mA
mA
mA
mA
CE
SEM
f = fMAX
L
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
MIL &
IND
S
L
13
10
80
65
13
10
80
65
10
8
80
65
____
____
(5)
____
____
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
75
155
130
85
75
155
130
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
85
75
MIL &
IND
S
L
190
160
85
75
190
160
80
70
190
160
SEMR = SEML = VIH
____
____
____
____
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L
and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
R
V
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
V
R
L
____
____
____
____
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
S
L
80
70
135
110
80
70
135
110
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEM = SEM > VCC - 0.2V
R
L
MIL &
IND
S
L
80
70
175
150
80
70
175
150
75
65
175
150
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f = fMAX
2739 tbl 11
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC =120ma (typ)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".
6
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
5V
5V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
1250Ω
1250Ω
DATAOUT
BUSY
INT
Input Rise/Fall Times
DATAOUT
Input Timing Reference Levels
Output Reference Levels
Output Load
5pF*
775Ω
30pF
775Ω
1.5V
,
Figures 1 and 2
2739 drw 06
2739 tbl 12
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(5pF for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
AC Electrical Oharacteristics Over the
OperatingtemperatureandSupplyVoltageRange(4)
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l,Ind
& Military
7006X25
Com'l & Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
17
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
15
15
17
17
20
20
25
25
Chip Enable Access Time(3)
____
____
____
____
____
____
____
____
t
t
Output Enable Access Time
10
10
12
13
____
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
3
____
____
____
____
t
3
3
3
3
Output High-Z Time(1,2)
10
10
12
15
____
____
____
____
t
t
Chip Enable to Power Up Time(2,5)
Chip Disable to Power Down Time(2,5)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
0
____
____
____
____
____
____
____
____
t
15
17
20
25
____
____
____
____
t
10
10
10
10
____
____
____
____
t
15
17
20
25
2739 tbl 13a
7006X35
Com'l &
Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min. Max.
Min.
Max.
Unit
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
35
35
55
55
70
70
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
t
t
20
30
35
____
____
____
t
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
15
25
30
____
____
____
t
t
Chip Enable to Power Up Time(2,5)
Chip Disable to Power Down Time(2,5)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
35
50
50
____
____
____
t
15
15
15
____
____
____
t
35
55
70
2739 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
6.42
7
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
t
RC
ADDR
(4)
t
t
AA
(4)
ACE
CE
(4)
tAOE
OE
R/W
(1)
LZ
tOH
t
VALID DATA(4)
DATAOUT
(2)
HZ
t
BUSYOUT
(3,4)
tBDD
2739 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
ISB
,
2739 drw 08
8
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7006X15
7006X17
Com'l Only
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
17
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
12
0
15
0
20
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
10
15
15
____
____
____
____
t
10
10
12
15
____
____
____
____
t
0
0
0
0
(1,2)
____
____
____
____
____
____
____
____
____
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
12
15
____
____
t
0
5
5
0
5
5
0
5
5
0
5
5
____
____
____
____
t
t
ns
2739 tbl 14a
7006X35
Com'l & Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
70
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
25
0
40
0
50
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
30
40
____
____
____
t
15
25
30
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
25
30
____
____
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2739 tbl 14b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested but not tested.
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.42
9
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
HZ
t
OE
tAW
CE or SEM(9)
(3)
WR
(6)
AS
(2)
tWP
t
t
R/W
DATAOUT
DATAIN
(7)
WZ
t
OW
t
(4)
(4)
tDW
tDH
2739 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
tAW
CE or SEM(9)
R/W
(3)
WR
(6)
AS
(2)
EW
t
t
t
t
DW
tDH
DATAIN
2739 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore CE = VIH and SEM = VIL. tEW must be met for either condition.
10
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tACE
tAW
tWR
t
t
EW
SEM
t
DW
tSOP
DATAOUT
VALID
DATA
0
DATAIN VALID
tAS
WP
tDH
R/W
tSWRD
tAOE
OE
t
SOP
Read Cycle
Write Cycle
2739 drw 11
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) “A”
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2739 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
11
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7006X15
7006X17
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Com'l Only
Com'l Only
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
17
17
17
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
17
____
____
____
____
t
5
5
5
5
____
____
____
____
BUSY Disable to Valid Data(3)
t
18
18
30
30
t
Write Hold After BUSY(5)
12
13
15
17
____
____
____
____
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
0
0
ns
ns
tWH
12
13
15
17
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
Write Data Valid to Read Data Delay(1)
(1)
____
____
____
____
____
____
____
____
t
WDD
30
25
30
25
45
35
50
35
ns
tDDD
ns
2739 tbl 15a
7006X35 Com'l
& Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
45
40
40
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
20
35
35
____
____
____
t
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
t
35
40
45
t
Write Hold After BUSY(5)
25
25
25
____
____
____
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
0
ns
ns
tWH
25
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
60
45
80
65
95
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2739 tbl 15b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. 'X' is part numbers indicates power rating (S or L).
.
12
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY(2,5)(M/S =VIH)(4)
t
WC
MATCH
ADDR"A"
R/W"A"
tWP
t
DW
tDH
VALID
DATAIN "A"
(1)
APS
t
MATCH
ADDR"B"
t
BDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
DDD
t
2739 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL(slave) then BUSY is input (BUSY"A" = VIH) and BUSY"B" = "don't care", for this example.
5. All timing is the same for left and right port. Port "A' may be either left or right port. Port "B" is the port opposite from Port "A".
Timing Waveform of Write with BUSY
t
WP
R/W"A"
(3)
tWB
BUSY"B"
(1)
t
WH
(2)
R/W"B"
2739 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' Version.
6.42
13
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2739 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1)(M/S = VIH)
ADDRESS "N"
ADDR"A"
ADDR"B"
BUSY"B"
(2)
APS
t
MATCHING ADDRESS "N"
t
BAA
tBDA
2739 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
____
____
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
0
ns
ns
ns
t
0
0
0
0
____
____
____
____
t
15
15
15
15
20
20
20
20
____
____
____
____
t
Interrupt Reset Time
ns
2739 tbl 16a
7006X35
Com'l &
Military
7006X55
Com'l, Ind
& Military
7006X70
Military Only
Symbol
INTERRUPT TIMING
Parameter
Min. Max.
Min. Max.
Min.
Max. Unit
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
____
t
0
0
0
ns
____
____
____
t
25
25
40
40
50
50
ns
____
____
____
t
Interrupt Reset Time
ns
2739 tbl 16b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
14
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
t
WC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(4)
WR
(3)
AS
t
t
CE"A"
R/W"A"
INT"B"
(3)
INS
t
2739 drw 17
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
INR
t
INT"B"
2739 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TruthTables
Truth Table III — Interrupt Flag(1,4)
Left Port
Right Port
OE
R/WL
A13L-A0L
R/WR
A
13R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OE
L
INTL
CER
R
INTR
(2)
L
L
X
X
L
X
X
X
L
3FFF
X
X
X
X
L
L
X
X
L
X
3FFF
3FFE
X
L
R
(3)
X
X
X
H
R
(3)
X
X
L
L
X
X
X
L
(2)
X
3FFE
H
X
X
L
2739 tbl 17
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.42
15
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY Arbitration
Inputs
Outputs
A
OL-A13L
(1)
AOR-A13R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY (1)
L
BUSY
R
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
(3)
MATCH
(2)
(2)
Write Inhibit
2739 tbl 18
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7006 are
push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D7
Left
D0
- D7
Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
1
1
0
0
1
1
0
1
1
1
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2739 tbl 19
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7006.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
TheIDT7006providestwoportswithseparatecontrol,addressand Theleftportclearstheinterruptbyreadingaddresslocation3FFEaccess
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation when CER = OER = VIL, R/W is a "don't care". Likewise, the right port
inmemory.TheIDT7006hasanautomaticpowerdownfeaturecontrolled interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
by CE. The CE controls on-chip power down circuitry that permits the 3FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
respectiveporttogointoastandbymodewhennotselected(CEHIGH). thememorylocation3FFF. Themessage(8bits)at3FFEor3FFFisuser-
Whenaportisenabled,accesstotheentirememoryarrayispermitted. defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction
isnotused,addresslocations3FFEand3FFFarenotusedasmailboxes,
butaspartoftherandomaccessmemory.RefertoTruthTableIIIforthe
interruptoperation.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
BusyLogic
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX) where a write is defined as CE = R/W = VIL per the Truth Table.
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
16
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
SLAVE
Dual Port
RAM
MASTER
Dual Port
RAM
CE
CE
BUSY (R)
BUSY (L)
BUSY (L)
BUSY (R)
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY (R)
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
BUSY (L)
2739 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7006 RAMs.
a master/slave array, bothaddress andchipenable mustbe validlong
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSY indicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe
slave.
SEMAPHORES
TheIDT7006isanextremelyfastDual-Port16Kx8CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
The Dual-PortRAMfeatures a fastaccess time, andbothports are
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chippowerdowncircuitrythatpermits the respective porttogointo
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7006containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7006shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7006doesnotuseitssemaphoreflagstocontrol
TheBUSYoutputsontheIDT7006RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganIDT7006RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill
receivea BUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemaster,usethe
BUSYsignalasawriteinhibitsignal.ThusontheIDT7006RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
6.42
17
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
anyresourcesthroughhardware,thusallowingthesystemdesignertotal cause either signal (SEM or OE) to go inactive or the output will never
flexibilityinsystemarchitecture.
change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin to guarantee that no system level contention will occur. A processor
either processor. This can prove to be a major advantage in very high- requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
speedsystems.
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requestedandthe processorwhichrequesteditnolongerneeds the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The criticalcase ofsemaphore timingis whenbothsides requesta
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
thesametime,theassignmentwillbearbitrarilymadetooneportorthe
other.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
ormisinterpreted, a software errorcaneasilyhappen.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thispro-cessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,
theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
The eightsemaphore flags reside withinthe IDT7006ina separate
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
throughaddresspinsA0–A2. Whenaccessingthesemaphores,none
oftheotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
signalsgoactive.Thisservestodisallowthesemaphorefromchanging resourcemarkersfortheIDT7006’sDual-PortRAM.Saythe16Kx8RAM
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside. wastobedividedintotwo8Kx8blockswhichweretobededicatedatany
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust onetimetoservicingeithertheleftorrightport.Semaphore0couldbeused
18
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
toindicatethesidewhichwouldcontrolthelowersectionofmemory,and evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
Semaphore1couldbedefinedas the indicatorfortheuppersectionof given a common meaning as was shown in the example above.
memory.
Semaphores are a useful form of arbitration in systems like disk
Totakearesource,inthis examplethelower8KofDual-PortRAM, interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
the processor on the left port could write and then read a zero in to atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
backratherthana one), the leftprocessorwouldassume controlofthe was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof theirassignedportionsofmemorycontinuouslywithoutanywaitstates.
the resourceaftertheleftprocessor,itwouldreadbackaoneinresponse
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the stateisavailableononeorbothsides.Onceasemaphorehandshakehas
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby been performed, both processors can access their assigned RAM
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining segmentsatfullspeed.
control,itwouldlockouttheleftside.
Anotherapplicationisintheareaofcomplexdatastructures. Inthis
Once the left side was finished with its task, it would write a one to case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
Semaphore 0 and may then try to gain access to Semaphore 1. If mayberesponsibleforbuildingandupdatingadatastructure.Theother
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then processorreadsanincompletedatastructure,amajorerrorconditionmay
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
8Kblocks ofDual-PortRAMwitheachother.
itandthenisabletogoinandupdatethedatastructure.Whentheupdate
The blocks do not have to be any particular size and can even be is completed, the data structure block is released. This allows the
variable, depending upon the complexity of the software using the interpretingprocessortocomebackandreadthecompletedatastructure,
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- therebyguaranteeingaconsistentdatastructure.
PortRAMorothersharedresources intoeightparts. Semaphores can
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
,
READ
2739 drw 20
Figure 4. IDT7006 Semaphore Logic
6.42
19
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
A
XXXXX
A
999
A
A
Device Power Speed Package
Type
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
I(1)
B
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G(2)
Green
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
68-pin Flatpack (F68-1)
F
15
17
20
25
35
55
70
Commercial Only
Commercial Only
Commercial, Industrial & Military
Commercial & Military
Commercial & Military
Commercial, Industrial, & Military
Military Only
Speed in nanoseconds
S
L
Standard Power
Low Power
128K (16K x 8) Dual-Port RAM
7006
2739 drw 21
NOTES:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
01/04/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Changed 3FFF to 3FFE in Truth Table III
Replaced IDT logo
Corrected drawing error
Addedcopywrightinfo
Increasedstoragetemperatureparameter
ClarifiedTAparameter
06/03/99:
09/14/99:
11/10/99:
12/22/99:
05/08/00:
Page 15
Page 1
Page 1
Page 4
Page 6
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±500mVto0mVinnotes
Addeddaterevisionforpinconfigurations
09/12/01:
Page 2 & 3
Page 6
AddedIndustrialtemptothecolumnheadingfor20nstoDCElectricalCharacteristics
Pages7,9,12&14 AddedIndustrialtemptothecolumnheadingsfor20nstoACElectricalCharacteristics
Page 7
Pages4,6,7,9,
12 & 14
Table 13a appeared twice, corrected and placed table 13b for 35, 55 & 70ns speeds
RemovedIndustrialtempnotefromalltables
Page 20
Page 1
Page 20
Page 20
AddedIndustrialtempto20nsinorderinginformation
Addedgreenavailabilitytofeatures
Addedgreenindicatortoorderinginformation
Removed "IDT" from orderable part number
01/31/06:
10/21/08:
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20
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