70121L35JG [IDT]
Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52;
| 型号： | 70121L35JG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
2K x 9 DUAL-PORT
IDT70121S/L
IDT70125S/L
STATIC RAM
WITH BUSY & INTERRUPT
◆
Features
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY output flag on Master; BUSY input on Slave
INT flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
✵
◆
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 35ns (max.)
Low-power operation
◆
◆
◆
◆
◆
◆
◆
◆
– IDT70121/70125S
Active:675mW(typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active:675mW(typ.)
Standby: 1mW (typ.)
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
◆
FunctionalBlockDiagram
OER
OEL
CE
R/W
R
CE
R/W
L
R
L
I/O0L- I/O8L
I/O0R-I/O8R
I/O
I/O
Control
Control
BUSY (1,2)
L
(1,2)
R
BUSY
A
10R
0R
A
10L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0L
11
11
ARBITRATION
INTERRUPT
LOGIC
CE
L
L
CE
OE
R/W
R
R
OE
R
R/W
L
(2)
(2)
L
INT
INTR
2654 drw 01
NOTES:
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.
70125 (SLAVE): BUSY is input.
2. INT is non-tri-stated push-pull output.
AUGUST 2014
1
DSC 2654/13
©2014 Integrated Device Technology, Inc.
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Description
feature,controlledbyCE,permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for
Data/Controlandparitybitsattheuser’soption. Thisfeatureisespecially
usefulindatacommunicationsapplicationswhereitisnecessarytousea
paritybitfortransmission/receptionerrorchecking.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 675mW of power. Low-power (L)
versions offer battery backup data retention capability with each port
typicallyconsuming200µWfroma2Vbattery.
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static
RAMs.TheIDT70121isdesignedtobeusedasastand-alone9-bitDual-
PortRAMorasa“MASTER”Dual-PortRAMtogetherwiththeIDT70125
“SLAVE”Dual-Portin18-bit-or-morewordwidthsystems.UsingtheIDT
MASTER/SLAVEDual-PortRAMapproachin18-bit-or-widermemory
systemapplicationsresultsinfull-speed,error-freeoperationwithoutthe
needforadditionaldiscretelogic.
Both devices provide two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power-down
The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC.
PinConfigurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedDC
OperatingConditions
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Min.
Typ.
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
T
BIAS
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
V
-0.5(1)
V
____
Storage
Temperature
TSTG
2654 tbl 03
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
IOUT
DC Output
Current
mA
2654 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximumratingconditionsforextendedperiodsmayaffectreliability.
Capacitance(TA = +25°C, f = 1.0MHz)
Conditions(1 )
Symbol
Parameter
Input Capacitance
Output Capacitance
Max. Unit
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
CIN
V
IN = 3dV
9
pF
COUT
V
OUT = 3dV
10
pF
2654 tbl 04
NOTE:
1. This parameter is determined by device characterization but is not production
tested.
MaximumOperatingTemperature
andSupplyVoltage(1)
Grade
Ambient
GND
Vcc
Temperature
Commercial
Industrial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
10%
-40OC to +85OC
2654 tbl 02
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70121S
70125S
70121L
70125L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CC = 5.5V, CE = VIH, VOUT = 0V to VCC
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
|ILI|
V
V
5
5
___
___
___
___
|ILO
|
10
V
OL
OH
I
OL = +4mA
0.4
0.4
___
___
V
Output High Voltage
I
OH = -4mA
2.4
2.4
V
2654 tbl 05
NOTE:
1. At Vcc < 2.0V leakages are undefined.
3
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4) (VCC = 5V ± 10%)
70121X25
70125X25
70121X35
70125X35
Com'l
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.
Max.
Typ.
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
L
135
135
260
220
135
135
250
210
mA
CE = VIL, Outputs Disabled
(2)
f = fMAX
___
___
___
___
IND
S
L
135
135
275
250
I
SB1
Standby Current
COM'L
IND
S
L
30
30
65
45
30
30
65
45
mA
mA
CE"A" = CE"B" = VIH
(Both Ports - TTL Level Inputs)
(2)
f = fMAX
___
___
___
___
S
L
30
30
80
65
(5)
ISB2
Standby Current
(One Port - TTL Level Inputs)
COM'L
IND
S
L
80
80
175
145
80
80
165
135
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(2)
f=fMAX
___
___
___
___
S
L
80
80
190
165
I
SB3
Full Standby Current (Both Ports
- CMOS Level Inputs)
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
CE"A" and CE"B" > VCC - 0.2V
V
IN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
___
___
___
___
S
L
1.0
0.2
15
5
ISB4
Full Standby Current
(One Port - CMOS Level Inputs)
COM'L
S
L
70
70
170
140
70
70
160
130
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
V
IN > VCC - 0.2V or VIN < 0.2V
___
___
___
___
S
L
70
70
185
160
Active Port Outputs Disabled,
IND
(2)
f = fMAX
2654 tbl 06a
70121X55
70125X55
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
COM'L
S
L
135
135
240
200
mA
mA
mA
CE = VIL, Outputs Disabled
(2)
f = fMAX
___
___
___
___
IND
S
L
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
COM'L
IND
S
L
30
30
65
45
CE"A" = CE"B" = VIH
(2)
f = fMAX
___
___
___
___
S
L
(5)
I
SB2
Standby Current
(One Port - TTL Level Inputs)
COM'L
S
L
80
80
155
125
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(2)
f=fMAX
___
___
___
___
IND
S
L
I
I
SB3
SB4
Full Standby Current
(Both Ports - CMOS Level
Inputs)
COM'L
IND
S
L
1.0
0.2
15
5
mA
mA
CE"A" and CE"B" > VCC - 0.2V
V
V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(3)
___
___
___
___
S
L
Full Standby Current
(One Port - CMOS Level Inputs)
COM'L
IND
S
L
70
70
150
120
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
V
IN > VCC - 0.2V or VIN < 0.2V
S
L
___
___
___
___
Active Port Outputs Disabled,
(2)
f = fMAX
2654 tbl 06b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of
input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, TA=+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
4
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Data Retention Characteristics (L Version Only)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
V
DR
CCDR
(3)
V
CC for Data Retention
2.0
___
I
Data Retention Current
µA
V
V
CC = 2V, CE > VCC - 0.2V
IN > VCC - 0.2V or VIN < 0.2
IND.
100
100
4000
1500
___
tCDR
Chip Deselect to Data Retention Time
COM'L.
(3)
(2)
___
___
tR
Operation Recovery Time
tRC
V
2654 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
≥
4.5V
VDR
4.5V
2V
t
CDR
tR
VDR
CE
VIH
VIH
2654 drw 03
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
5V
5V
1250Ω
1250Ω
DATAOUT
BUSY
INT
DATAOUT
5pF*
775Ω
30pF
775Ω
2654 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
5
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(3)
70121X25
70121X35
70125X35
Com'l
70125X25
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
25
35
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
25
25
35
35
____
____
____
____
t
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
t
12
25
____
____
t
0
0
____
____
t
0
0
Output High-Z Time(1,2)
10
15
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
____
____
____
____
t
50
50
ns
2654 tbl 09a
70121X55
70125X55
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Unit
____
t
t
t
t
t
t
t
t
t
RC
AA
Read Cycle Time
55
ns
ns
ns
ns
ns
ns
ns
ns
____
Address Access Time
55
55
____
____
ACE
AOE
OH
LZ
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
35
____
0
____
0
Output High-Z Time(1,2)
30
____
HZ
PU
PD
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
____
____
50
ns
2654 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
6
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2654 drw 05
(3,4)
tBDD
Timing Waveform of Read Cycle No. 2, Either Side(5)
tACE
CE
OE
(2)
(4)
tHZ
tAOE
(2)
(1)
tHZ
tLZ
VALID DATA
DATAOUT
(1)
(4)
tLZ
tPD
tPU
ICC
50%
50%
CURRENT
ISS
2654 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW.
7
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70121X25
70121X35
70125X35
Com'l
70125X25
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
(4)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(6)
t
t
t
20
0
30
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1, 2,3)
Data Hold Time(5)
12
20
____
____
t
10
15
____
____
t
0
0
(1,3)
____
____
t
Write Enable to Output in High-Z
10
15
____
____
t
Output Active from End-of-Write(1,2,3,5)
0
0
ns
2654 tbl 10a
70121X55
70125X55
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Unit
____
____
____
____
____
____
____
t
t
t
t
t
t
t
t
t
t
t
WC
EW
AW
AS
Write Cycle Time(4)
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
WP
WR
DW
HZ
Write Pulse Width(6)
40
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2,3)
Data Hold Time(5)
20
____
30
____
DH
WZ
OW
0
Write Enable to Output in High-Z(1,3)
30
____
Output Active from End-of-Write(1,2,3,5)
0
ns
____
2654 tbl 10b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
4. 'X' in part numbers indicates power rating (S or L).
5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions.
Although tDH and tOW values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW.
6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
8
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
(3)
tAW
tWR
CE
(7)
(2)
(6)
tAS
tWP
tHZ
R/W
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
2654 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE
(3)
(6)
AS
(2)
tWR
t
tEW
R/W
tDW
tDH
DATAIN
2654 drw 08
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
9
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature
andSupplyVoltageRange(6)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT70121)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
DDD
APS
BDD
WH
20
20
20
20
50
20
20
20
20
60
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(1)
t
t
t
t
t
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Data(3)
35
45
____
____
t
5
5
ns
ns
ns
____
____
t
30
30
t
Write Hold After BUSY(5)
15
20
____
____
BUSY INPUT TIMING (For SLAVE IDT70125)
____
____
____
____
t
WB
WH
WDD
DDD
Write to BUSY Input(4)
0
0
ns
ns
ns
t
Write Hold After BUSY(5)
15
20
____
____
t
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
50
35
60
45
____
____
t
ns
2654 tbl 11a
70121X55
70125X55
Com'l Only
Symbol
BUSY TIMING (For MASTER IDT 70121)
Parameter
Min.
Max.
Unit
____
____
____
____
t
t
t
t
t
t
t
t
t
BAA
BDA
BAC
BDC
WDD
DDD
APS
BDD
WH
30
30
30
30
80
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time(2)
65
____
5
ns
ns
ns
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
45
____
20
BUSY INPUT TIMING (For SLAVE IDT 70125)
____
____
t
t
t
t
WB
Write to BUSY Input(4)
Write Hold After BUSY(5)
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
0
ns
ns
ns
WH
20
____
WDD
DDD
80
65
____
ns
2654 tbl 11b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
10
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)
t
WC
ADDR 'A'
MATCH
tWP
R/W'A'
tDW
tDH
DATAIN'A'
VALID
(1)
tAPS
ADDR'B'
MATCH
tBDA
tBDD
BUSY'B'
t
WDD
DATAOUT 'B'
VALID
(4)
DDD
t
2654 drw 09
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT70125).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(3)
t
WP
R/W"A"
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
,
2654 drw 10
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
(1)
ADDR"A and B"
ADDRESSES MATCH
CE"A"
(2)
APS
t
CE"B"
t
BAC
tBDC
BUSY"B"
2654 drw 11
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
11
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbritration Controlled by Address(1)
tRC
tWC
OR
ADDR'A'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
tAPS
ADDR'B'
tBAA
tBDA
BUSY'B'
2654 drw 12
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. IftAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70121X25
70125X25
70121X35
70125X35
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
25
25
35
35
____
____
t
Interrupt Reset Time
ns
2654 tbl 12a
70121X55
70125X55
Com'l Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Unit
____
____
t
t
t
t
AS
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
ns
ns
ns
WR
INS
INR
0
____
45
45
____
Interrupt Reset Time
ns
2654 tbl 12b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
12
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Interrupt Mode(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR'A'
(4)
(3)
t
WR
t
AS
R/W'A'
(3)
t
INS
INT'B'
2654 drw 13
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TruthTables
Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
X
D
0-8
Function
Port Disable and in Power-Down Mode, ISB2 or ISB4
CE = CE
CE
H
H
L
OE
X
Z
Z
X
X
R
L = H, Power-DownMode, ISB1 or ISB3
L
X
DATAIN
DATAOUT
Z
Data on Port Written Into Memory(2)
Data in Memory Output on Port(3)
High-Impedance Outputs
H
L
L
H
L
H
2654 tbl 13
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II. Interrupt Flag(1,4)
Left Port
Right Port
OE
R/W
L
A10L-A0L
R/W
R
A
10R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CER
R
INTR
L
X
X
X
L
X
X
L
X
7FF
X
X
X
X
X
L
L
X
X
L
X
L(2)
H(3)
X
R
X
X
7FF
7FE
X
R
X
X
L(3)
H(2)
L
X
X
L
L
7FE
X
X
L
2654 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
13
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
FunctionalDescription
The BUSYoutputs on the IDT70121/125 RAM in master mode, are
push-pulltypeoutputsanddonotrequirepullupresistorstooperate. If
theseRAMsarebeingexpandedindepth,thentheBUSYindicationfor
the resulting array requires the use of an external AND gate.
TheIDT70121/125providestwoportswithseparatecontrol,address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70121/125 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
thatpermitstherespectiveporttogointoastandbymodewhennotselected
(CE HIGH). Whenaportisenabled, accesstotheentirememoryarray
ispermitted.
Width Expansion with Busy Logic
Master/SlaveArrays
When expanding an IDT70121/125 RAM array in width while using
BUSYlogic,onemasterpartisusedtodecidewhichsideoftheRAMarray
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemasteruse
theBUSYsignalasawriteinhibitsignal.ThusontheIDT70121RAMthe
BUSY pin is an output of the part, and the BUSY pin is an input of the
IDT70125 as shown in Figure 3.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)isassignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CE = R/W = VIL per Truth Table
II.Theleftportclearstheinterruptbyaccessaddresslocation7FEaccess
when CER = OER = VIL, R/W is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
7FF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess
the memory location 7FF. The message (9 bits) at 7FE or 7FF is user-
defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction
isnotused,addresslocations7FEand7FFarenotusedasmailboxes,
butaspartoftherandomaccessmemory.RefertoTableIIfortheinterrupt
operation.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY
R
BUSY
R
BUSY
L
BUSY
L
Busy Logic
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
BUSY
R
BUSY
L
BUSY
R
BUSYR
BUSY
L
BUSY
L
,
2654 drw 14
Figure 3. Busy and chip enable routing for both width and depth
expansion with 70121 (Master) and 70125 (Slave) RAMs.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use anyBUSY indication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
not desirable, the BUSY logic can be disabled by using the IDT70125
(SLAVE).IntheIDT70125,theBUSYpinoperatessolelyasawriteinhibit
inputpin.NormaloperationcanbeprogrammedbytyingtheBUSYpins
HIGH.OnceinslavemodetheBUSYpinoperatessolelyasawriteinhibit
inputpin. Ifdesired, unintendedwriteoperationscanbepreventedtoa
port by tying theBUSY pin for that port LOW.
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration, onamaster, isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
14
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
OrderingInformation
NOTES:
1. Industrialtemperature:forotherspeeds,packagesandpowerscontactyoursalesoffice.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
Datasheet Document History
01/06/99:
Initiated datasheet document history
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Corrected DSC number
Changedstoragetemperatureparameterfrom-55to+125to-65to+150
ClarifiedTA parameterfootnote
Pages 2 and 3
06/03/99:
05/28/04:
Page 1
Page 3
Page 4
Page 9
Page 2
DCElectricalparameters–changedtestconditionwordingfrom"open"to"disabled"
Changed±500mVto0mVinnotes
Addeddaterevisionforpinconfiguration
Page4, 6, 8,10&12AddedIndustrialtemptocolumnheadingsfor35nsspeedtoDCandACElectricalCharacteristics
Page 4 RemovedIndustrialtempfrom25,45&55nsspeedsfromDCElectricalCharacteristics
Page3,4,6,8,10&12RemovedIndustrialtempfootnotefromalltables
Page 10
Page 15
Page 1 & 15
Page 6
Corrected error in AC BUSYtiming tables changing 71V33 to 70121 and changing 71V43 to 70125
AddedIndustrialtempofferingto35nsorderinginformation
Replaced old TM logo with new TM logo
Footnotereference5removedfromACElectricalCharacteristicsREADtable
Changedwordingoffootnote1from"INT istotem-poleoutput"to"INTisnon-tr-statedpush-pulloutput"
Page 1
15
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
Page 5
Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns
04/05/06:
Page 1
Added green availability to features
Page 15
Page 15
Page 1
Added green indicator to ordering information
Removed "IDT" from orderable part number
Added green availability to Features
10/21/08:
08/05/14:
Page 15
Page 2 &15
Page 15
Page 1
Added green indicator to Ordering Information
The package code for the J52-1 changed to J52 to match standard package code
Added Tape and Reel to Ordering Information
Removed 45ns commercial speed grade from Features High-speed access
information
08/27/14:
Page 1-16
Page 4
Removed 45ns commercial speed grade throughout the datasheet to correct a discrepancy in
IDT's product catalog
Specifically including the DC Chars table
Page 6,8,10&12 Specifically including the AC Chars tables
Page 15 Removed 45ns commercial speed grade from the Ordering Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
16
6.42
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