7014S25JI [IDT]
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52;
| 型号： | 7014S25JI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7014S
HIGH-SPEED
4K x 9DUAL-PORT
STATIC RAM
Features:
◆
Description:
True Dual-Ported memory cells which allow simultaneous
TheIDT7014is ahigh-speed4Kx9Dual-PortStaticRAMdesigned
to be used in systems where on-chip hardware port arbitration is not
needed.Thispart lendsitselftohigh-speedapplicationswhichdonotrely
onBUSYsignalstomanagesimultaneousaccess.
TheIDT7014provides twoindependentports withseparatecontrol,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
readsorwritestoanylocationinmemory.Seefunctionaldescription.
The IDT7014 utilitizes a 9-bit wide data path to allow for parity at the
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
receptionerrorchecking.
reads of the same memory location
High-speed access
◆
– Commercial: 12/15/20/25ns (max.)
– Industrial:15/20/25ns(max.)
Standard-power operation
◆
– IDT7014S
Active: 750mW (typ.)
Fully asynchronous operation from either port
TTL-compatible; single 5V (±10%) power supply
Available in 52-pin PLCC and a 64-pin TQFP
◆
◆
◆
◆
Industrial temperature range (–40°C to +85°C) is available
Fabricated using IDT’s high-performance technology, these Dual-
Portstypicallyoperateononly750mWofpoweratmaximumaccesstimes
asfastas12ns.
for selected speeds
The IDT7014 is packaged in a 52-pin PLCC and a 64-pin thin quad
flatpack,(TQFP).
FunctionalBlockDiagram
W
R/
R
R/WL
OE
R
OEL
I/O
CONTROL
I/O
CONTROL
I/O0R- I/O8R
I/O0L- I/O8L
ADDRESS
DECODER
ADDRESS
DECODER
MEMORY
ARRAY
A0R- A11R
A0L- A11L
2528 drw 01
MARCH 2000
1
DSC 2528/13
©2000IntegratedDeviceTechnology,Inc.
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfiguration(1,2,3)
INDEX
7
6 5 4 3 2
5251 50 4948 47
A6L
A7L
1
46
45
44
43
42
41
40
39
38
37
36
35
34
8
9
A7R
A8R
A8L
9L
10
11
12
13
14
15
16
17
18
19
20
9R
A
A
A10R
A11R
A10L
A11L
IDT 7014J
J52-1(4)
OER
OE
L
GND
R/WR
VCC
R/WL
GND
I/O8L
I/O7L
52-Pin PLCC
Top View(5)
GND
I/O8R
I/O7R
I/O6R
I/O5R
I/O6L
21 22 23 24 2526 27 2829 30 31 32 33
,
2528 drw 02
INDEX
1
2
A6L
A7L
48
47
A6R
A7R
3
4
5
6
7
8
9
10
11
12
46
45
44
43
42
41
40
39
38
37
A8L
A9L
A8R
A9R
A10L
A11L
OEL
N/C
VCC
N/C
A10R
A11R
OER
N/C
GND
N/C
IDT7014PF
PN64-1(4)
64-Pin TQFP
Top View(5)
R/WL
N/C
R/WR
N/C
GND
I/O8L
I/O7L
I/O6L
13
14
15
36
35
34
33
GND
I/O8R
I/O7R
I/O6R
16
2528 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in. x .17 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking
2
IDT7014S/L
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1,2)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Commercial
Industrial
0OC to +70OC
0V
0V
5.0V + 10%
5.0V + 10%
-40OC to +85OC
(2)
VTERM
Terminal Voltage
-0.5 to +VCC
-55 to +125
V
2528 tbl 02
Temperature
Under Bias
oC
TBIAS
TSTG
IOUT
NOTES:
1. This is the parameter TA.
Storage
Temperature
-55 to +125
50
oC
DC Output
Current
mA
RecommendedDCOperating
Conditions
2528 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Symbol
Parameter
Min.
4.5
0
Typ.
Max. Unit
VCC
Supply Voltage
5.0
5.5
0
V
V
V
GND Ground
0
(2)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
6.0
(1)
____
-0.5
0.8
V
2528 tbl 03
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7014S
Symbol
|ILI|
Parameter
Input Leakage Current
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
Unit
µA
µA
V
___
10
10
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
VOUT = 0V to VCC
IOL = +4mA
VOL
0.4
___
VOH
IOH = -4mA
2.4
V
2528 tbl 04
NOTE:
1. At VCC < 2.0V input leakages are undefined.
3
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VCC = 5V ± 10%)
7014S12
Com'l Only
7014S15
Com'l & Ind
Symbol
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
Outputs Open
Version
COM'L
IND
Typ. Max
160 250
Typ.
160
160
Max Unit
ICC
mA
S
S
250
260
(1)
f = fMAX
____
____
2528 tbl 05a
7014S20
Com'l & Ind
7014S25
Com'l & Ind
Symbol
Parameter
Test Condition
Outputs Open
Version
Typ.
155
155
Max
Typ.
150
150
Max.
240
255
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
mA
COM'L
IND
S
S
245
260
(1)
f = fMAX
2528 tbl 05b
NOTES:
1. At f = fmax, address inputs are cycling at the maximum read cycle of 1/tRC using the "AC Test Conditions" input levels of GND to 3V.
5V
AC Test Conditions
5V
Input Pulse Levels
GND to 3.0V
3ns Max.
893Ω
893Ω
5pF*
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
DATAOUT
DATAOUT
1.5V
30pF
347Ω
347Ω
Figures 1,2 and 3
2528 tbl 06
2528 drw 04
2528 drw 05
Figure 1. AC Output Test Load.
Figure 2. Output Test Load
(for tHZ, tWZ, and tOW)
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Package Only
*Includingscopeandjig.
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
VIN = 3dV
Max. Unit
8
9
pF
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
7
6
COUT
VOUT = 3dV
10
pF
2528 tbl 07
NOTES:
5
4
3
tAA
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
swith from 0V to 3V or from 3V to 0V.
(Typical, ns)
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
,
2528 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
4
IDT7014S/L
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
7014S12
Com'l Only
7014S15
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
tAA
tAOE
tOH
tLZ
Read Cycle Time
12
15
ns
ns
ns
ns
ns
____
____
Address Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
12
15
____
____
8
8
____
____
3
3
____
____
3
3
Output High-Z Time(1,2)
7
7
ns
____
____
tHZ
2528 tbl 08a
7014S20
Com'l & Ind
7014S25
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
tAA
tAOE
tOH
tLZ
Read Cycle Time
20
25
ns
ns
ns
ns
ns
____
____
Address Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
20
25
____
____
10
12
____
____
3
3
____
____
3
3
Output High-Z Time(1,2)
9
11
ns
____
____
tHZ
2528 tbl 08b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization, but is not production tested.
5
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2528 drw 07
(1, 3)
Timing Waveform of Read Cycle No. 2, Either Side
tAOE
OE
tHZ
tLZ
VALID DATA
DATAOUT
2528 drw 08
NOTES:
1. R/W = VIH for Read Cycles.
2. OE = VIL.
3. Addresses valid prior to OE transition LOW.
Timing Waveform of Write with Port-to-Port Read(1,2)
tWC
ADDR"A"
MATCH
tWP
R/W
"A"
tDW
tDH
DATAIN "A"
ADDR"B"
VALID
MATCH
tWDD
DATAOUT "B"
VALID
tDDD
2528 drw 09
NOTES:
1. R/W"B" = VIH, read cycle pass through.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6
IDT7014S/L
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
7014S12
Com'l Only
7014S15
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tAW
tAS
Write Cycle Time
12
10
0
15
14
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
tWP
tWR
tDW
tHZ
10
1
12
1
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
8
10
____
____
7
7
____
____
tDH
0
0
(1,2)
____
____
tWZ
tOW
tWDD
tDDD
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,3)
Write Pulse to Data Delay(4)
7
7
____
____
0
0
____
____
25
22
30
25
Write Data Valid to Read Data Delay (4)
ns
____
____
2528 tbl 09a
7014S20
Com'l & Ind
7014S25
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tAW
tAS
Write Cycle Time
20
15
0
25
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
tWP
tWR
tDW
tHZ
15
2
20
2
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
12
15
____
____
9
11
____
____
tDH
0
0
(1,2)
____
____
tWZ
tOW
tWDD
tDDD
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,3)
Write Pulse to Data Delay(4)
9
11
____
____
0
0
____
____
40
30
45
35
Write Data Valid to Read Data Delay(4)
ns
____
____
2528 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”.
7
6.42
IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle(1,2,3,4,5)
ADDRESS
OE
AW
t
(5)
tAS
tWP
tWR
R/W
(4)
(4)
tWZ
tOW
tHZ
(3)
DATAOUT
(3)
tDW
tDH
DATAIN
2528 drw 10
NOTES:
1. R/W must be HIGH during all address transitions.
2. tWR is measured from R/W going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured 0mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
Truth Table I Read/Write Control
Left or Right Port(1)
FunctionalDescription
The IDT7014 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to
any location in memory. It lacks the chip enable feature of CMOS Dual
Ports,thusitoperatesinactivemodeassoonaspowerisapplied.Each
porthasitsownOutputEnablecontrol(OE).Inthereadmode,theport’s
OEturnsontheoutputdriverswhensetLOW. Theuserapplicationshould
avoidsimultaneouswriteoperationstothesamememorylocation.There
isnoon-chiparbitrationcircuitrytoresolvewritepriorityandpartialdata
frombothportsmaybewritten.READ/WRITEconditionsareillustrated
in Table 1.
R/W OE
D0-8
Function
L
H
X
X
L
DATAIN Data written into memory
DATAOUT Data in memory output on port
H
Z
High-impedance outputs
2528 tbl 10
NOTE:
1. AOL - A11L is not equal to AOR - A11R.
'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = HIGH Impedance.
8
IDT7014S/L
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT
999
A
A
XXXX
A
Device Type Power
Speed Package
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
I(1)
Industrial (-40°C to +85°C)
PF
J
64-pin TQFP (PN64-1)
52-pin PLCC (J52-1)
12
15
20
25
Commercial Only
,
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Speed in nanoseconds
S
Standard Power
7014 36K (4K x 9-Bit) Dual-Port RAM
2528 drw 11
DatasheetDocumentHistory
1/6/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Page2Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/3/99:
Page 1 Corrected DSC number
3/10/00:
AddedIndustrialTemperatureRangesanddeletedcorrespondingnotes
Replaced IDT logo
Page 1 Made corrections to drawing
Changed±200mVto0mVinnotes
Page 6made changes todrawings
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9
6.42
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7014S25PFG8
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64
IDT
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