7024S35PFB_技术文档

HIGH-SPEED

IDT7024S/L

4K x 16 DUAL-PORT

STATIC RAM

◆

IDT7024 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:20/25/35/55/70ns(max.)

– Industrial:55ns (max.)

◆

– Commercial:15/17/20/25/35/55ns(max.)

Low-power operation

◆

– IDT7024S

◆

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7024L

Active:750mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

bus compatibility

FunctionalBlockDiagram

R/WL

UBL

R/WR

UBR

LBL

CEL

OEL

R

CER

OER

LB

I/O8L-I/O15L

I/O8R-I/O15R

I/O

Control

I/O0L-I/O7L

0R

I/O -I/O

7R

(1,2)

BUSYL

(1,2)

BUSYR

A11R

A0R

A11L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0L

12

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CER

OER

CEL

OE

L

WR

R/

R/WL

SEMR

(2)

SEML

(2)

M/S

INTR

2740 drw 01

INTL

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

APRIL 2000

1

DSC 2740/10

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Description

port to enter a very low standby power mode.

The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The

IDT7024isdesignedtobeusedasastand-alone64K-bitDual-PortRAM

orasacombinationMASTER/SLAVEDual-PortRAMfor32-bitormore

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach

in32-bitorwidermemorysystemapplicationsresultsinfull-speed,error-

freeoperationwithouttheneedforadditionaldiscretelogic.

This device provides two independent ports with separate control,

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

reads or writes to any location in memory. An automatic power down

featurecontrolledbychipenable(CE)permitstheon-chipcircuitryofeach

FabricatedusingIDT’sCMOShigh-performancetechnology,these

devices typically operate on only 750mW of power. Low-power (L)

versionsofferbatterybackupdataretentioncapabilitywithtypicalpower

consumptionof500µWfroma2Vbattery.

TheIDT7024ispackagedinaceramic84-pinPGA,an84-pinFlatpack

andPLCC,anda100-pinTQFP.Militarygradeproductismanufactured

incompliancewiththelatestrevisionofMIL-PRF-38535QML,makingit

ideallysuitedtomilitarytemperatureapplicationsdemandingthehighest

levelofperformanceandreliability.

PinConfigurations^(1,2,3)

INDEX

11 10

9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

74

8L

9L

7L

6L

5L

4L

3L

2L

1L

0L

I/O

A

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

10L

11L

12L

13L

I/O

GND

IDT7024J or F

14L

15L

I/O

(4)

J84-1

F84-2

L

INT

(4)

L

CC

BUSY

GND

M/S

V

84-Pin PLCC / Flatpack

GND

(5)

Top View

0R

1R

2R

I/O

R

BUSY

R

INT

CC

V

0R

1R

2R

3R

4R

5R

6R

A

3R

4R

5R

6R

7R

8R

I/O

Index

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

,

2740 drw 02

10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

75

N/C

2

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

3

4

10L

I/O

11L

I/O

12L

I/O

13L

I/O

5

5L

A

4L

A

3L

A

2L

A

1L

A

0L

A

6

7

8

9

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

14L

I/O

IDT7024PF

15L

L

INT

(4)

PN100-1

CC

V

L

BUSY

GND

M/S

GND

100-Pin TQFP

0R

I/O

1R

I/O

2R

I/O

(5)

Top View

R

BUSY

R

INT

CC

V

0R

A

1R

A

2R

A

3R

A

4R

A

3R

I/O

4R

I/O

5R

I/O

6R

I/O

NOTES:

N/C

1. All V^CCpins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.

F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

2740 drw 03

PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

2

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

63

61

60

58

55

54

51

48

46

45

42

40

39

37

34

11

10

09

08

07

06

05

04

03

02

01

I/O^7L

I/O^5L

I/O^4L

I/O^2L

I/O^0L

L

A^11L

A^10L

A^7L

OE

SEM

LB

L

66

64

62

59

56

49

50

47

44

43

I/O^10L

I/O^8L

I/O^6L

I/O^3L

I/O^1L

N/C

A^9L

A^8L

A^5L

UBL

CEL

67

65

57

53

52

41

R/WL

GND

V

CC

I/O^11L

I/O^9L

A^6L

A^4L

69

68

38

I/O^13L

I/O^12L

A^3L

A^2L

72

71

73

33

35

15L

BUSYL

I/O

CC

V

A

0L

I/O^14L

INTL

IDT7024G

(4)

75

70

74

32

31

36

G84-3

I/O^0R

GND

M/S

GND

A^1L

84-Pin PGA

(5)

Top View

76

77

78

28

29

30

V^CC

I/O^1R

I/O

2R

A^0R

INTR

BUSYR

79

80

26

27

A^2R

I/O

3R

I/O^4R

A^1R

81

83

7

11

12

23

25

SEMR

I/O^5R

A^5R

I/O

7R

GND

A^3R

82

1

3

2

5

8

10

14

17

20

22

24

I/O^6R

I/O^9R

I/O^10R

I/O^13R

I/O^15R

R/WR

A^11R

A^8R

A^6R

A^4R

UBR

84

4

6

9

15

13

16

18

19

21

I/O^8R

I/O^11R

I/O^12R

I/O^14R

N/C

A^10R

A^9R

A^7R

OER

LBR

CER

A

B

C

D

E

F

G

H

J

K

L

2740 drw 04

Index

NOTES:

1. All V^CCpins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

PinNames

MaximumOperatingTemperature

andSupplyVoltage^(1,2)

Left Port

Right Port

Names

Grade

Ambient

Temperature

GND

Vcc

Chip Enable

CEL

CER

WL

WR

R/

Read/Write Enable

Output Enable

Address

+

Military

-55^OC to +125^OC

0^OC to +70^OC

0V

5.0V 10%

OEL

OER

+

5.0V 10%

Commercial

Industrial

0L

11L

0R

11R

A

- A

A

- A

-40^OC to +85^OC

5.0V 10%

+

0L

15L

0R

15R

I/O - I/O

SEML

UBL

I/O - I/O

SEMR

UBR

Data Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Interrupt Flag

2740 tbl 02

NOTES:

1. This is the parameter T^A.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

LBL

LBR

INTL

INTR

Busy Flag

BUSYL

BUSYR

S

M/

Master or Slave Select

Power

CC

V

GND

Ground

2740 tbl 01

6.42

3

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/W

X

L

I/O8-15

High-Z

DATAIN

High-Z

DATAIN

I/O0-7

High-Z

DATAIN

High-Z

DATAOUT

High-Z

Mode

CE

H

X

L

OE

X

L

UB

X

H

L

LB

X

H

L

SEM

H

Deselcted: Power-Down

Both Bytes Deselected

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

H

L

H

L

H

L

H

L

H

X

L

H

L

H

DATA_OUT

High-Z

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

L

H

L

H

L

H

DATAOUT

High-Z

X

H

X

Outputs Disabled

2740 tbl 03

NOTE:

1. A^0L— A11L ≠ A0R — A11R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs⁽¹⁾

Outputs

CE⁽²⁾

H

OE

L

UB

X

H

X

H

L

LB

X

H

X

H

X

L

SEM

L

R/W

H

↑

I/O8-15

I/O0-7

Mode

Read Semaphore Flag Data Out

Write I/O0 into Semaphore Flag

Write I/O₀into Semaphore Flag

Not Allowed

DATAOUT

DATAIN

DATAOUT

DATAIN

X

L

H

X

L

X

L

DATA

IN

↑

IN

____

L

X

L

____

L

X

L

Not Allowed

2740 tbl 04

NOTE:

1. There are eight semaphore flags written to via I/O⁰and read from all of the I/O's (I/O0 - I/O15).

These eight semaphores are addressed by A⁰- A2.

AbsoluteMaximumRatings⁽¹⁾

RecommendedDCOperating

Conditions

Symbol

Rating

Commercial

& Industrial

Military

Unit

Symbol

Parameter

Min.

4.5

0

Typ. Max. Unit

(2)

V^TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

V^CC

Supply Voltage

5.0

5.5

0

V

GND Ground

0

Temperature

Under Bias

-55 to +125

50

-65 to +135

-65 to +150

50

^oC

T^BIAS

T^STG

I^OUT

(2)

____

V^IH

V^IL

Input High Voltage

Input Low Voltage

2.2

6.0

(1)

____

-0.5

0.8

V

Storage

Temperature

2740 tbl 06

NOTES:

DC Output

Current

mA

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 10%.

2740 tbl 05

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. V^TERMmust not exceed Vcc +10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period over VTERM > Vcc + 10%.

6.42

4

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

(1)

Capacitance (TA = +25°C, f = 1.0MHz)

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions^{(2 )}

Max. Unit

C^IN

V^IN= 3dV

9

pF

C^OUT

V^OUT= 3dV

10

pF

2740 tbl 07

NOTES:

1. This parameter are determined by device characterization, but is not

production tested.

2. 3dV references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7024S

7024L

Symbol

Parameter

Input Leakage Curre nt⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

= 5.5V, V = 0V to V

Min.

Max.

10

Min.

Max.

Unit

µA

V

___

LI

|I |

CC

IN

CC

V

5

___

LO

|I

|

10

CE

IH OUT

= V , V = 0V to V

OL

V

OL

I

= +4mA

= -4mA

0.4

___

OH

V

OH

I

Output High Voltage

2.4

V

2740 tbl 08

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6)(VCC = 5.0V ± 10%)

7024X15

Com'l Only

7024X17

Com'l Only

7024X20

Com'l &

Military

7024X25

Com'l &

Military

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

I^CC

Dynamic Operating

Current

(Both Ports Active)

S

L

170

310

260

170

310

260

160

290

240

155

265

220

mA

CE = V^IL,

Outputs Open

SEM = V^IH

____

(3)

MIL &

IND

S

L

160

370

320

155

340

280

f = f^MAX

I^SB1

I^SB2

I^SB3

I^SB4

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

20

60

50

20

60

50

20

60

50

16

60

50

mA

CE^R= CE^L= V^IH

SEM^R= SEM^L= V^IH

(3)

f = f^MAX

____

MIL &

IND

S

L

20

90

70

16

80

65

(5)

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

105

190

160

105

190

160

95

180

150

90

170

140

CE^"A"= V^ILand CE^"B"= V^IH

Active Port Outputs Open,

(3)

f=f^MAX

____

MIL &

IND

S

L

95

240

210

90

215

180

SEM^R= SEM^L= V^IH

Full Standby Current

Both Ports CE^Land

CE^R> V^CC- 0.2V,

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

(Both Ports

-

CMOS Level Inputs)

V^IN> V^CC- 0.2V or

____

V^IN< 0.2V, f = 0⁽⁴⁾

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

SEM^R= SEM^L> V^CC- 0.2V

Full Standby Current

(One Port -

CMOS Level Inputs)

COM'L

S

L

100

170

140

100

170

140

90

155

130

85

145

120

CE^"A"< 0.2V and

(5)

CE^"B"> V^CC- 0.2V

SEM^R= SEM^L> V^CC- 0.2V

____

MIL &

IND

S

L

90

225

200

85

200

170

V^IN> V^CC- 0.2V or V^IN< 0.2V

Active Port Outputs Open,

(3)

MAX

f = f

2740 tbl 09a

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. V^CC= 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (TYP.)

3. At f = f^MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for specific speeds, packages and powers contact your sales office.

6.42

5

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6)(cont.) (VCC = 5.0V ± 10%)

7024X35

Com'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

____

mA

I^CC

Dynamic Operating

Current

(Both Ports Active)

S

L

150

250

210

150

250

210

CE = V^IL,

Outputs Open

SEM = V^IH

(3)

MIL &

IND

S

L

150

300

250

150

300

250

140

300

250

f = f^MAX

____

mA

I^SB1

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

S

L

13

60

50

13

60

50

CE^R= CE^L= V^IH

SEM^R= SEM^L= V^IH

(3)

f = f^MAX

MIL &

IND

S

L

13

80

65

13

80

65

10

80

65

____

(5)

I^SB2

Standby Current

(One Port - TTL

Level Inputs)

COM'L

S

L

85

155

130

95

155

130

CE^"A"= V^ILand CE^"B"= V^IH

Active Port Outputs Open,

(3)

f=f^MAX

MIL &

IND

S

L

85

190

160

95

190

160

80

190

160

SEM^R= SEM^L= V^IH

____

mA

I^SB3

Full Standby Current

(Both Ports -

Both Ports CE^Land

CE^R> V^CC- 0.2V,

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

CMOS Level Inputs)

V^IN> V^CC- 0.2V or

V^IN< 0.2V, f = 0⁽⁴⁾

SEM^R= SEM^L> V^CC- 0.2V

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

1.0

0.2

30

10

____

I^SB4

Full Standby Current

(One Port -

CMOS Level Inputs)

COM'L

S

L

80

135

110

80

135

110

CE^"A"< 0.2V and

(5)

CE^"B"> V^CC- 0.2V

SEM^R= SEM^L> V^CC- 0.2V

V^IN> V^CC- 0.2V or V^IN< 0.2V

Active Port Outputs Open,

MIL &

IND

S

L

80

175

150

80

175

150

75

175

150

(3)

f = f^MAX

2740 tbl 09b

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. V^CC= 5V, TA = +25°C, and are not production tested.

3. At f = f^MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for specific speeds, packages and powers contact your sales office.

Data Retention Characteristics Over All Temperature Ranges

(4)

(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)

Symbol

V^DR

I^CCDR

Parameter

V^CCfor Data Retention

Test Condition

Min.

Typ.⁽¹⁾

Max.

Unit

V

___

V^CC= 2V

2.0

___

Data Retention Current

µA

CE > V^HC

MIL. & IND.

COM'L.

100

4000

___

V^IN> V^HCor < V^LC

100

1500

(3)

___

t^CDR

Chip Deselect to Data Retention Time

Operation Recovery Time

0

ns

SEM > V^HC

(3)

(2)

___

t^R

t^RC

ns

2740 tbl 10

NOTES:

1. T^A= +25°C, VCC = 2V, and are by device characterization but are not production tested.

2. t^RC= Read Cycle Time

3. This parameter is guaranteed but not tested.

4. At Vcc < 2.0V, input leakages are not defined.

6.42

6

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Data Retention Waveform

DATA RETENTION MODE

VDR

≥

4.5V

tR

VCC

2V

tCDR

VDR

VIH

CE

2740 drw 05

AC Test Conditions

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

5ns

1.5V

Figures 1 and 2

2740 tbl 11

5V

1250

Ω

1250

Ω

DATA_OUT

BUSY

INT

DATA_OUT

30pF

775

Ω

5pF*

775

Ω

2740 drw 06

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for t^LZ, tHZ, tWZ, tOW)

*Including scope and Jig

6.42

7

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(4,5)

7024X15

Com'l Only

7024X17

Com'l Only

7024X20

Com'l &

Military

7024X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t^RC

Read Cycle Time

15

17

20

25

ns

____

t^AA

Address Access Time

15

17

20

25

Chip Enable Access Time⁽³⁾

____

tACE

t^ABE

t^AOE

t^OH

t^LZ

Byte Enable Access Time⁽³⁾

Output Enable Access Time

10

12

13

____

Output Hold from Address Change

Output Low-Z Time^(1,2)

3

____

3

Output High-Z Time^(1,2)

10

12

15

____

t^HZ

t^PU

t^PD

t^SOP

t^SAA

Chip Enable to Power Up Time^(1,2)

Chip Disable to Power Down Time^(1,2)

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access⁽³⁾

0

____

15

17

20

25

____

10

____

15

17

20

25

ns

2740 tbl 12a

7024X35

Com'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t^RC

Read Cycle Time

35

55

70

ns

____

t^AA

Address Access Time

35

55

70

Chip Enable Access Time⁽³⁾

Byte Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t^ACE

t^ABE

t^AOE

t^OH

t^LZ

20

30

35

____

3

____

3

Output High-Z Time^(1,2)

15

25

30

____

t^HZ

t^PU

t^PD

t^SOP

t^SAA

Chip Enable to Power Up Time^(1,2)

Chip Disable to Power Down Time^(1,2)

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access⁽³⁾

0

____

35

50

____

15

____

35

55

70

ns

2740 tbl 12b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^IL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL.

4. 'X' in part number indicates power rating (S or L).

5. Industrial temperature: for other speeds, packages and powers contact your sales office.

6.42

8

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

tAA

(4)

tACE

CE

(4)

tAOE

OE

(4)

tABE

UB, LB

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

2740 drw 07

tBDD

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. t^BDDdelay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has

no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^ABE, tAOE, tACE, tAA or tBDD.

5. SEM = V^IH.

Timing of Power-Up Power-Down

CE

t^PU

t^PD

ICC

I

SB

,

2740 drw 08

6.42

9

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage^(5,6)

7024X15

Com'l Only

7024X17

Com'l Only

7024X20

Com'l &

Military

7024X25

Com'l &

Military

Symbol

WRITE CYCLE

tWC

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

Write Cycle Time

15

12

0

17

12

0

20

15

0

25

20

0

ns

tEW

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

AW

t

tAS

tWP

12

0

12

0

15

0

20

0

tWR

tDW

tHZ

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

10

15

____

10

12

15

____

tDH

0

(1,2)

____

tWZ

tOW

tSWRD

tSPS

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

12

15

____

0

5

0

5

0

5

0

5

____

ns

2740 tbl 13a

7024X35

Com'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

tWC

tEW

tAW

tAS

Write Cycle Time

35

30

0

55

45

0

70

50

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

tWP

25

0

40

0

50

0

tWR

tDW

tHZ

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

15

30

40

____

15

25

30

____

tDH

0

(1,2)

____

tWZ

tOW

tSWRD

tSPS

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

15

25

30

____

0

5

0

5

0

5

____

Flag Write to Read Time

SEM

ns

SEM Flag Contention Window

2740 tbl 13b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^IL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.

Either condition must be valid for the entire t^EWtime.

4. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH

and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

6.42

10

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM ⁽⁹⁾

(9)

UB or LB

(3)

(2)

(6)

tWR

tWP

tAS

R/W

DATAOUT

DATAIN

(7)

tWZ

tOW

(4)

tDW

tDH

2740 drw 09

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing^(1,5)

t_WC

ADDRESS

t_AW

(9)

or

CE SEM

(3)

(2)

(6)

t_WR

t_EW

t_AS

(9)

or

UB LB

R/

W

t_DW

t_DH

DATA_IN

2740 drw 10

NOTES:

1. R/W or CE or UB & LB = V^IHduring all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = VIL to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW = V^ILtransition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.

7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load

(Figure 2).

8. If OE = V^ILduring R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t^DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified t^{WP .}

9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be

met for either condition.

6.42

11

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

t_OH

tSAA

A0-A2

VALID ADDRESS

tWR

tACE

tAW

tEW

SEM

tSOP

t_DW

DATAOUT

VALID⁽²⁾

DATAIN

VALID

I/O₀

tAS

tWP

t_DH

R/W

t_SWRD

t_AOE

OE

Write Cycle

Read Cycle

2740 drw 11

NOTES:

1. CE = V^IHor UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. “DATA^OUTVALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

0"A" 2"A"

A

-A

MATCH

SIDE⁽²⁾

"A"

R/W

"A"

SEM

tSPS

A0"B"-A2"B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

2740 drw 12

NOTES:

1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, semaphore flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W^Aor SEMA going HIGH to R/WB or SEMB going HIGH.

4. If t^SPSis not satisfied, there is no guarantee which side will obtain the semaphore flag.

6.42

12

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(6,7)

7024X15

Com'l Only

7024X17

Com'l Only

7024X20

Com'l &

Military

7024X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = V^IH)

____

t^BAA

t^BDA

t^BAC

t^BDC

t^APS

t^BDD

t^WH

15

17

20

ns

BUSY Access Time from Address Match

Disable Time from Address Not Match

BUSY

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

BUSY Disable to Valid Data⁽³⁾

15

17

____

5

____

18

30

Write Hold After BUSY⁽⁵⁾

12

13

15

17

____

BUSY INPUT TIMING (M/S = V^IH)

____

BUSY Input to Write⁽⁴⁾

t^WB

0

ns

t^WH

PORT-TO-PORT DELAY TIMING

t^WDD

t^DDD

Write Hold After BUSY⁽⁵⁾

12

13

15

17

(1)

____

Write Pulse to Data Delay

30

25

30

25

45

35

50

35

ns

Write Data Valid to Read Data Delay⁽¹⁾

ns

2740 tbl 14a

7024X35

Com'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = V^IH)

____

BAA

t

20

45

40

45

40

ns

BUSY Access Time from Address Match

t^BDA

t^BAC

t^BDC

t^APS

t^BDD

t^WH

BUSY Disable Time from Address Not Match

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

20

35

____

5

____

BUSY Disable to Valid Data⁽³⁾

Write Hold After BUSY⁽⁵⁾

35

40

45

____

25

BUSY INPUT TIMING (M/S = V^IH)

____

BUSY Input to Write⁽⁴⁾

t^WB

0

ns

t^WH

PORT-TO-PORT DELAY TIMING

t^WDD

t^DDD

Write Hold After BUSY⁽⁵⁾

25

(1)

____

Write Pulse to Data Delay

60

45

80

65

95

80

ns

Write Data Valid to Read Data Delay⁽¹⁾

ns

2740 tbl 14b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'.

5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'.

6. 'X' in part number indicates power rating (S or L).

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

6.42

13

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

TimingWaveformof WritewithPort-to-PortReadandBUSY^(2,4,5)(M/S = VIH)

t_WC

MATCH

ADDR_"A"

t_WP

R/

W"A"

t_DH

t_DW

VALID

DATA_{IN "A"}

(1)

t_APS

MATCH

ADDR_"B"

t_BAA

t_BDA

t_BDD

BUSY"B"

t_WDD

VALID

DATA_{OUT "B"}

(3)

t_DDD

2740 drw 13

NOTES:

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL.

3. OE = V^ILfor the reading port.

4. If M/S = V^IL(slave) then BUSY is an input BUSY"A" = VIL and BUSY"B" = don't care, for this example.

5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY

tWP

"A"

R/W

(3)

tWB

"B"

BUSY

(1)

tWH

,

(2)

R/ "B"

W

2740 drw 14

NOTES:

1. t^WHmust be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on port "B" Blocking R/W^"B", until BUSY"B" goes HIGH.

3. t^WBis only for the 'Slave' Version.

6.42

14

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR_"A"

ADDRESSES MATCH

and _"B"

CE"A"

(2)

t_APS

CE"B"

t_BAC

t_BDC

BUSY"B"

2740 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR_"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

t_APS

MATCHING ADDRESS "N"

t_BAA

t_BDA

2740 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(1,2)

7024X15

Com'l Only

7024X17

Com'l Only

7024X20

Com'l &

Military

7024X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t^AS

Address Set-up Time

0

ns

t^WR

t^INS

t^INR

Write Recovery Time

Interrupt Set Time

0

____

15

20

____

Interrupt Reset Time

ns

2740 tbl 15a

7024X35

Com'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t^AS

Address Set-up Time

0

ns

t^WR

t^INS

t^INR

Write Recovery Time

Interrupt Set Time

0

____

25

40

50

____

Interrupt Reset Time

ns

2740 tbl 15b

NOTES:

1. 'X' in part number indicates power rating (S or L).

2. Industrial temperature: for other speeds, packages and powers contact your sales office.

6.42

15

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

t_WC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR_"A"

(4)

(3)

t_AS

t_WR

CE"A"

R/ "A"

W

(3)

t_INS

INT"B"

2740 drw 17

t_RC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR_"B"

(3)

t_AS

CE"B"

"B"

OE

(3)

t_INR

"B"

INT

2740 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III Interrupt Flag^(1,4)

Left Port

Right Port

R/WL

L

A11L-A0L

FFF

X

R/WR

X

A11R-A0R

X

Function

CEL

L

OEL

X

INTL

X

CER

X

OER

X

INTR

(2)

L

Set Right INTR Flag

(3)

X

L

FFF

FFE

X

H

Reset Right INTR Flag

Set Left _INTLFlag

(3)

X

L

X

(2)

X

L

FFE

H

X

Reset Left INTL Flag

2740 tbl 16

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. INT^Rand INTL must be initialized at power-up.

6.42

16

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table IV

Address BUSY Arbritration

Inputs

Outputs

A^0L-A^11L

A^0R-A^11R

(1)

Function

Normal

CEL CER

BUSYL

BUSYR

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

(3)

MATCH

(2)

Write Inhibit

2740 tbl 17

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are

push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table V Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D⁰- D¹⁵Left

D⁰- D¹⁵Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2740 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.

2. There are eight semaphore flags written to via I/O0 and read from all the I/O's. These eight semaphores are addressed by A0-A2.

3. CE = V^IH, SEM = VIL, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.

FunctionalDescription

TheIDT7024providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

inmemory.TheIDT7024hasanautomaticpowerdownfeaturecontrolled

by CE. The CE controls on-chip power down circuitry that permits the

respectiveporttogointoastandbymodewhennotselected(CE=VIH).

Whenaportisenabled,accesstotheentirememoryarrayispermitted.

ormessagecenter)is assignedtoeachport. Theleftportinterruptflag

(INT^L) is asserted when the right port writes to memory location FFE

(HEX), whereawriteisdefinedastheCE=R/W=VILpertheTruthTable

III.TheleftportclearstheinterruptbyaccessaddresslocationFFEaccess

when CER = OER = VIL, R/W is a "don't care". Likewise, the right port

interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation

FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess

thememorylocationFFF. Themessage(16bits)atFFEorFFFisuser-

defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

6.42

17

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

isnotused,addresslocationsFFEandFFFarenotusedasmailboxes,

butaspartoftherandomaccessmemory.RefertoTruthTableIIIforthe

interruptoperation.

CE

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

BUSY (R)

BUSY (L)

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

BUSY (R)

BUSY (L) BUSY (R)

BUSY (L)

2740 drw 19

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7024 RAMs.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7024SRAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-PortRAMfeatures a fastaccess time, andbothports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslows theaccess timeoftherightport.Bothports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chippowerdowncircuitrythatpermits the respective porttogointo

standbymodewhennotselected.Thisistheconditionwhichisshownin

Truth Table I where CE and SEM = VIH.

SystemswhichcanbestusetheIDT7024containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

aperformanceincreaseofferedbytheIDT7024'shardwaresemaphores,

whichprovidealockoutmechanismwithoutrequiringcomplexprogram-

ming.

Softwarehandshakingbetweenprocessors offers themaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7024doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speedsystems.

Width Expansion with BUSY Logic

Master/SlaveArrays

WhenexpandinganIDT7024RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill

receiveaBUSYindication,andtooutputthatindication.Anynumberof

slaves to be addressed in the same address range as the master, use

theBUSYsignalasawriteinhibitsignal.ThusontheIDT7024RAMthe

BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and

theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown

in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onamaster,isbasedonthechipenableand

address signals only. Itignores whetheranaccess is a readorwrite. In

a master/slave array, bothaddress andchipenable mustbe validlong

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupteddataintheslave.

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

Semaphores

TheIDT7024isanextremelyfastDual-Port4Kx16CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

6.42

18

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

it. If it was successful, it proceeds to assume control over the shared

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe byeitherrepeatedreadsorbywritingaoneintothesamelocation.The

rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform into a semaphore flag. Whichever latch is first to present a zero to the

anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken, sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

theleftsideshouldsucceedingainingcontrol.

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

aonetothatlatch.

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

The eightsemaphore flags reside withinthe IDT7024ina separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

memoryspacefromtheDual-PortRAM.This addressspaceisaccessed is requestedandthe processorwhichrequesteditnolongerneeds the

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that

semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.

R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each

The critical case of semaphore timing is when both sides request

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside a single token by attempting to write a zero into it at the same time.

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof The semaphore logic is specially designed to resolve this problem.

theotheraddresspinshasanyeffect.

Ifsimultaneous requests are made, the logicguarantees thatonlyone

Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel sidereceivesthetoken.Ifonesideisearlierthantheotherinmakingthe

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero request, the firstside tomake the requestwillreceive the token. Ifboth

on that side and a one on the other side (see Truth Table III). That requestsarriveatthesametime,theassignmentwillbearbitrarilymade

semaphorecannowonlybemodifiedbythesideshowingthezero.When to one port or the other.

aoneiswrittenintothesamelocationfromthesameside,theflagwillbe

One caution that should be noted when using semaphores is that

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside semaphoresalonedonotguaranteethataccesstoaresourceissecure.

ispending)andthencanbewrittentobybothsides.Thefactthattheside Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites ormisinterpreted, a software errorcaneasilyhappen.

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

Initializationofthesemaphoresisnotautomaticandmustbehandled

communications.(Athoroughdiscussionontheuseofthisfeaturefollows viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis sidesshouldhaveaonewrittenintothematinitializationfrombothsides

freedbythefirstside.

to assure that they will be free when needed.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

UsingSemaphoresSomeExamples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

resourcemarkersfortheIDT7024’sDual-PortRAM.Saythe4Kx16RAM

was tobedividedintotwo2Kx16blocks whichweretobededicatedat

anyonetimetoservicingeithertheleftorrightport.Semaphore0could

be used to indicate the side which would control the lower section of

memory,andSemaphore1couldbedefinedastheindicatorfortheupper

sectionofmemory.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTruth

TableIII).Asanexample,assumeaprocessorwritesazerototheleftport

atafreesemaphorelocation.Onasubsequentread,theprocessorwill

verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol

overtheresourceinquestion.Meanwhile,ifaprocessorontherightside

attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

gap between the read and write cycles.

Totakearesource,inthis examplethelower2KofDual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread

backratherthana one), the leftprocessorwouldassume controlofthe

lower2K.Meanwhiletherightprocessorwasattemptingtogaincontrolof

theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse

tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the

softwarecouldchoosetotryandgaincontrolofthesecond2Ksectionby

writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining

control,itwouldlockouttheleftside.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo

itssemaphorerequestandperformothertasksuntilitwasabletowrite,then

6.42

19

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

readazerointoSemaphore1.Iftherightprocessorperformsasimilartask

Semaphoresarealsousefulinapplicationswherenomemory“WAIT”

withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap stateisavailableononeorbothsides.Onceasemaphorehandshakehas

2Kblocks ofDual-PortRAMwitheachother. been performed, both processors can access their assigned RAM

The blocks do not have to be any particular size and can even be segmentsatfullspeed.

variable, depending upon the complexity of the software using the

Anotherapplicationisintheareaofcomplexdatastructures. Inthis

semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

PortRAMorothersharedresources intoeightparts. Semaphores can mayberesponsibleforbuildingandupdatingadatastructure.Theother

evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

given a common meaning as was shown in the example above.

processorreadsanincompletedatastructure,amajorerrorconditionmay

Semaphores are a useful form of arbitration in systems like disk exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse itandthenisabletogoinandupdatethedatastructure.Whentheupdate

ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea is completed, the data structure block is released. This allows the

was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess interpretingprocessortocomebackandreadthecompletedatastructure,

theirassignedportionsofmemorycontinuouslywithoutanywaitstates. therebyguaranteeingaconsistentdatastructure.

L PORT

SEMAPHORE

R PORT

SEMAPHORE

REQUEST FLIP FLOP

0

D

0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

2740 drw 20

Figure 4. IDT7024 Semaphore Logic

6.42

20

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I

B

Commercial (0 C to +70 C)

° °

(1)

Industrial (-40 C to +85 C)

°

Military (-55 C to +125 C)

°

Compliant to MIL-PRF-38535 QML

100-pin TQFP (PN100-1)

84-pin PGA (G84-3)

PF

G

J

84-pin PLCC (J84-1)

F

84-pin Flatpack (F84-2)

15

17

20

25

35

55

70

Commercial Only

Commercial & Military

Commercial, Industrial & Military

Military Only

Speed in nanoseconds

S

L

Standard Power

Low Power

7024

64K (4K x 16) Dual-Port RAM

2740 drw 21

NOTE:

1. Industrial temperature range is available on selected PLCC packages in standard power.

For other speeds, packages and powers contact your sales office.

DatasheetDocumentHistory

1/13/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Pages2and3Addedadditionalnotestopinconfigurations

Changeddrawingformat

Page 1 Corrected DSC number

Replaced IDT logo

6/4/99:

4/4/00:

Page 6CorrectedtypoinData Retentionchart

Changed±500mVto0mVinnotes

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

831-754-4613

DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

21


型号：	7024S35PFB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual-Port SRAM, 4KX16, 35ns, CMOS, PQFP100, TQFP-100 静态存储器内存集成电路
文件：	总21页 (文件大小：190K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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