7034L15PFG [IDT]
HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM;
| 型号： | 7034L15PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7034S/L
HIGH-SPEED
4K x 18 DUAL-PORT
STATIC RAM
Features:
◆
True Dual-Ported memory cells which allow simultaneous
using the Master/Slave select when cascading more than
one device
reads of the same memory location
◆
◆
High-speed access
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆
◆
◆
Interrupt Flag
◆
Low-power operation
On-chip port arbitration logic
– IDT7034S
Full on-chip hardware support of semaphore signaling
between ports
Active:850mW(typ.)
Standby: 5mW (typ.)
– IDT7034L
◆
◆
◆
◆
◆
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Active:850mW(typ.)
Standby: 1mW (typ.)
◆
Separate upper-byte and lower-byte control for multi-
plexed bus compatibility
◆
◆
IDT7034 easily expands data bus width to 36 bits or more
Green parts available. See ordering information
Functional Block Diagram
R/WL
R/
W
R
UBL
UB
R
LB
CE
OE
L
L
L
LB
CE
OE
R
R
R
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
.
I/O
Control
I/O
Control
I/O0R-I/O8R
BUSY (1,2)
L
(1,2)
R
BUSY
A
11L
A
11R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
0R
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/
R
CE
OE
R/
L
R
L
W
R
WL
SEM
R
SEM
L
(2)
(2)
INTR
M/S
INTL
4089 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
JUNE 2015
1
DSC 4089/10
©2015 Integrated Device Technology, Inc.
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
forreadsorwritestoanylocationinmemory.Anautomaticpowerdown
featurecontrolledbyChipEnable(CE)permitstheon-chipcircuitryofeach
port to enter a very low standby power mode.
The IDT7034 is a high-speed 4K x 18 Dual-Port Static RAM. The
IDT7034 is designed to be used as a stand-alone 72K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit
or more word systems. Using the IDT MASTER/SLAVE Dual-Port
RAM approach in 36-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional
discrete logic.
The IDT7034 utilizes a 18-bit wide data path to allow for parity at
the user's option. This feature is especially useful in data communica-
tion applications.
Fabricated using CMOS high-performance technology, these de-
vicestypicallyoperateononly850mWofpower.Low-power(L)versions
offerbatterybackupdataretentioncapabilitywithtypicalpowerconsump-
tionof500µWfroma2Vbattery.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
PinConfigurations(1,2,3)
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
N/C
N/C
N/C
N/C
75
74
2
3
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
5
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
6
7
8
9
IDT7034PF
PN100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O15L
I/O16L
(4)
INT
L
VCC
BUSY
GND
M/S
L
100-PIN TQFP
GND
I/O0R
I/O1R
I/O2R
(5)
TOP VIEW
BUSY
R
.
INT
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
N/C
1R
2R
3R
4R
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4089drw 02
NOTES:
1. All VCC pins must be connected to power supply
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L - A11 L
I/O0L - I/O17L
SEM
UB
LB
INT
BUSY
A
0R - A11R
I/O0R - I/O17R
SEM
UB
LB
INT
BUSY
M/S
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
L
R
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power
V
CC
GND
Ground
4089 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
I/O9-17
High-Z
High-Z
DATAIN
High-Z
DATAIN
DATAOUT
High-Z
DATAOUT
High-Z
I/O0-8
High-Z
High-Z
High-Z
Mode
Deselected: Power-Down
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
X
H
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
L
H
L
L
H
L
H
DATAIN
DATAIN
High-Z
L
L
L
H
L
H
H
H
X
L
H
L
H
Read Upper Byte Only
L
L
H
L
H
DATAOUT Read Lower Byte Only
DATAOUT Read Both Bytes
L
L
L
H
X
H
X
X
X
High-Z
Outputs Disabled
4089 tbl 02
NOTE:
1. A0L — A11L ≠ A0R — A11R
3
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O9-17
I/O0-8
Mode
CE
H
OE
L
UB
X
LB
X
SEM
L
L
DATAOUT
DATAOUT
DATAOUT Read Data in Semaphore Flag
DATAOUT Read Data in Semaphore Flag
X
H
L
H
H
H
↑
X
X
X
L
DATAIN
DATAIN
Write I/O
0
into Semaphore Flag
into Semaphore Flag
X
L
L
↑
X
X
X
X
X
H
L
H
X
L
L
L
L
DATAIN
____
DATAIN
____
Write I/O
0
Not Allowed
Not Allowed
____
____
X
4089 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O17. These eight semaphores are addressed by A0 - A2.
Absolute Maximum Ratings(1)
Maximum Operating
1)
TemperatureandSupplyVoltage(
Symbol
Rating
Commercial
& Industrial
Unit
Ambient
(2)
Grade
Commercial
Temperature
GND
0V
Vcc
V
TE RM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
0OC to +70OC
5.0V
5.0V
+
+
10%
-40OC to +85OC
0V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
10%
4089 tbl 05
Industrial
T
BIAS
NOTES:
Storage
TSTG
1. This is the parameter TA. This is the "instant on" case temperature.
Temperature
DC Output
Current
mA
IOUT
4089 tbl 04
Recommended DC Operating
Conditions
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Supply Voltage
Min.
4.5
0
Typ.
5.0
0
Max. Unit
V
CC
5.5
0
V
V
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.
GND
Ground
6.0(2)
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
V
-0.5(1)
____
V
0.8
V
(1)
Capacitance (TA = +25°C, f = 1.0MHz)
4089 tbl 06
NOTES:
Conditions(2)
IN = 3dV
OUT = 3dV
Symbol
Parameter
Input Capacitance
Output Capacitance
Max. Unit
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
CIN
V
9
pF
COUT
V
10
pF
4089 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
4
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7034S
7034L
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
___
___
|ILI
|
V
CC = 5.5V, VIN = 0V to VCC
10
10
5
5
µA
µA
V
___
___
___
___
|ILO
|
CE = VIH, VOUT = 0V to VCC
OL = 4mA
OH = -4mA
V
OL
I
0.4
___
0.4
___
V
OH
Output High Voltage
I
2.4
2.4
V
4089 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7034X15
7034X20
Com'l Only
Com'l & Ind
Typ.(2)
Typ.(2)
Symbol
Parameter
Test Condition
Version
COM'L
Max.
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
L
170
170
310
260
160
290
mA
CE = V , Outputs Disabled
SEM = IVLIH
160
240
(3)
f = fMAX
____
____
____
____
IND
S
L
160
160
370
320
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
20
20
60
50
20
20
60
50
mA
mA
mA
mA
CE
L
= CE
R
= VIH
= VIH
SEM
R
= SEM
L
(3)
f = fMAX
____
____
____
____
S
L
20
20
90
70
(5)
ISB2
Standby Current
COM'L
IND
S
L
105
105
190
160
95
95
180
150
CE"A" = V and CE = VIH
Active PoIrLt Outputs"BD"isabled,
(One Port - TTL Level Inputs)
(3)
f=f
____
____
____
____
S
L
95
95
240
210
SEM
R
MAX = SEM
L
= VIH
ISB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE and
CE > V - 0L.2V
S
L
1.0
0.2
1.0
0.2
15
5
COM'L
IND
15
5
V
V
INR> VCCCC- 0.2V or
IN < 0.2V, f = 0(4)
____
____
____
____
S
L
1.0
0.2
30
10
SEM
R
= SEM > VCC - 0.2V
L
ISB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
COM'L
IND
S
L
100
100
170
140
90
90
155
130
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEM
R
= SEM > VCC - 0.2V
L
____
____
____
____
S
L
90
90
225
200
V
IN > VCC - 0.2V or V < 0.2V
Active Port Outputs DIiNsabled
(3)
f = fMAX
4089 tbl 09
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Data Retention Characteristics Over All Temperature Ranges
(4)
(L Version Only) (VCC = 0.2V, VHC = VCC - 0.2V)
Symbol
Parameter
Test Condition
Min.
2.0
___
Typ.(1)
___
Max.
___
Unit
V
V
DR
V
CC for Data Retention
V
CC = 2V
CE > VHC
IN > VHC or < VLC
SEM > VHC
ICCDR
Data Retention Current
µA
IND.
100
4000
___
V
COM'L.
100
1500
(3)
___
___
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
___
___
tR
tRC
ns
4089 tbl 10
NOTES:
1. TA = +25°C, VCC = 2V, not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
4. At Vcc < 2.0V input leakages are undefined.
Data Retention Waveform
DATA RETENTION MODE
VDR >
4.5V
4.5V
VCC
2V
tCDR
t
R
VDR
VIH
VIH
CE
4089 drw 03
AC Test Conditions
Input Pulse Levels
5V
5V
GND to 3.0V
5ns Max.
1.5V
Input Rise/Fall Times
893Ω
893Ω
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
1.5V
30pF
5pF*
347Ω
347Ω
Figures 1 and 2
4089 tbl 11
4
089 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*including scope and jig.
6
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
7034X15
Com'l Only
7034X20
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
____
20
____
ns
ns
ns
t
Address Access Time
15
15
15
20
20
20
____
____
Chip Enable Access Time(3)
t
____
____
____
____
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
t
ns
ns
ns
ns
t
10
____
12
____
t
3
3
____
____
Output Low-Z Time(1,2)
t
3
3
____
____
Output High-Z Time(1,2)
t
10
12
ns
ns
ns
ns
____
____
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
t
0
0
____
____
t
15
20
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
t
Semaphore Address Access Time
15
20
ns
4089 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
(1)
tOH
tLZ
DATAOUT
BUSYOUT
VALID DATA(4)
(2)
tHZ
(3,4)
4089 drw 05
t
BDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
7
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing of Power-up Power-down
CE
tPU
tPD
ICC
50%
50%
ISB
,
4089 drw 06
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7034X15
7034X20
Com'l Only
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
t
t
Address Set-up Time(3)
Write Pulse Width
t
____
____
____
____
____
____
t
12
0
15
0
t
Write Recovery Time
Data Valid to End-of-Write
t
10
15
____
____
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
12
____
____
t
0
0
ns
ns
ns
ns
(1,2)
____
____
t
10
12
Write Enable to Output in High-Z
____
____
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
4089 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire
tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
8
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
1,5,8)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
UB or LB (9)
R/W
(3)
(6)
(2)
tAS
tWR
tWP
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
4089 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM(9)
UB or LB(9)
(3)
(2)
(6)
AS
tWR
tEW
t
R/W
tDW
tDH
DATAIN
4089 drw 08
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met for either condition.
9
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveforme of Semaphore Read After Write Timing, Either Side(1)
tSAA
tOH
A0 - A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tSOP
tDW
OUT
DATA
DATAIN VALID
DATA
0
VALID(2)
tAS
tWP
tDH
R/W
tAOE
tSWRD
OE
tSOP
Write Cycle
Read Cycle
4089 drw 09
NOTE:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID' represents all I/Os (I/O0-I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
"B"
R/W"B"
SEM"B"
4089 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
10
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7034X15
Com'l Only
7034X20
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
15
17
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
18
30
ns
ns
____
____
(5)
t
12
15
Write Hold After BUSY
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
ns
ns
(5)
tWH
12
15
Write Hold After BUSY
PORT-TO-PORT DELAY TIMING
____
____
____
____
Write Pulse to Data Delay(1)
t
WDD
30
25
45
30
ns
Write Data Valid to Read Data Delay(1)
tDDD
ns
4089 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write With
Port-To-Port Delay (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part numbers indicates power rating (S or L).
11
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
VALID
(1)
t
APS
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
4089 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is an input. BUSY"A" = VIL and BUSY"B" = 'don't care'
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the opposite Port from Port "A".
Timing Waveform of Write with BUSY
tWP
R/W"A"
(3)
WB
t
BUSY"B"
(1)
t
WH
R/W"B"
.
(2)
4089 drw 12
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' Version.
12
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
4089 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1)(M/S = VIH)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
4089 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
7034X15
7034X20
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
____
0
____
t
15
15
20
20
____
____
t
Interrupt Reset Time
ns
4089 tbl 15
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
13
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
tAS
tWR
CE"A"
R/W"A"
INT"B"
(3)
tINS
4089 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
4089 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1)
Left Port
OE
Right Port
R/W
L
A
0L-A11L
FFF
X
R/W
R
A
0R-A11R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
L
INT
L
CE
R
OER
INTR
L
X
X
X
L
X
X
L
X
X
X
L
X
X
X
X
L
X
L
L
X
X
L
X
L(2)
H(3)
X
R
FFF
FFE
X
R
X
L(3)
H(2)
X
X
L
FFE
X
X
L
4089 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
14
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
-A
AOORL-A1111RL
Function
Normal
Normal
Normal
(1)
(1)
BUSY
L
BUSYR
CE
L
CER
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
Write Inhibit(3)
MATCH
(2)
(2)
4089 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7034 are push
pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left
D0
- D17 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
4089 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7034.
2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
FUNCTIONAL DESCRIPTION
flag (INTL) is asserted when the right port writes to memory location
FFE(HEX),whereawrite isdefinedastheCER =R/WR=VIL perTruth
Table III. The left port clears the interrupt by an address location FFE
access when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location FFF (HEX) and to clear the interrupt flag (INTR), the
right port must access the memory location FFF. The message (18
bits) at FFE or FFF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations FFE
and FFF are not used as mail boxes, but as part of the random access
memory. Refer to Table III for the interrupt operation.
The IDT7034 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT7034 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
15
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
BUSY LOGIC
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
togetheranduseanyBUSY indicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation. If the write inhibit function of
BUSY logicisnotdesirable, theBUSY logiccanbedisabledbyplacing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pinoperatessolelyasawriteinhibitinputpin. Normaloperationcanbe
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
BUSY (R)
BUSY (R)
BUSY (L)
BUSY (L)
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY (R)
BUSY (L) BUSY (R)
BUSY (R)
BUSY (L)
BUSY (L)
4089 drw 17
Figure 3. Busy and chip enable routing for both width and
depth expansion with IDT7034 RAMs.
other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on
the left port in no way slows the access time of the right port. Both ports
areidenticalinfunctiontostandardCMOSStaticRAMandcanberead
from, or written to, at the same time with the only possible conflict
arising from the simultaneous writing of, or a simultaneous READ/
WRITE of, a non-semaphore location. Semaphores are protected
against such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion of the
Dual-Port RAM. These devices have an automatic power-down fea-
ture controlled by CE, the Dual-Port RAM enable, and SEM, the
semaphoreenable. TheCEandSEMpinscontrolon-chippowerdown
circuitry that permits the respective port to go into standby mode when
notselected.ThisistheconditionwhichisshowninTruthTableIwhere
CE and SEM are both HIGH.
TheBUSYoutputsontheIDT7034RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7034 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT7034 RAM the BUSY pin is an output if the part is used as a master
(M/S pin = VIH), and the BUSY pin is an input if the part used as a slave
(M/S pin = VIL) as shown in Figure 3.
Systems which can best use the IDT7034 contain multiple proces-
sorsorcontrollersandaretypicallyveryhigh-speedsystemswhichare
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7034's hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicating BUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
system flexibility by permitting shared resources to be allocated in
varyingconfigurations. TheIDT7034doesnotuseitssemaphoreflags
to control any resources through hardware, thus allowing the system
designer total flexibility in system architecture.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/Wsignal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
SEMAPHORES
HOW THE SEMAPHORE FLAGS WORK
The IDT7034 is an extremely fast Dual-Port 4K x 18 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,
16
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
thestateofasemaphorelatchisusedasatokenindicatingthatshared subsequent read, the processor will verify that it has written success-
resource is in use. If the left processor wants to use this resource, it fully to that location and will assume control over the resource in
requests the token by setting the latch. This processor then verifies its question. Meanwhile, if a processor on the right side attempts to write
success in setting the latch by reading it. If it was successful, it a zero to the same semaphore flag it will fail, as will be verified by the
proceeds to assume control over the shared resource. If it was not factthataonewillbereadfromthatsemaphoreontherightsideduring
successful in setting the latch, it determines that the right side subsequent read. Had a sequence of READ/WRITE been used
processor has set the latch first, has the token and is using the shared instead, system contention problems could have occurred during the
resource. The left processor can then either repeatedly request that gap between the read and write cycles.
semaphore’s status or remove its request for that semaphore to
It is important to note that a failed semaphore request must be
perform another task and occasionally attempt again to gain control of followed by either repeated reads or by writing a one into the same
the token via the set and test sequence. Once the right side has location. The reason for this is easily understood by looking at the
relinquished the token, the left side should succeed in gaining control. simple logic diagram of the semaphore flag in Figure 4. Two sema-
The semaphore flags are active LOW. A token is requested by phore request latches feed into a semaphore flag. Whichever latch is
writing a zero into a semaphore latch and is released when the same first to present a zero to the semaphore flag will force its side of the
side writes a one to that latch.
semaphore flag LOW and the other side HIGH. This condition will
The eight semaphore flags reside within the IDT7034 in continue until a one is written to the same semaphore request latch.
a separate memory space from the Dual-Port RAM. This address Should the other side’s semaphore request latch have been written to
space is accessed by placing a LOW input on the SEM pin (which acts a zero in the meantime, the semaphore flag will flip over to the other
as a chip select for the semaphore flags) and using the other control side as soon as a one is written into the first side’s request latch. The
pins (Address, OE, and R/W) as they would be used in accessing a second side’s flag will now stay LOW until its semaphore request latch
standard Static RAM. Each of the flags has a unique address which is written to a one. From this it is easy to understand that, if a
can be accessed by either side through address pins A0 – A2. When semaphore is requested and the processor which requested it no
accessing the semaphores, none of the other address pins has any longer needs the resource, the entire system can hang up until a one
effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
level is written into an unused semaphore location, that flag will be set a single token by attempting to write a zero into it at the same time. The
to a zero on that side and a one on the other side (see Table V). That semaphore logic is specially designed to resolve this problem. If
semaphore can now only be modified by the side showing the zero. simultaneous requests are made, the logic guarantees that only one
When a one is written into the same location from the same side, the side receives the token. If one side is earlier than the other in making
flag will be set to a one for both sides (unless a semaphore request the request, the first side to make the request will receive the token. If
fromtheothersideispending)andthencanbewrittentobybothsides. bothrequestsarriveatthesametime, theassignmentwillbearbitrarily
The fact that the side which is able to write a zero into a semaphore made to one port or the other.
subsequently locks out writes from the other side is what makes
One caution that should be noted when using semaphores is that
semaphore flags useful in interprocessor communications. (A semaphores alone do not guarantee that access to a resource is
thorough discussion on the use of this feature follows shortly.) A zero secure. As with any powerful programming technique, if semaphores
written into the same location from the other side will be stored in the are misused or misinterpreted, a software error can easily happen.
semaphore request latch for that side until the semaphore is freed by
the first side.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
When a semaphore flag is read, its value is spread into all data bits phore request flag which contains a zero must be reset to a one, all
so that a flag that is a one reads as a one in all data bits and a flag semaphores on both sides should have a one written into them at
containing a zero reads as all zeros. The read value is latched into one initialization from both sides to assure that they will be free when
side’s output register when that side's semaphore select (SEM) and needed.
output enable (OE) signals go active. This serves to disallow the
USING SEMAPHORES—SOME EXAMPLES
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT7034’sDual-PortRAM.Saythe4K
x 18 RAM was to be divided into two 2K x 18 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of memory.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
Totakearesource, inthisexamplethelower2KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskwassuccessfullycompleted(azerowasread
back rather than a one), the left processor would assume control of the
17
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
lower2K.Meanwhiletherightprocessorwasattemptingtogaincontrol during a transfer and the I/O device cannot tolerate any wait states.
of the resource after the left processor, it would read back a one in With the use of semaphores, once the two devices has determined
responsetothezeroithadattemptedtowriteintoSemaphore0. Atthis which memory area was “off-limits” to the CPU, both the CPU and the
point, the software could choose to try and gain control of the second I/O devices could access their assigned portions of memory continu-
2K section by writing, then reading a zero into Semaphore 1. If it ously without any wait states.
succeeded in gaining control, it would lock out the left side.
Semaphores are also useful in applications where no memory
Once the left side was finished with its task, it would write a one to “WAIT” state is available on one or both sides. Once a semaphore
Semaphore 0 and may then try to gain access to Semaphore 1. If handshake has been performed, both processors can access their
Semaphore 1 was still occupied by the right side, the left side could assigned RAM segments at full speed.
undo its semaphore request and perform other tasks until it was able
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
to write, then read a zero into Semaphore 1. If the right processor case, block arbitration is very important. For this application one
performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe processor may be responsible for building and updating a data
two processors to swap 2K blocks of Dual-Port RAM with each other. structure. The other processor then reads and interprets that data
The blocks do not have to be any particular size and can even be structure. If the interpreting processor reads an incomplete data
variable, depending upon the complexity of the software using the structure, a major error condition may exist. Therefore, some sort of
semaphore flags. All eight semaphores could be used to divide the arbitration must be used between the two different processors. The
Dual-Port RAM or other shared resources into eight parts. Sema- building processor arbitrates for the block, locks it and then is able to
phores can even be assigned different meanings on different sides go in and update the data structure. When the update is completed,
rather than being given a common meaning as was shown in the the data structure block is released. This allows the interpreting
example above.
processortocomebackandreadthecompletedatastructure, thereby
Semaphores are a useful form of arbitration in systems like disk guaranteeing a consistent data structure.
interfaces where the CPU must be locked out of a section of memory
L PORT
SEMAPHORE
R PORT
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
.
4089 drw 18
Figure 4. IDT7034 Semaphore Logic
18
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
A
XXXXX
A
999
A
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
)
I(1
)
G(2
Green
PF
100-pin TQFP (PN100)
15
20
Commercial Only
Speed in nanoseconds
Commercial & Industrial
Standard Power
Low Power
S
L
7034
72K (4K x 18) Dual-Port RAM
4089 drw 19
NOTES:
1. Contactyour localsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
DatasheetDocumentHistory
12/3/98:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmetictypographicalcorrections
Addedadditionalnotestopinconfigurations
Page 9 Fixed typographical error
Changeddrawingformat
5/19/99:
6/3/99:
Page 1 Corrected DSC number
RemovedPreliminary
9/1/99:
10/4/99:
11/10/99:
5/22/00:
RemovedIndustrialTemperatureRangesandremovedcorrespondingnotes
Replaced IDT logo
Page 4 Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±500mVto0mVinnotes
01/29/09:
06/05/15::
Page 19 Removed "IDT" from orderable part number
Page 1 AddedGreenavailabilitytoFeatures
Page 2 RemovedIDTinreferencetofabrication
Page 2 & 19 The package code for PN100-1 changed to PN100 to match the standard package codes
Page 19 AddedGreenandT&RindicatorsandthecorrelatingfootnotestoOrderingInformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
19
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