70914S15JG [IDT]
Dual-Port SRAM, 4KX9, 15ns, CMOS, PQCC68, 0.950 X 0.950 X 0.170 INCH, GREEN, PLASTIC, LCC-68;
| 型号： | 70914S15JG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 4KX9, 15ns, CMOS, PQCC68, 0.950 X 0.950 X 0.170 INCH, GREEN, PLASTIC, LCC-68 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70914S
HIGH SPEED 36K (4K X 9)
SYNCHRONOUS
DUAL-PORT RAM
Features
◆
High-speed clock-to-data output times
– Fast 12ns clock to data out
– Military:20/25ns(max.)
– Commercial:12/15/20ns (max.)
– Self-timedwriteallowsfastcycletimes
– 16ns cycletimes,60MHzoperation
◆
◆
◆
◆
◆
◆
◆
Low-power operation
– IDT70914S
Active: 850 mW (typ.)
Standby: 50 mW (typ.)
Architecture based on Dual-Port RAM cells
– Allowsfullsimultaneousaccessfrombothports
Synchronous operation
– 4ns setup to clock, 1ns hold on all control, data, and address
inputs
– Data input, address, and control registers
TTL-compatible, single 5V (+ 10%) power supply
Clock Enable feature
Guaranteed data output hold times
Available in 68-pin PLCC, and 80-pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (-40°C to +85°C) is available
for selected speeds.
Recommended for replacement of IDT7099 (4K x 9) if
separate 9th bit data control signals are not required
Green parts available, see ordering information
◆
◆
◆
◆
FunctionalBlockDiagram
I/O0-8R
I/O0-8L
WRITE
WRITE
LOGIC
MEMORY
LOGIC
ARRAY
SENSE
AMPS
SENSE
AMPS
DECODER DECODER
REG
en
REG
en
OE
CLK
CLKEN
R
OE
CLK
CLKEN
L
L
R
L
R
Self-
Self-
timed
Write
Logic
timed
Write
Logic
R/W
L
REG
R/WR
REG
CEL
CE
R
A0L-A11L
A0R-A11R
3490 drw 01
MAY 2010
1
DSC-3490/8
©2010 IntegratedDeviceTechnology,Inc.
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
receptionerrorchecking.
TheIDT70914isahigh-speed4Kx9bitsynchronousDual-PortRAM.
The memory array is based on Dual-Port memory cells to allow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
providedbythisapproachallowsystemstobedesignedwithveryshort
cycletimes.Withaninputdataregister,thisdevicehasbeenoptimizedfor
applicationshavingunidirectionaldatafloworbi-directionaldataflowin
bursts.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
Dual-Ports typicallyoperateononly850mWofpoweratmaximumhigh-
speedclock-to-dataoutput times as fast as12ns.An automaticpower
down feature,controlledby CE,permitstheon-chipcircuitryofeachport
to enter a very low standby power mode.
The IDT70914 ispackaged ina68-pinPLCC,andan80-pinTQFP.
Militarygradeproductismanufacturedincompliancewiththelatestrevision
ofMIL-PRF-38535QML,makingitideallysuitedformilitarytemperature
applicationsdemandingthehighestlevelofperformanceandreliability.
TheIDT70914utilizesa9-bitwidedatapathtoallowforparityatthe
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
PinConfigurations(1,2,3)
INDEX
9
8
7
6
5
4
3
2
68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
A
A
A
A
A
OE
N/C
GND
GND
7R
8R
9R
10R
11R
A
A
A
A
6L
7L
8L
9L
1
A10L
R
A11L
OE
L
IDT70914J
J68-1(4)
N/C
VCC
68-Pin PLCC
Top View(5)
R/W
N/C
N/C
L
R/W
N/C
N/C
R
48 CE
47
R
CE
L
GND
I/O8L
I/O7L
I/O6L
GND
I/O8R
I/O7R
I/O6R
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
,
3490 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3) (con't.)
Reference
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
N/C
1
2
60
N/C
59
A
A
A
A
6L
7L
8L
9L
A
A
A
7R
8R
9R
3
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
4
5
A
10R
6
A
10L
11L
A11R
7
A
N/C
IDT70914PF
PN80-1(4)
8
N/C
OE
N/C
OE
R
9
L
N/C
10
11
12
13
14
15
16
17
18
19
20
GND
80-Pin TQFP
Top View(5)
V
CC
GND
R/W
L
R/W
N/C
N/C
R
N/C
N/C
CE
L
CER
GND
I/O8L
I/O7L
I/O6L
N/C
GND
I/O8R
I/O7R
I/O6R
N/C
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
,
3490 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.432
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1,2)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Grade
Ambient
GND
VCC
(2)
Temperature
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
-55OC to+125OC
0OC to +70OC
0V
0V
0V
5.0V
5.0V
5.0V
+
+
+
10%
10%
(2)
Commercial
Industrial
VTERM
Terminal Voltage
-0.5 to VCC
-55 to +125
-0.5 to VCC
-65 to +135
V
-40OC to +85OC
10%
Temperature
Under Bias
oC
TBIAS
TSTG
IOUT
3490 tbl 02
NOTES:
Storage
Temperature
-65 to +150
50
-65 to +150
50
oC
1. This is the parameter TA. This is the "instant on" casae temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
DC Output
Current
mA
3490 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
RecommendedDCOperating
Conditions
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
VCC
4.5
5.0
5.5
0
V
V
V
0
0
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
Capacitance
-0.5(1)
V
____
VIL
(TA = +25°C, f = 1.0MHz) TQFP Only
3490 tbl 03
NOTES:
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VCC + 10%.
CIN
V
8
9
pF
COUT
V
pF
3490 tbl 04
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70914S
Symbol
Parameter
Test Conditions
CC = 5.5V, VIN = 0V to VCC
Min.
Max.
Unit
(1)
___
Input Leakage Current
|ILI|
V
10
10
µA
µA
V
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
CE = VIH, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
VOL
I
0.4
___
VOH
I
2.4
V
3490 tbl 05
NOTE:
1. At VCC < 2.0V, input leakages are undefined
6.42
4
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(4,5) (VCC = 5V ± 10%)
70914S12
70914S15
Com'l Only
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
190
310
180
300
mA
CE
L
and CER = VIL,
Outputs Disabled
____
____
____
____
(1)
MIL &
IND
f = fMAX
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
95
150
90
140
mA
mA
CE
L
and CER = VIH
(1)
f = fMAX
____
____
____
____
MIL &
IND
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
170
220
160
210
CE"A" = VIL and
(3)
CE"B" = VIH
____
____
____
____
MIL &
IND
Active Port Outputs
(1)
Disabled, f=fMAX
I
SB3
Full Standby
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
R
and
mA
mA
COM'L
10
15
10
15
Current (Both
Ports - All CMOS
Level Inputs)
L
____
____
____
____
V
V
MIL &
IND
ISB4
Full Standby
Current (One
Port - All CMOS
Level Inputs)
COM'L
165
210
155
200
CE"A" < 0.2V and
(3)
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or
____
____
____
____
MIL &
IND
V
IN < 0.2V, Active Port
Outputs Disabled
(1)
f = fMAX
3490 tbl 06a
70914S20
Com'l &
Military
70914S25
Military
Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
290
310
Typ.(2)
Max.
Unit
____
____
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
170
170
mA
CE
L
and CER = VIL,
Outputs Disabled
(1)
MIL &
IND
160
290
f = fMAX
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
85
85
130
140
mA
mA
mA
mA
CE
L
and CER = VIH
(1)
f = fMAX
MIL &
IND
80
130
____
____
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
150
150
200
210
CE = VIL and
CE"AB" = VIH
(3)
MIL &
IND
140
200
Active Port Outputs
(1)
Disabled, f=fMAX
____
____
ISB3
Full Standby
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
R and
COM'L
10
10
15
20
Current (Both
Ports - All CMOS
Level Inputs)
L
MIL &
IND
10
20
V
V
____
____
ISB4
Full Standby
Current (One
Port - All CMOS
Level Inputs)
COM'L
145
145
190
200
CE"A" < 0.2V and
(3)
CE"B" > VCC - 0.2V
V
IN > VCC - 0.2V or
MIL &
IND
135
190
V
IN < 0.2V, Active Port
Outputs Disabled
(1)
f = fMAX
3490 tbl 06b
NOTES:
1. At fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels
of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.452
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3490 tbl 07
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
3490 drw 05
3490 drw 06
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
- 9pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
5
∆tCD
(Typical, ns)
4
3
2
1
0
,
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
3490 drw 07
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
6
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
70914S12
Com'l Only
70914S15
Com'l Only
Symbol
Parameter
Min.
16
Max.
Min.
20
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
t
CY C
CH
CL
CD
Clock Cycle Time
t
Clock High Time
6
6
t
Clock Low Time
6
6
____
____
t
Clock High to Output Valid
Registered Signal Set-up Time
Registered Signal Hold Time
Data Output Hold After Clock High
12
15
____
____
tS
4
1
3
4
1
3
____
____
____
____
____
____
tH
t
DC
CKLZ
CKHZ
OE
OLZ
OHZ
SCK
HCK
(1,2)
t
Clock High to Output Low-Z
2
2
(1,2)
____
____
t
Clock High to Output High-Z
7
7
____
____
t
Output Enable to Output Valid
7
8
(1,2)
____
____
t
Output Enable to Output Low-Z
0
0
(1,2)
____
____
t
Output Disable to Output High-Z
7
7
____
____
t
Clock Enable, Disable Set-up Time
Clock Enable, Disable Hold Time
4
2
4
2
____
____
t
Port-to-Port Delay
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
25
13
30
15
ns
t
CS S
ns
3490 tbl 08a
70914S20
Com'l &
Military
70914S25
Military
Only
Symbol
Parameter
Min.
20
Max.
Min.
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
CY C
CH
CL
CD
Clock Cycle Time
____
____
t
Clock High Time
8
10
t
Clock Low Time
8
10
____
____
t
Clock High to Output Valid
Registered Signal Set-up Time
Registered Signal Hold Time
Data Output Hold After Clock High
20
25
____
____
tS
5
1
3
6
1
3
____
____
____
____
____
____
tH
t
DC
CKLZ
CKHZ
OE
OLZ
OHZ
SCK
HCK
(1,2)
t
Clock High to Output Low-Z
2
2
(1,2)
____
____
t
Clock High to Output High-Z
9
12
____
____
t
Output Enable to Output Valid
10
12
(1,2)
____
____
t
Output Enable to Output Low-Z
0
0
(1,2)
____
____
t
Output Disable to Output High-Z
9
11
____
____
t
Clock Enable, Disable Set-up Time
Clock Enable, Disable Hold Time
5
2
6
2
____
____
t
Port-to-Port Delay
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
35
15
45
20
ns
t
CS S
ns
3490 tbl 08b
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.472
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle, Either Side
tCYC
t
CH
tCL
CLK
tSCK
t
SCK
t
HCK
CLKEN
tS
t
H
CE
R/W
ADDRESS
DATAOUT
An
An + 1
An + 2
An + 3
(1)
t
DC
t
CKHZ
t
CD
Qn
Qn + 1
Qn + 1
(1)
tCKLZ
(1)
(1)
t
OHZ
t
OLZ
t
OE
OE
3490 drw 08
Timing Waveform of Write with Port-to-Port Read(2,3,4)
CLK "A"
R/W "A"
NO
MATCH
ADDR "A"
DATA IN "A"
CLK "B"
MATCH
VALID
(5)
t
CCS
tCD
R/W "B"
NO
MATCH
ADDR "B"
MATCH
tCWDD
tCD
DATA OUT "B"
VALID
VALID
t
DC
3490 drw 09
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CEL = CER = VIL, CLKENL = CLKENR = VIL.
3. OE = VIL for the reading port, port 'B'.
4. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A".
5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD. tCWDD does not apply in this case.
6.42
8
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read-to-Write Cycle No. 1(1,2) (tCYC = min.)
tCYC
tCYC
tCH
tCL
tCH
tCL
CLK
CLKEN
CE
tS
tH
(1)
R/W
An + 1(1)
ADDRESS
DATAIN
An
An + 1
An + 2
Dn + 2
(1)
Dn + 1
(3)
tCD
tCKHZ
DATAOUT
Qn
(3)
tCKLZ
3490 drw 10
Timing Waveform of Read-to-Write Cycle No. 2(4) (tCYC > min.)
(4)
tCYC
tCH
tCL
CLK
CLKEN
CE
tS
tH
R/W
ADDRESS
DATAIN
An
An + 1
Dn + 1
tCD
DATAOUT
Qn
(3)
t
CKLZ
tOHZ
OE
3490 drw 11
NOTES:
1. For tCYC = min.; data out coincident with the rising edge of the subsequent write clock can occur. To ensure writing to the correct address location, the write must
be repeated on the second write clock rising edge. If CE = VIL, invalid data will be written into array. The An+1 must be rewritten on the following cycle.
2. OE LOW throughout.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. For tCYC > min.; OE may be used to avoid data out coincident with the rising edge of the subsequent write clock. Use of OE will eliminate the need for the write to
be repeated.
6.492
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
FunctionalDescription
transitionsoftheclocksignalallowingtheshortestpossiblerealizedcycle
times.Clockenableinputsareprovidedtostalltheoperationoftheaddress
and data input registers without introducing clock skew for very fast
interleavedmemoryapplications.
A HIGH on the CE input for one clock cycle will power down the
internalcircuitrytoreducestaticpowerconsumption.
The IDT70914 provides a true synchronous Dual-Port Static RAM
interface.Registeredinputsprovideveryshortset-upandholdtimeson
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclock signal.Anasynchronousoutputenableis
providedtoeaseasynchronousbusinterfacing.
The internal write pulse width is dependent on the LOW to HIGH
Truth Table I: Read/Write Control(1)
Inputs
Outputs
Synchronous(3)
Asynchronous
Mode
CLK
R/W
I/O0-8
High-Z
DATAIN
DATAOUT
High-Z
CE
H
L
OE
X
X
L
X
L
Deselected, Power-Down
↑
↑
↑
↑
Selected and Write Enabled
Read Selected and Data Output Enable Read
Outputs Disabled
L
H
X
X
H
3490 tbl 09
Truth Table II: Clock Enable Function Table(1)
Inputs
Register Inputs
Register Outputs(4)
ADDR DATAOUT
(3)
CLKEN(2)
Mode
CLK
ADDR
H
DATAIN
Load "1"
Load "0"
L
L
H
L
H
L
H
L
↑
↑
↑
X
L
H
H
X
X
X
NC
NC
NC
NC
Hold (do nothing)
X
3490 tbl 10
NOTES:
1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW
voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = VIL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on
the LOW-to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK.
4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
6.42
10
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
A
XXXXX
99
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +85°C)
Blank
)
I(1
B
Compliant to MIL-PRF-38535 QML
)
G(2
Green
68-pin PLCC (J68-1)
80-pin TQFP (PN80-1)
J
PF
Commercial Only
Commercial Only
Commercial & Military
Military Only
12
15
20
25
Speed in nanoseconds
Standard Power
S
70914
36K (4K x 9-Bit) Synchronous Dual-Port RAM
3490 drw 12
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power. For specific speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
3/10/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Page2and3Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/7/99:
11/10/99:
5/24/00:
Replaced IDT logo
Page 4 Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
1/12/01:
RemovedPGApinout(obsoletepackage)
Changedcycle time of12ns partfrom17ns (58MHz)to16ns (60MHz)
Page 11 Removed "IDT" from orderable part number
Page 1 Addedgreenpartsavailabilitytofeatures
Page 11 Addedgreenindicatortoorderinginformation
10/21/08:
05/24/10:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.1412
相关型号：
70914S20JG
Dual-Port SRAM, 4KX9, 20ns, CMOS, PQCC68, 0.950 X 0.950 X 0.170 INCH, GREEN, PLASTIC, LCC-68
IDT
70914S25JB
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 1.27 MM PITCH, PLASTIC, LCC-68
IDT
70914S25JGB
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC68, 0.950 X 0.950 X 0.170 INCH, GREEN, PLASTIC, LCC-68
IDT
©2020 ICPDF网 联系我们和版权申明