70T653MS10BCGI8 [IDT]
HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM;
| 型号： | 70T653MS10BCGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| 文件： | 总24页 (文件大小：705K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 2.5V
512K x 36
IDT70T653M
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
Features
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
Full on-chip hardware support of semaphore signaling
between ports
◆
◆
◆
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
– Commercial:10/12/15ns(max.)
– Industrial: 12ns (max.)
◆
◆
◆
◆
◆
◆
RapidWrite Mode simplifies high-speed consecutive write
cycles
Sleep Mode Inputs on both ports
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Includes JTAG functionality
Dual chip enables allow for depth expansion without
external logic
◆
◆
◆
IDT70T653M easily expands data bus width to 72 bits or
more using the Busy Input when cascading more than one
device
Available in a 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
Busy input for port contention management
Interrupt Flags
◆
Green parts available, see ordering information
Functional Block Diagram
BE3L
BE3R
BE2R
BE2L
BE1L
BE0L
BE1R
BE0R
R/
WL
R/
WR
B B B B B B B B
E E E E E E E E
0
L
1
L
2
L
3
L
3 2 1 0
R R R R
CE0L
CE1L
CE0R
CE1R
OEL
OE
R
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout18-26_L
Dout27-35_L
512K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Di n_L
Di n_R
I/O0R -I/O35R
A
18R
0R
A
18L
0L
Address
Decoder
Address
Decoder
ADDR_L
ADDR_R
A
A
CE0L
CE1L
ARBITRATION
CE0R
CE1R
TDI
TCK
TMS
TRST
INTERRUPT
SEMAPHORE
LOGIC
JTAG
TDO
OE
L
OE
R
R/W
L
R/W
R
BUSY
SEM
L
BUSY
SEM
R
L
R
(1)
(1)
INTL
INT
R
ZZ
(2)
(2)
ZZR
CONTROL
LOGIC
ZZL
NOTES:
1. INT is non-tri-state totem-pole outputs (push-pull).
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode
5679 drw 01
pins themselves (ZZx) are not affected during sleep mode.
JUNE 2015
1
DSC-5679/6
©2015 Integrated Device Technology, Inc.
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70T653M is a high-speed 512K x 36 Asynchronous Dual-
Port Static RAM. The IDT70T653M is designed to be used as a stand-
alone18874K-bitDual-PortRAM.Thisdeviceprovidestwoindependent
portswithseparatecontrol,address,andI/Opinsthatpermitindependent,
asynchronousaccessforreadsorwritestoanylocationinmemory. An
automaticpowerdownfeaturecontrolledbythe chipenables(eitherCE0
orCE1)permittheon-chipcircuitryofeachporttoenteraverylowstandby
power mode.
TheIDT70T653MhasaRapidWriteModewhichallowsthedesigner
toperformback-to-backwriteoperationswithoutpulsingtheR/Winput
each cycle. This is especially significant at the 10ns cycle time of the
IDT70T653M,easingdesignconsiderationsatthesehighperformance
levels.
The70T653Mcansupportanoperatingvoltageofeither3.3Vor2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) is at 2.5V.
2
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfiguration(1,2,3)
70T653M BC
BC-256(4,5)
256-Pin BGA
Top View
A1
A2
A3
A6
A7
A8L
A8
A9
A11
A12
A5L
A13
A2L
A14
A0L
A4
A5
A10
A15
A16
NC
TDI
NC
A11L
BE2L CE1L
INTL
A17L A14L
OEL
NC
NC
B1
B2
B3
B6
B7
A9L
B9
CE0L
B11
B12
A4L
B13
A1L
B4
B5
A15L
B8
B10
B14
B15
B16
I/O18L NC TDO
A12L
NC
A18L
BE3L
R/WL
NC I/O17L NC
C1
C5
A13L
C6
C2
C3
C4
A16L
C7
A7L
C8
C9
C10
C11
C12
A6L
C13
A3L
C16
C14
C15
I/O18R
A10L
I/O19L VSS
BE1L BE0L SEML BUSY
L
I/O16L
OPTL I/O17R
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
VDDQL
VDDQL
VDDQR
VDDQR VDD I/O15R I/O15L I/O16R
I/O20L
VDDQL
VDDQR VDDQR
VDDQL
VDD
E5
E6
E7
VSS
E8
VSS
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
VDD
VDD
VSS
VSS
VDD
VDD VDDQR
I/O21R I/O21L I/O22L VDDQL
I/O13L
I/O14R
I/O14L
F7
VSS
F5
F6
F9
F10
F1
F2
F3
F11
F13
F14
F15
F16
F8
VSS
F12
VDD
F4
I/O23L I/O22R I/O23R
VDD
NC
VSS
VSS
I/O12R I/O13R I/O12L
VDDQR
VSS
VDDQL
G1
G2
G3
G5
G4
G6
G8
VSS
G9
G14
G15
G16
G7
VSS
G10
G12
VSS
G13
G11
I/O24R
VSS
I/O24L
VDDQR
VSS
VSS
I/O25L
I/O10L I/O11L I/O11R
VSS
VDDQL
VSS
H11
H12
H16
H13
H7
VSS
H8
VSS
H9
H10
H14
H15
H5
H6
H3
H4
H1
H2
VSS
VSS VDDQL
I/O9R IO9L
I/O10R
J16
VSS
VSS
I/O26R VDDQR VSS
VSS
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
VSS
J8
VSS
J9
J13
J10
J11
J12
J14
J15
I/O27L
ZZR
I/O28R I/O27R VDDQL
VSS
VSS
VDDQR
VSS
VSS
ZZL
I/O8R
I/O7R I/O8L
K6
K8
VSS
K10
K12
VSS
K13
K2
K4
K5
K7
VSS
K9
K11
K15
K16
K1
K3
K14
VSS
VSS
VDDQR
I/O29L
VDDQL VSS
VSS
VSS
I/O6L I/O7L
I/O29R
I/O28L
I/O6R
L7
VSS
L8
VSS
L11
L12
VDD
L13
L5
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
VSS
VDDQL
I/O30R VDDQR VDD
NC
VSS
VSS
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
VSS
M8
VSS
M9
M10
M11
M12
VDD
M13
M1 M2
M3
M4
M16
M14
M15
VDD
N5
VDD
VSS
VSS
VDD
VDDQL
I/O32R I/O32L I/O31L VDDQR
I/O4L
I/O3R I/O3L
N8
N12
N13
N16
N6
N7
N9
N10
N11
N4
N15
N1
N2
N3
N14
VDDQL
VDDQL
I/O2R
I/O1R
VDD
VDD VDDQR VDDQR VDDQL
VDDQR VDDQR VDDQL
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9 P10 P11
P12
P14
P15
P16
P6
A10R
P13
I/O35R I/O34L TMS A16R A13R
A7R BE1R BE0R SEMR BUSY
R
A6R
I/O0L I/O0R I/O1L
A3R
R5
R6
R7
A9R
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
A15R A12R
BE3R CE0R R/WR VSS
NC
I/O35L NC TRST A18R
A4R
A1R OPTR
NC
T2
T3
T4
A17R
T1
T5
A14R
T8
T9
T15
T16
T6
A11R
T7
A8R
T10
T11
T12
T13
A2R
T14
A0R
TCK
NC
NC
BE2R CE1R
NC
NC
OER INTR
A5R
5679 drw 02f
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
3
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R CE1R
R/W
OE
Names
Chip Enables (Input)
CE0L
R/W
OE
,
CE1L
,
L
R
Read/Write Enable (Input)
Output Enable (Input)
L
R
A
0L - A18L
I/O0L - I/O35L
SEM
INT
BUSY
BE0L - BE3L
A
0R - A18R
I/O0R - I/O35R
SEM
INT
BUSY
BE0R - BE3R
Address (Input)
Data Input/Output
Semaphore Enable (Input)
Interrupt Flag (Output)
Busy Input
L
R
L
R
L
R
Byte Enables (9-bit bytes) (Input)
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode Pin(3) (Input)
Power (2.5V)(1) (Input)
V
DDQL
V
DDQR
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
OPT
L
OPTR
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
ZZL
ZZR
V
V
DD
SS
Ground (0V) (Input)
TDI
TDO
TCK
Test Data Input
3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not
affected during sleep mode. It is recommended that boundry scan not be operated
during sleep mode.
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
TMS
TRST
Reset (Initialize TAP Controller) (Input)
5679 tbl 01
4
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2)
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CE
X
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
SEM CE
0
BE
X
X
H
H
H
H
L
3
BE
X
X
H
H
H
L
2
BE
X
X
H
H
L
1
BE
X
X
H
L
0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
DIN
Write to Byte 0 Only
H
H
H
L
L
D
IN
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
H
H
L
L
D
IN
High-Z
High-Z
H
H
L
L
D
IN
High-Z
High-Z
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
H
L
H
L
L
DIN
DIN
High-Z
High-Z Write to Upper 2 bytes Only
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
Read Byte 0 Only
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
L
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
H
H
L
DOUT
High-Z
High-Z
L
H
H
L
DOUT
High-Z
High-Z
L
H
L
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
L
H
L
H
L
DOUT
DOUT
High-Z
L
L
L
DOUT
DOUT
DOUT
DOUT
H
X
L
L
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Outputs Disabled
High-Z High-Z Sleep Mode
X
X
X
X
5679 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
I/O
R/W
H
I/O118--82,6
I/O
0
Mode
CE(2)
H
OE
L
BE
X
3
BE
2
BE
X
1
BE
L
0
SEM
L
X
X
L
L
L
DATAOUT
DATAOUT Read Data in Semaphore Flag(3)
↑
H
X
X
X
L
X
______
DATAIN
______
Write I/O
0 into Semaphore Flag
L
X
X
X
X
X
Not Allowed
5679 tbl 03
NOTES:
1. There are eight semaphore flags written to I/O0 and read from the I/Os (I/O0-I/O08 and I/O18-I/O26). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective BEn. To read data BEn = VIL.
5
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage(1)
Ambient
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
2.4
0
Typ.
2.5
2.5
0
Max.
2.6
2.6
0
Unit
V
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
V
+
+
DD
V
DD
DDQ
SS
V
V
2.5V
2.5V
100mV
100mV
V
V
Industrial
0V
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
V
DDQ + 100mV(2)
____
5679 tbl 04
1.7
1.7
V
V
V
IH
IH
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
_
Input High Voltage
V
V
DD + 100mV(2)
____
JTAG
Capacitance(1)
V
V
V
IH
IL
IL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
Input High Voltage -
____
____
____
ZZ, OPT
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Input Low Voltage
0.7
0.2
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 0V
OUT = 0V
Max. Unit
Input Low Voltage -
-0.3(1)
V
ZZ, OPT
CIN
V
15
pF
5679 tbl 05
NOTES:
(2)
COUT
V
10.5
pF
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
5679 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS(0V), and VDDQX for that port must be
supplied as indicated above.
2. COUT also references CI/O.
RecommendedDCOperating
Conditions with VDDQ at 3.3V
AbsoluteMaximumRatings(1)
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
3.15
0
Typ.
2.5
3.3
0
Max.
2.6
3.45
0
Unit
V
Symbol
Rating
Commercial
& Industrial
Unit
V
V
DD
DDQ
SS
V
V
V
TERM
V
Terminal Voltage
-0.5 to 3.6
(VDD
)
wiDthD Respect to GND
V
V
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
(2)
V
TERM
(VDDQ
V
Terminal Voltage
-0.3 to VDDQ + 0.3
-0.3 to VDDQ + 0.3
-55 to +125
V
wiDthDQRespect to GND
2.0
1.7
V
DDQ + 150mV(2)
V
V
____
V
IH
IH
)
(2)
_
V
TERM
Input and I/O Terminal
V
Input High Voltage
____
V
V
DD + 100mV(2)
JTAG
(INPUTS and I/O's)
Voltage with Respect to GND
(3)
Input High Voltage -
TBIAS
Temperature
Under Bias
oC
oC
VIH
VIL
VIL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
____
____
____
ZZ, OPT
Input Low Voltage
0.8
0.2
Storage
-65 to +150
TSTG
Input Low Voltage -
Temperature
-0.3(1)
V
ZZ, OPT
T
JN
Junction Temperature
+150
50
oC
5679 tbl 06
NOTES:
IOUT(For VDDQ = 3.3V) DC Output Current
mA
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
IOUT(For VDDQ = 2.5V) DC Output Current
40
mA
5679 tbl 07
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be
supplied as indicated above.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed VDDQ during power
supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
6
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T653M
Min.
___
___
___
___
Symbol
|ILI
|ILI
|ILO
Parameter
Input Leakage Current(1)
JTAG & ZZ Input Leakage Current(1,2)
Output Leakage Current(1,3)
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DD = Max. IN = 0V to VDD
= VIH or CE = VIL, VOUT = 0V to VDDQ
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Max.
10
Unit
µA
µA
µA
V
|
V
V
|
,
V
+60
10
|
CE
0
1
V
OL (3.3V) Output Low Voltage(1)
OH (3.3V) Output High Voltage(1)
OL (2.5V) Output Low Voltage(1)
OH (2.5V) Output High Voltage(1)
NOTES:
I
0.4
___
V
I
2.4
___
V
V
I
0.4
V
___
V
I
2.0
V
5679 tbl 09
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)
70T653MS10
Com'l Only
70T653MS12
Com'l
70T653MS15
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
710
790
210
260
460
510
Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
mA
600
CE and CE = VIL
,
OutLputs DisaRbled
S
S
S
S
S
S
600
810
600
450
____
____
____
____
(1)
Ports Active)
IND
600
f = fMAX
(6)
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
mA
CE
L
= CE
R
= VIH
COM'L
IND
180
240
150
120
170
(1)
f = fMAX
____
____
____
____
150
(6)
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
COM'L
IND
400
530
360
300
400
Active Port Outputs Disabled,
____
____
____
____
(1)
360
f = fMAX
ISB3
Full Standby Current Both Ports CE
L
and
COM'L
IND
S
S
4
20
4
4
20
40
4
20
(Both Ports - CMOS CE
R > VDDQ - 0.2V,
Level Inputs)
VIN > VDDQ - 0.2V or VIN < 0.2V,
____
____
____
____
f = 0(2)
(6)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
CE"A" < 0.2V and
COM'L
IND
S
S
400
530
460
510
300
400
CE"B" > VDDQ - 0.2V(5)
V
IN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
____
____
____
____
360
(1)
f = fMAX
IZZ
Sleep Mode Current ZZL = ZZR =
V
IH
mA
COM'L
IND
S
S
4
20
4
4
20
40
4
20
(1)
(Both Ports - TTL
Level Inputs)
f = fMAX
____
____
____
____
5679 tbl 10
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input
levels of GND to 3.3V.
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 200mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V
CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V.
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.
7
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels
GND to 3.0V / GND to 2.4V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
Figure 1
5679 tbl 11
50Ω
50Ω
,
DATAOUT
1.5V/1.25
10pF
(Tester)
5679 drw 03
Figure 1. AC Output Test load.
4
3.5
3
2.5
∆
t
AA/tACE
2
1.5
1
(Typical, ns)
0.5
0
0
160
140
5679 drw 05
20
40
60
120
80
100
∆
Capacitance (pF) from AC Test Load
Figure 3. Typical Output Derating (Lumped Capacitive Load).
8
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70T653MS10
Com'l Only
70T653MS12
Com'l
70T653MS15
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
LZOB
HZ
PU
PD
SOP
SAA
SOE
Read Cycle Time
10
____
12
____
15
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Access Time
10
10
5
12
12
6
15
15
7
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
____
____
____
____
____
____
____
____
____
t
t
t
5
____
6
____
7
____
t
Output Hold from Address Change
3
3
0
0
3
3
0
0
3
3
0
0
t
Output Low-Z Time Chip Enable and Semaphore(1,2)
Output Low-Z Time Output Enable and Byte Enable(1,2)
Output High-Z Time(1,2)
____
____
____
____
____
____
t
t
4
____
6
____
8
____
t
Chip Enable to Power Up Time(2)
0
____
0
____
0
____
t
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
8
4
8
6
12
8
____
____
____
t
t
2
____
10
5
2
____
12
6
2
____
15
7
t
Semaphore Output Enable Access Time
ns
5679 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(4)
70T653MS10
Com'l Only
70T653MS12
Com'l
70T653MS15
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
DH
WZ
OW
SWRD
SPS
Write Cycle Time
10
7
12
9
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
7
9
t
0
0
t
7
9
12
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2)
SEM Flag Write to Read Time
SEM Flag Contention Window
0
0
t
5
7
10
t
0
____
0
____
0
____
t
4
____
6
____
8
____
t
3
5
5
3
5
5
3
5
5
____
____
____
____
____
____
t
t
ns
5679 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
9
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(4)
t
RC
ADDR
(3)
t
t
AA
(3)
ACE
CE(5)
(3)
t
AOE
OE
(3)
t
ABE
BEn
R/W
t
OH
(1)
tLZ/tLZOB
VALID DATA(3)
DATAOUT
(2)
tHZ
.
5679 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE, CE or BEn.
2. Timing depends on which signal is de-asserted first CE, OE or BEn.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tABE.
4. SEM = VIH.
5. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
Timing of Power-Up Power-Down
CE
tPU
t
PD
I
CC
SB
50%
50%
.
5679 drw 07
I
10
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
CE or SEM(9)
t
AW
(7)
t
HZ
(9)
BEn
(3)
(6)
(2)
t
WR
t
AS
tWP
R/W
(7)
(7)
t
LZ
t
OW
tWZ
(4)
OUT
(4)
DATA
t
DH
t
DW
,
IN
DATA
5679 drw 10
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)
t
WC
ADDRESS
tAW
CE or SEM(9)
BEn(9)
(6)
AS
(3)
WR
(2)
t
t
EW
t
R/W
tDW
tDH
DATAIN
.
.
5679 drw 11
NOTES:
1. R/W or CE or BEn = VIH during all address transitions for Write Cycles 1 and 2.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
11
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Addressinputsmustbestable. Inputdatasetupandholdtimes(tDW and
RapidWrite Mode Write Cycle
RtDaHp) iwdWill rnitoewMboederetfheereIn/OcewdilltoretmheaiennindtinhgeIandpdurtemssodtreafnosritthioend. uIrnattihoins
of the operations due to R/W being held low. All standard Write Cycle
specifications must be adhered to. However, tAS and tWR are only
applicable when switching between read and write operations. Also,
therearetwoadditionalconditionsontheAddressInputsthatmustalso
bemettoensurecorrectaddresscontrolledwrites. Thesespecifications,
the Allowable Address Skew (tAAS) and the Address Rise/Fall time
(tARF),mustbemettousetheRapidWriteMode. Iftheseconditionsare
notmetthereisthepotentialforinadvertentwriteoperationsatrandom
intermediate locations as the device transitions between the desired
writeaddresses.
Unlike other vendors' Asynchronous Random Access Memories,
theIDT70T653Miscapableofperformingmultipleback-to-backwrite
operations without having to pulse the R/W, CE, or BEn signals high
duringaddresstransitions. ThisRapidWriteModefunctionalityallows
the system designer to achieve optimum back-to-back write cycle
performancewithoutthedifficulttaskofgeneratingnarrowresetpulses
everycycle, simplifyingsystemdesignandreducingtimetomarket.
DuringthisnewRapidWriteMode,theendofthewritecycleisnow
definedbytheendingaddresstransition,insteadoftheR/WorCEorBEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughouttheaddresstransitionbetweenwritecycles.Caremustbe
taken to still meet the Write Cycle time (tWC), the time in which the
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)
(4)
WC
t
WC
t
tWC
ADDRESS
(2)
EW
t
CE or SEM(6)
BEn
R/W
t
WR
t
WP
(5)
WZ
(5)
OW
t
t
DATAOUT
tDH
tDH
t
DH
tDW
tDW
tDW
DATAIN
5679 drw 08
NOTES:
1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
12
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle(1)
Symbol
Parameter
Min
Max
Unit
____
t
AAS
Allowable Address Skew for RapidWrite Mode
Address Rise/Fall Time for RapidWrite Mode
1
ns
____
tARF
1.5
V/ns
5679 tbl 14
NOTE:
1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.
Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle
A
0
tARF
t
AAS
A
18
t
ARF
5679 drw 09
13
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
t
AW
tWR
ACE
t
EW
SEM(1)
tOH
t
SOP
tDW
OUT
DATA
VALID(2)
I/O
IN
DATA VALID
t
AS
t
WP
tDH
R/W
t
SWRD
tSOE
OE
t
SOP
Write Cycle
Read Cycle
.
5679 drw 12
NOTES:
1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate BEn controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8 and I/O18 - I/O26) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
.
5679 drw 13
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
14
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70T653MS10
Com'l Only
70T653MS12
Com'l
70T653MS15
Com'l Only
& Ind
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
BUSY TIMING
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
7
0
9
0
ns
ns
tWH
12
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
____
____
____
____
____
____
t
WDD
14
14
16
16
20
20
ns
tDDD
ns
5679 tbl 15
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2,3)
70T65M3S10
Com'l Only
70T653MS12
70T6539MS15
Com'l Only
Com'l
& Ind
Symbol
SLEEP MODE TIMING (ZZx=VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
)
____
____
____
____
____
____
____
____
____
t
ZZS
ZZR
ZZPD
ZZPU
Sleep Mode Set Time
10
10
12
12
15
15
t
Sleep Mode Reset Time
t
Sleep Mode Power Down Time(4)
Sleep Mode Power Up Time(4)
10
____
12
____
15
____
t
0
0
0
5679 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
4. This parameter is guaranteed by device characterization, but is not production tested.
15
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read(1,3)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDH
t
DW
VALID
DATAIN "A"
ADDR"B"
MATCH
(4)
R/W"B"
tWDD
DATAOUT "B"
VALID
(3)
t
DDD
.
NOTES:
5679 drw 14a
1. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
2. OE = VIL for the reading port.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4. R/WB = VIH.
Timing Waveform of Write with BUSY
tWP
R/W"A"
t
WB
BUSY"B"
(1)
tWH
(2)
R/W"B"
.
NOTES:
1. tWH must be met for BUSY input.
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
5679 drw 15
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2)
70T653MS10
Com'l Only
70T653MS12
Com'l
& Ind
70T653MS15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
____
0
____
0
____
t
10
10
12
12
15
15
____
____
____
t
Interrupt Reset Time
ns
5679 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
16
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
t
WC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
(5)
(4)
tWR
tAS
(3)
CE"A"
R/W"A"
INT"B"
(4)
tINS
.
5679 drw 18
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
(4)
t
AS
(3)
CE"B"
OE"B"
INT"B"
(4)
t
INR
.
5679 drw 19
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (CE or R/W) is asserted last.
5. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
Right Port
R/W
L
L
A
18L-A0L
R/W
X
R
A
18R-A0R
Function
CE
L
OE
X
L
INT
X
L
CE
X
R
OE
X
R
INTR
L
7FFFF
X
X
L(2)
H(3)
X
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT Flag
R
Flag
X
X
X
X
L(3)
H(2)
X
L
L
7FFFF
7FFFE
X
R
Flag
X
X
X
X
L
L
X
L
X
L
L
7FFFE
X
X
X
X
L
5679 tbl 17
NOTES:
1. Assumes BUSYL = BUSYR =VIH. CE0X = VIL and CE1X = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
17
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Example of Semaphore Procurement Sequence(1,2,3)
D
0
- D Left
D0 - D Right
D
18 - D286 Right
18 - D286 Left
Functions
Status
D
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5679 tbl 19
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T653M.
2. There are eight semaphore flags written to via I/O0 and read from I/Os (I/O0-I/O8 and I/O18-I/O26). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
semaphoreflags. Theseflagsalloweitherprocessorontheleftor
TheIDT70T653Mprovidestwoportswithseparatecontrol,address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T653M has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
when not selected (CE= HIGH). When a port is enabled, access to the
entirememoryarrayispermitted.
right side of the Dual-Port RAM to claim a privilege over the other
processorforfunctionsdefinedbythesystemdesigner’ssoftware.As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port RAM or any other
shared resource.
TheDual-PortRAMfeaturesafastaccesstime,withbothportsbeing
completelyindependentofeachother.Thismeansthatthe activityonthe
leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom
orwrittentoatthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE0andCE1,theDual-
PortRAMchipenables,andSEM,thesemaphoreenable.TheCE0,CE1,
and SEM pins control on-chip power down circuitry that permits the
respectiveporttogointostandbymodewhennotselected.
Systems which can best use the IDT70T653M contain multiple
processors or controllers and are typically very high-speed systems
whicharesoftwarecontrolledorsoftwareintensive. Theseystemscan
benefit from a performance increase offered by the IDT70T653Ms
hardware semaphores, which provide a lockout mechanism without
requiringcomplexprogramming.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mail box
ormessagecenter)isassignedtoeachport. Theleftportinterruptflag
(INTL)isassertedwhentherightportwritestomemorylocation7FFFE
(HEX),whereawriteisdefinedasCER=R/WR =VIL pertheTruthTable.
Theleftportclearstheinterruptthroughaccessofaddresslocation7FFFE
when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
7FFFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
thememorylocation7FFFF.Themessage(36bits)at7FFFEor7FFFF
isuser-definedsinceitisanaddressableSRAMlocation.Iftheinterrupt
functionisnotused, addresslocations7FFFEand7FFFFarenotused
asmailboxes,butaspartoftherandomaccessmemory.RefertoTruth
Table III for the interrupt operation.
BusyLogic
Softwarehandshakingbetweenprocessorsoffersthemaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations. The IDT70T653M does not use its semaphore flags to
control any resources through hardware, thus allowing the system
designertotalflexibilityinsystemarchitecture.
TheBUSYpinoperatesasawriteinhibitinputpin.Normaloperation
canbeprogrammedbytyingtheBUSYpinsHIGH.Ifdesired,unintended
writeoperationscanbepreventedtoaportbytyingtheBUSYpinforthat
port LOW.
Anadvantageofusingsemaphoresratherthanthemorecommon
methodsofhardwarearbitrationisthatwaitstatesareneverincurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
Semaphores
The IDT70T653M is an extremely fast Dual-Port 512K x 36 CMOS
StaticRAMwithanadditional8addresslocationsdedicatedtobinary
18
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
subsequent read (see Table IV). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fullytothatlocationandwillassumecontrolovertheresourceinquestion.
Meanwhile,ifaprocessorontherightsideattemptstowriteazerotothe
samesemaphoreflagitwillfail,aswillbeverifiedbythe factthataonewill
bereadfromthatsemaphoreontherightsideduringsubsequentread.
HadasequenceofREAD/WRITEbeenusedinstead,systemcontention
problemscouldhaveoccurredduringthegapbetweenthereadandwrite
cycles.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,it
proceeds to assume control over the shared resource. If it was not
successfulinsettingthelatch,itdeterminesthattherightsideprocessor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquishedthetoken,theleftsideshouldsucceedingainingcontrol.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
sidewritesaonetothatlatch.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
The eight semaphore flags reside within the IDT70T653M in a
separate memory space from the Dual-Port RAM. This address space
isaccessedbyplacingalowinputontheSEMpin(whichactsasachip
selectforthesemaphoreflags)andusingtheothercontrolpins(Address,
CE0, CE1,R/W and BEn) as they would be used in accessing a
standardStaticRAM.Eachoftheflagshasauniqueaddresswhichcan
beaccessedbyeithersidethroughaddresspinsA0–A2.Whenaccessing
thesemaphores, noneoftheotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table IV).
Thatsemaphorecannowonlybemodifiedbythesideshowingthezero.
Whenaoneiswrittenintothesamelocationfromthesameside,the flag
will be set to a one for both sides (unless a semaphore request
fromtheothersideispending)andthencanbewrittentobybothsides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphoreflagsusefulininterprocessorcommunications.(Athorough
discussionontheuseofthisfeaturefollowsshortly.)Azerowrittenintothe
samelocationfromtheothersidewillbestoredinthesemaphorerequest
latchforthatsideuntilthesemaphoreisfreedbythefirstside.
5679 drw 21
Figure 4. IDT70T653M Semaphore Logic
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Iftheoppositesidesemaphorerequestlatchhas
beenwrittentozerointhemeantime,thesemaphoreflagwillflipoverto
theothersideassoonasaoneiswrittenintothefirstrequestlatch.The
oppositesideflagwillnowstayLOWuntilitssemaphorerequestlatchis
writtentoaone.Fromthisitiseasytounderstandthat,ifasemaphoreis
requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
side to make the request will receive the token. If
bothrequestsarriveatthesametime, theassignmentwillbearbitrarily
made to one port or the other.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE
signalsneedtobeactive. (PleaserefertoTruthTableII). Furthermore,
thereadvalueislatchedintooneside’soutputregisterwhenthatside's
semaphoreselect(SEM,BEn)andoutputenable(OE)signalsgoactive.
Thisservestodisallowthesemaphorefromchangingstateinthemiddle
of a read cycle due to a write cycle from the other side.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
19
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
20
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
SleepMode
The IDT70T653M is equipped with an optional sleep or low power operation occurs during these periods, the memory array may be
modeonbothports.Thesleepmodepinonbothportsisactivehigh.During corrupted. Validity of data out from the RAM cannot be guaranteed
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the immediatelyafterZZisasserted(priortobeinginsleep).
port will enter sleep mode where it will meet lowest possible power
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
conditions.Thesleepmodetimingdiagramshowsthemodesofoperation: disconnectsitsinternalbuffer.Alloutputswillremaininhigh-Zstatewhile
NormalOperation, NoRead/WriteAllowedandSleepMode.
insleepmode.Allinputsareallowedtotoggle.TheRAMwillnotbeselected
Foraperiodoftime priortosleepmodeandafterrecoveringfromsleep and will not perform any reads or writes.
mode(tZZS andtZZR),newreadsorwritesarenotallowed.Ifawriteorread
JTAG Functionality and Configuration
TheIDT70T653Miscomposedoftwoindependentmemoryarrays, Register Sizes, and System Interface Parameter tables. Specifically,
and thus cannot be treated as a single JTAG device in the scan chain. commands for Array B must precede those for Array A in any JTAG
The two arrays (A and B) each have identical characteristics and operationssenttotheIDT70T653M. PleasereferenceApplicationNote
commandsbutmustbetreatedasseparateentitiesinJTAGoperations. AN-411,"JTAGTestingofMultichipModules"forspecificinstructionson
Please refer to Figure 5.
performing JTAG testing on the IDT70T653M. AN-411 is available at
JTAGsignalingmustbeprovidedseriallytoeacharrayandutilizes www.idt.com.
theinformationprovidedintheIdentificationRegisterDefinitions,Scan
IDT70T653M
Array B
TDO
TDI
TDOA
TDIB
Array A
TCK
TMS
TRST
5679 drw 23
Figure 5. JTAG Configuration for IDT70T653M
21
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JCYC
t
JR
tJF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
t
JDC
t
JS
t
JH
Device Outputs(2)/
TDO
t
JRSR
t
JCD
TRST
x
5679 drw 24
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, TCK and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T653M
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
____
Units
ns
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
____
____
t
ns
t
40
____
ns
t
3(1)
3(1)
ns
____
t
ns
____
t
50
ns
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
____
ns
NOTES:
1. Guaranteed by design.
t
25
____
ns
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any
speed specified in this datasheet.
t
0
ns
____
____
t
15
15
ns
5. JTAG cannot be tested in sleep mode.
t
JTAG Hold
ns
5679 tbl 20
22
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Value
Value
Instruction Field Array B
Instruction Field Array A
Description
Reserved for Version number
Array B
0x0
Array A
0x0
Revision Number (31:28)
Revision Number (63:60)
IDT Device ID (59:44)
IDT Device ID (27:12)
0x33B
0x33
1
0x33B
0x33
1
Defines IDT Part number
IDT JEDEC ID (11:1)
IDT JEDEC ID (43:33)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID Register
ID Register Indicator Bit (Bit 0)
ID Register Indicator Bit (Bit 32)
5679 tbl 21
ScanRegisterSizes
Bit Size
Array A
Bit Size
Bit Size
Register Name
Array B
70T653M
Instruction (IR)
4
1
4
1
8
2
Bypass (BYR)
Identification (IDR)
Boundary Scan (BSR)
32
32
64
Note (3)
Note (3)
Note (3)
5679 tbl 22
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
00000000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
11111111
Places the bypass register (BYR) between TDI and TDO.
00100010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
01000100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
00110011
00010001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
RESERVED
Several combinations are reserved. Do not use codes other than those
identified above.
All Other Codes
5679 tbl 23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, TCK and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
23
IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
A
A
A
Speed
Package
Power
Device
Type
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0 C to +70 C)
Industrial (-40 C to +85 C)
Blank
I(1)
G(2)
BC
Green
256-ball BGA (BC-256)
Commercial Only
Commercial & Industrial
Commercial Only
10
12
15
Speed in nanoseconds
Standard Power
S
18Mbit (512K x 36) Asynchronous Dual-Port RAM
70T653M
5679 drw 25
NOTE:
1. Contactyourlocalsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
DatasheetDocumentHistory:
10/08/03: InitialDatasheet
10/20/03: Page1Added"IncludesJTAGfunctionality"tofeatures
Page 13 Corrected tARF to 1.5V/ns Min
09/28/04: Removed "Preliminary" status
Page 11 Updated Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Page21 AddedJTAGConfigurationandJTAGFunctionalitydescriptions
Page 1 & 24 Replaced old logo with the new TM logo
06/30/05: Page 1 Added green availability to features
Page 24 Added green indicator to ordering information
07/25/08: Page 7 Corrected a typo in the DC Chars table
01/19/09: Page 24 Removed "IDT" from orderable part number
06/15//15: Page 3 RemovedthedatefromtheBC256pinconfiguration
Page24AddedTapeandReelindicatorsandaddedfootnoteannotationstotheOrderingInformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
24
相关型号：
70T653MS12BCG8
Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
70T653MS12BCGI8
Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
70T653MS15BCG
Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
70T653MS15BCG8
Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
70T659S10BCGI8
Application Specific SRAM, 128KX36, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
©2020 ICPDF网 联系我们和版权申明