70V18L20PFGI中文资料_数据手册_规格书

HIGH-SPEED 3.3V

64K x 9 DUAL-PORT

STATIC RAM

IDT70V18L

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

IDT70V18 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

than one device

◆

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

◆

Low-power operation

Full on-chip hardware support of semaphore signaling

between ports

– IDT70V18L

◆

Active: 440mW (typ.)

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

Standby: 660µW (typ.)

◆

Dual chip enables allow for depth expansion without

external logic

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Busy and Interrupt Flags

◆

On-chip port arbitration logic

Green parts available, see ordering information

Functional Block Diagram

R/W_L

CE0L

CE1L

R/W_R

CE0

R

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

0-8L

I/O

0-8R

I/O

(1,2)

L

(1,2)

R

BUSY

64Kx9

MEMORY

ARRAY

70V18

A

15L

A

15R

0R

Address

Decoder

Address

Decoder

A

0L

16

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE _0L

CE_1L

CE_0R

CE_1R

OE_R

OE

L

R/W_L

R/W

R

SEM

INT

L

SEM

R

(2)

INT

R

M/S⁽¹⁾

4854 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

MARCH 2015

1

DSC-4854/6

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT70V18 is a high-speed 64K x 9 Dual-Port Static RAM. The forreadsorwritestoanylocationinmemory.Anautomaticpowerdown

IDT70V18 is designed to be used as a stand-alone 576K-bit Dual-Port featurecontrolledbythe chipenables(eitherCE0orCE1)permittheon-

RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit- chip circuitry of each port to enter a very low standby power mode.

or-morewordsystem.UsingtheIDTMASTER/SLAVEDual-PortRAM

Fabricated using CMOS high-performance technology, these de-

approach in 18-bit or wider memory system applications results in full- vicestypicallyoperateononly440mWofpower.

speed, error-free operation without the need for additional discrete

logic.

TheIDT70V18ispackagedina100-pinThinQuadFlatpack(TQFP).

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access

Pin Configurations^(1,2,3)

Index

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

NC

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

2

A

7L

8L

9L

3

A

7R

4

8R

5

9R

A

10L

11L

12L

13L

14L

15L

6

10R

11R

12R

13R

14R

15R

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT70V18PF

PN100

(4

)

NC

Vcc

NC

CE0L

CE1L

NC

GND

NC

CE0R

CE1R

100-Pin

TQFP

(5)

Top View

SEM

R/W

OE

L

SEM

R/W

OE

R

GND

NC

GND

NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

4854 drw 02

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

2

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

CE0R, CE1R

R/W

OE

Names

Chip Enables

CE0L, CE1L

R/W

OE

L

R

Read/Write Enable

Output Enable

Address

L

R

A

0L - A15L

A

0R - A15R

I/O0R - I/O8R

SEM

INT

BUSY

M/S

I/O^0L- I/O8L

SEM

INT

BUSY

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

L

R

L

R

L

R

Master or Slave Select

Power

V

CC

GND

Ground

4854 tbl 01

Absolute Maximum Ratings⁽¹⁾

Recommended DC Operating

Conditions

Symbol

Rating

Commercial

Unit

& Industrial

Symbol

V^CC

Parameter

Supply Voltage

Ground

Min.

3.0

Typ.

Max.

3.6

Unit

V

(2)

3.3

V

TERM

Te rm inal Vo l tag e

-0.5 to +4.6

V

with Respect to GND

GND

V^IH

0

____

0

V

(3)

T

BIAS

STG

JN

OUT

Temperature Under Bias

Storage Temperature

Junction Temperature

DC Output Current

-55 to +125

-65 to +150

+150

^oC

Input High Voltage

Input Low Voltage

2.0

-0.3⁽¹⁾

VCC+0.3⁽²⁾

V

____

T

V^IL

0.8

V

4854 tbl 04

T

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 0.3V.

I

50

mA

4854 tbl 02

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

Capacitance⁽¹⁾(TA = +25°C, f = 1.0MHz)

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions

IN = 0V

OUT = 0V

Max. Unit

2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.

3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.

CIN

V

9

pF

(2)

C

OUT

V

10

pF

4854 tbl 05

NOTES:

Maximum Operating Temperature

andSupplyVoltage

1. This parameter is determined by device characterization but is not produc-

tion tested.

2. COUT also references CI/O.

Grade

Ambient

GND

Vcc

Temperature⁽¹⁾

Commercial

Industrial

0^OC to +70^OC

-40^OC to +85^OC

0V

3.3V

+

0.3V

4854 tbl 03

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

3

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I – Chip Enable^(1,2)

CE

1

Mode

CE

CE0

V

IL

V

IH

Port Selected (TTL Active)

L

< 0.2V

>VCC -0.2V

X

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

Port Deselected (CMOS Inactive)

V

IH

X

V

X⁽³⁾

IL

H

>VCC -0.2V

X⁽³⁾

<0.2V

4854 tbl 06

NOTES:

1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.

2. 'H' = VIH and 'L' = VIL.

3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.

Truth Table II – Non-Contention Read/Write Control

Inputs⁽¹⁾

R/W

Outputs

I/O0-8

(2)

Mode

CE

OE

X

SEM

H

L

X

L

High-Z

DATA^IN

DATA^OUT

High-Z

Deselected: Power-Down

Write to Memory

X

H

L

H

X

L

H

Read Memory

X

H

X

Outputs Disabled

4854 tbl 07

NOTES:

1. A0L — A15L ≠ A0R — A15R

2. Refer to Chip Enable Truth Table.

Truth Table III – Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

I/O0-8

(2)

R/W

H

Mode

CE

OE

L

SEM

H

L

DATAOUT

Read Semaphore Flag Data Out

Write I/O into Semaphore Flag

Not Allowed

X

DATA^IN

______

0

↑

X

4854 tbl 08

NOTES:

1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O8). These eight semaphore flags are addressed by A0-A2.

2. Refer to Chip Enable Truth Table.

4

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

70V18L

Symbol

|I^LI

|I^LO

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

CC = 3.6V, VIN = 0V to VCC

Min.

___

Max.

Unit

µA

V

|

V

5

(2)

___

|

CE = VIH, VOUT = 0V to VCC

OL = +4mA

OH = -4mA

V

OL

I

0.4

___

V

OH

Output High Voltage

I

2.4

V

4854 tbl 09

NOTES:

1. At Vcc < 2.0V, input leakages are undefined.

2. RefertoTruthTableI-ChipEnable.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽⁵⁾(VCC = 3.3V ± 0.3V)

70V18L15

Com'l Only

70V18L20

Com'l

& Ind

Unit

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽¹⁾Max. Typ.⁽¹⁾Max.

mA

ICC

Dynamic Operating

Current

L

145

---

235

---

135

35

205

220

55

CE = V^IL, Outputs Disabled

SEM = ₍V₂₎^IH

(Both Ports Active)

IND

f = fMAX

mA

ISB1

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

IND

40

---

70

CE

L

= CE = VIH

R

SEM = SEM

L

= VIH

f = fM^RAX

(2)

---

35

65

(4)

ISB2

Standby Current

(One Port - TTL Level

Inputs)

COM'L

IND

100

---

155

---

90

140

150

3.0

135

145

CE"A" = V and CE = VIH

Active Po^Ir^Lt Outputs^"BD^"isabled,

(2)

90

f=f^MAX

,

SEM

R

= SEM = VIH

L

ISB3

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE

L

and CE

R

> VCC - 0.2V,

COM'L

IND

0.2

---

3.0

---

0.2

90

V

IN > VCC - 0.2V or VIN < 0.2V, f = 0⁽³⁾

SEM = SEML > VCC - 0.2V

R

CE"A" < 0.2V and CE"B" > V - 0.2V⁽⁴⁾

,

ISB4

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

IND

95

150

SEM

R

= SEM

L

> VCC - 0.2V,^CC

90

V

> VCC - 0.2V or VIN < 0.2V,

Ac^INtive Port Outputs Disabled, f = f^MAX

---

(2)

4854 tbl 10

NOTES:

1. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)

2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND

to 3V.

3. f = 0 means no address or control lines change.

4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

5. Refer to Truth Table I - Chip Enable.

5

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

3.3V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

1.5V

Figures 1 and 2

590Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

30pF

435Ω

5pF*

435Ω

4854 tbl 11

4854 drw 03

4854 drw 04

Figure 1. AC Output Load

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

Waveform of Read Cycles⁽⁵⁾

t

RC

ADDR

(4)

t

AA

(4)

CE⁽⁶⁾

OE

ACE

(4)

tAOE

R/W

(1)

t

OH

(2)

tLZ

(4)

DATAOUT

VALID DATA

t

HZ

BUSYOUT

(3,4)

BDD

4854 drw 05

t

Timing of Power-Up Power-Down

CE⁽⁶⁾

tPU

tPD

ICC

50%

.

4854 drw 06

ISB

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

6. Refer toTruth Table I - Chip Enable.

6

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70V18L15

70V18L20

Com'l

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

15

____

20

____

ns

t

Address Access Time

15

20

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

Output High-Z Time^(1,2)

Chip Enable to Power Up Time ⁽²⁾

Chip Disable to Power Down Time ⁽²⁾

____

t

10

____

12

____

t

3

____

t

3

____

3

____

t

10

____

10

____

t

0

____

0

____

t

15

____

20

____

t

Semaphore Flag Update Pulse (OE or SEM)

10

____

10

____

t

Semaphore Address Access Time

15

20

ns

4854 tbl 12

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage

70V18L15

Com'l Only

70V18L20

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

15

12

0

20

15

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

t

Write Pulse Width

12

0

15

0

t

Write Recovery Time

t

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

Write Enab le to Output in High-Z^(1,2)

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

____

15

____

t

10

____

10

____

t

0

____

0

____

t

10

____

10

____

t

0

5

0

5

____

t

ns

4854 tbl 13

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.

3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

temperature, the actual tDH will always be smaller than the actual tOW.

7

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

t

WC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM⁽⁹⁾

(7)

tHZ

(3)

(6)

(2)

tWR

tAS

tWP

R/W

(7)

tLZ

tOW

tWZ

(4)

OUT

DATA

tDH

t

DW

IN

DATA

,

4854 drw 07

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

tWC

ADDRESS

tAW

CE or SEM^(9,10)

(3)

(6)

(2)

tWR

tAS

tEW

R/W

tDW

tDH

DATAIN

4854 drw 08

NOTES:

1. R/W or CE = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus

for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

10. Refer to Truth Table I - Chip Enable .

8

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

VALID ADDRESS

A0-A2

VALID ADDRESS

tAW

tWR

t

ACE

tEW

SEM

t

OH

tDW

tSOP

OUT

DATA

DATA_INVALID

I/O

VALID⁽²⁾

tAS

tWP

tDH

R/W

tSWRD

tAOE

OE

tSOP

Write Cycle

Read Cycle

4854 drw 09

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).

2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

SIDE⁽²⁾"A"

R/W"A"

SEM"A"

tSPS

A0"B"-A2"B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

4854 drw 10

NOTES:

1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

9

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70V18L15

70V18L20

Com'l

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max. Unit

BUSY TIMING (M/S=VIH

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

15

20

ns

BUSY Access Time from Address Match

t

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

15

____

17

____

t

5

____

5

____

BUSY Disable to Valid Data⁽³⁾

t

15

____

17

____

(5)

t

Write Hold After BUSY

12

15

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

t

WB

0

ns

(5)

tWH

Write Hold After BUSY

12

15

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

Write Data Valid to Read Data Delay⁽¹⁾

30

25

45

30

ns

tDDD

ns

4854 tbl 14

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

10

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)^(2,4,5)

tWC

MATCH

ADDR"A"

R/W"A"

tWP

tDW

t

DH

VALID

DATAIN "A"

(1)

tAPS

MATCH

ADDR"B"

t

BAA

tBDA

tBDD

BUSY"B"

t

WDD

DATAOUT "B"

VALID

(3)

tDDD

4854 drw 11

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL, refer to Chip Enable Truth Table.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

(3)

t

WB

BUSY"B"

(1)

tWH

(2)

R/W"B"

4854 drw 12

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'slave' version.

11

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)^(1,3)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

tAPS

CE"B"

tBAC

tBDC

BUSY"B"

4854 drw 13

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(M/S = VIH)⁽¹⁾

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

tAPS

MATCHING ADDRESS "N"

t

BAA

tBDA

4854 drw 14

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. Refer to Truth Table I - Chip Enable.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70V18L15

70V18L20

Com'l Only

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

0

____

t

15

20

____

t

Interrupt Reset Time

ns

4854 tbl 15

12

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing^(1,5)

tWC

INTERRUPT SET ADDRESS⁽²⁾

ADDR"A"

(3)

(4)

t

AS

t

WR

CE"A"

R/W"A"

INT"B"

(3)

tINS

4854 drw 15

tRC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR"B"

CE"B"

(3)

tAS

OE"B"

(3)

tINR

INT"B"

4854 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Truth Table I - Chip Enable.

Truth Table IV — Interrupt Flag^(1,4,5)

Left Port

Right Port

R/W

L

A

15L-A0L

FFFF

X

R/W

R

A

15R-A0R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CE

L

OE

L

INT

L

CE

R

OE

R

INTR

L

X

L

X

L

X

L⁽³⁾

H⁽²⁾

X

L

X

L

X

L⁽²⁾

H⁽³⁾

X

R

X

L

FFFF

FFFE

X

R

X

L

FFFE

X

L

4854 tbl 16

NOTES:

1. Assumes BUSYL = BUSYR =VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5. Refer to Truth Table I - Chip Enable.

13

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table V —

Address BUSY Arbitration⁽⁴⁾

Inputs

Outputs

A

-A

AO^OR^L-A¹15⁵R^L

Function

Normal

(1)

CE

L

CE

R

BUSY

L

BUSYR

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

MATCH

(2)

Write Inhibit⁽³⁾

4854 tbl 17

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V18 are push-

pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and

enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSYR outputs are driving LOW regardless of actual logic level on the pin.

4. Refer to Truth Table I - Chip Enable.

Truth Table VI — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0

- D8

Left

D0

- D8

Right

Status

No Action

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

0

1

0

1

0

1

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

4854 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V18.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.

Functional Description

The IDT70V18 provides two ports with separate control, address FFFE (HEX), where a write is defined as CER = R/WR = VIL per the

and I/O pins that permit independent access for reads or writes to any Truth Table. The left port clears the interrupt through access of

location in memory. The IDT70V18 has an automatic power down address location FFFE when CEL = OEL = VIL, R/W is a "don't care".

feature controlled by CE. The CE0 and CE1 control the on-chip power Likewise, the right port interrupt flag (INTR) is asserted when the left

down circuitry that permits the respective port to go into a standby port writes to memory location FFFF (HEX) and to clear the interrupt

mode when not selected (CE = VIH). When a port is enabled, access flag (INTR), the right port must read the memory location FFFF. The

to the entire memory array is permitted.

message (9 bits) at FFFE or FFFF is user-defined since it is an

addressable SRAM location. If the interrupt function is not used,

address locations FFFE and FFFF are not used as mail boxes, but as

part of the random access memory. Refer to Truth Table IV for the

interrupt operation.

Interrupts

If the user chooses the interrupt function, a memory location (mail

boxormessagecenter)isassignedtoeachport. Theleftportinterrupt

flag (INTL) is asserted when the right port writes to memory location

14

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with the R/W signal. Failure to

observe this timing can result in a glitched internal write inhibit signal

and corrupted data in the slave.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

RAM have accessed the same location at the same time. It also allows

one of the two accesses to proceed and signals the other side that the

RAMis“Busy”. The BUSY pincanthenbeusedtostalltheaccessuntil

the operation on the other side is completed. If a write operation has

been attempted from the side that receives a BUSY indication, the

write signal is gated internally to prevent the write from proceeding. Semaphores

The use of BUSY logic is not required or desirable for all applica-

tions. In some cases it may be useful to logically OR the BUSY outputs

togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe

event of an illegal or illogical operation. If the write inhibit function of

BUSY logicisnotdesirable, the BUSY logiccanbedisabledbyplacing

the part in slave mode with the M/S pin. Once in slave mode the BUSY

pinoperatessolelyasawriteinhibitinputpin. Normaloperationcanbe

programmed by tying the BUSY pins HIGH. If desired, unintended

write operations can be prevented to a port by tying the BUSY pin for

that port LOW.

The IDT70V18 is an extremely fast Dual-Port 64K x 9 CMOS Static

RAM with an additional 8 address locations dedicated to binary

semaphore flags. These flags allow either processor on the left or right

side of the Dual-Port RAM to claim a privilege over the other processor

for functions defined by the system designer’s software. As an ex-

ample, the semaphore can be used by one processor to inhibit the

other from accessing a portion of the Dual-Port RAM or any other

shared resource.

The Dual-Port RAM features a fast access time, with both ports

being completely independent of each other. This means that the

activity on the left port in no way slows the access time of the right port.

Both ports are identical in function to standard CMOS Static RAM and

can be read from or written to at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic power-down

feature controlled by CE, the Dual-Port RAM enable, and SEM, the

semaphore enable. The CE and SEM pins control on-chip power

down circuitry that permits the respective port to go into standby mode

when not selected. This is the condition which is shown in Truth Table

III where CE and SEM are both HIGH.

The BUSY outputs on the IDT70V18 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

A16

CE0

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

BUSY

R

BUSYR

BUSY

L

BUSYL

CE1

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

Systems which can best use the IDT70V18 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70V18s

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

BUSY

L

BUSY

L

BUSYR

BUSY

R

.

4854 drw 17

Figure 3. Busy and chip enable routing for both width and depth expansion

with IDT70V18 RAMs.

Softwarehandshakingbetweenprocessorsoffersthemaximumin

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V18 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70V18 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAMs

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70V18 RAM the BUSY pin is an output if the part is used as a

master (M/S pin = VIH), and the BUSY pin is an input if the part used

as a slave (M/S pin = VIL) as shown in Figure 3.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port RAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,

the state of a semaphore latch is used as a token indicating that a

shared resource is in use. If the left processor wants to use this

resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen

If two or more master parts were used when expanding in width, a

splitdecisioncouldresultwithonemasterindicatingBUSY ononeside

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

The BUSY arbitration on a master is based on the chip enable and

15

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

factthataonewillbereadfromthatsemaphoreontherightsideduring

subsequent read. Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,

it proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first, has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag LOW and the other side HIGH. This condition will

The eight semaphore flags reside within the IDT70V18 in a

separate memory space from the Dual-Port RAM. This address space

isaccessedbyplacingalowinputontheSEMpin(whichactsasachip

select for the semaphore flags) and using the other control pins

(Address, CE, and R/W) as they would be used in accessing a

standard Static RAM. Each of the flags has a unique address which

can be accessed by either side through address pins A0 – A2. When

accessing the semaphores, none of the other address pins has any

effect.

L PORT

R PORT

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

0

D

0

D

Q

WRITE

Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel

is written into an unused semaphore location, that flag will be set to a

zero on that side and a one on the other side (see Truth Table VI). That

semaphore can now only be modified by the side showing the zero.

When a one is written into the same location from the same side, the

SEMAPHORE

READ

SEMAPHORE

READ

4854 drw 18

Figure 4. IDT70V18 Semaphore Logic

flag will be set to a one for both sides (unless a semaphore request continue until a one is written to the same semaphore request latch.

fromtheothersideispending)andthencanbewrittentobybothsides. Should the other side’s semaphore request latch have been written to

The fact that the side which is able to write a zero into a semaphore a zero in the meantime, the semaphore flag will flip over to the other

subsequently locks out writes from the other side is what makes side as soon as a one is written into the first side’s request latch. The

semaphore flags useful in interprocessor communications. (A thor- second side’s flag will now stay LOWuntil its semaphore request latch

ough discussion on the use of this feature follows shortly.) A zero is written to a one. From this it is easy to understand that, if a

written into the same location from the other side will be stored in the semaphore is requested and the processor which requested it no

semaphore request latch for that side until the semaphore is freed by longer needs the resource, the entire system can hang up until a one

the first side.

When a semaphore flag is read, its value is spread into all data bits

is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request

so that a flag that is a one reads as a one in all data bits and a flag a single token by attempting to write a zero into it at the same time. The

containing a zero reads as all zeros. The read value is latched into one semaphore logic is specially designed to resolve this problem. If

side’s output register when that side's semaphore select (SEM) and simultaneous requests are made, the logic guarantees that only one

output enable (OE) signals go active. This serves to disallow the side receives the token. If one side is earlier than the other in making

semaphore from changing state in the middle of a read cycle due to a the request, the first side to make the request will receive the token. If

write cycle from the other side. Because of this latch, a repeated read bothrequestsarriveatthesametime, theassignmentwillbearbitrarily

of a semaphore in a test loop must cause either signal (SEM or OE) to made to one port or the other.

go inactive or the output will never change.

One caution that should be noted when using semaphores is that

A sequence WRITE/READ must be used by the semaphore in semaphores alone do not guarantee that access to a resource is

order to guarantee that no system level contention will occur. A secure. As with any powerful programming technique, if semaphores

processor requests access to shared resources by attempting to write are misused or misinterpreted, a software error can easily happen.

a zero into a semaphore location. If the semaphore is already in use,

Initialization of the semaphores is not automatic and must be

the semaphore request latch will contain a zero, yet the semaphore handled via the initialization program at power-up. Since any sema-

flag will appear as one, a fact which the processor will verify by the phore request flag which contains a zero must be reset to a one,

subsequent read (see Table VI). As an example, assume a processor all semaphores on both sides should have a one written into them

writes a zero to the left port at a free semaphore location. On a at initialization from both sides to assure that they will be free

subsequent read, the processor will verify that it has written success- when needed.

fully to that location and will assume control over the resource in

16

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Ordering Information

A

XXXXX

A

999

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

8

Tube or Tray

Tape and Reel

Blank

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

G⁽²⁾

PF

Green

100-pin TQFP (PN100)

15

20

Commercial Only

Commercial & Industrial

Speed in nanoseconds

L

Low Power

70V18 576K (64K x 9) 3.3V Dual-Port RAM

4854 drw 19

1. Industrialtemperaturerangeisavailable.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.

2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.

DatasheetDocumentHistory:

09/30/99:

11/10/99:

04/10/00:

01/02/02:

InitialPublicOffering

Page 1 & 17 Replaced IDT logo

Page 2 Fixed incorrect pin number

Page 3 Increasedstoragetemperatureparameter

ClarifiedTA parameter

Page 4 Fixed I/O8 in notes

Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Added Truth Table I - Chip Enable as note 5

Page 6 Fixed 5pF* in drawing 04

Page 7 Corrected±200mVto0mVinnotes

Pages 5, 7, 10 & 12 Added industrial temperature range for 20ns to DC & AC Electrical Characteristics

Page3, 5, 7, 10&12 Removedindustrialtempoptionfootnotefromalltables

Page 1 & 17 Replace IDT ^TMlogo with IDT ® logo

10/21/04:

01/29/09:

RemovedPreliminarystatus

Page4 AddedJunctionTemptotheAbsolutemaximumRatingstable

Updated Capacitance table

Page 8 Updated Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

Page 1 & 17 Replaced old IDT  logo with new IDT TM logo

Page 17 Removed "IDT" from orderable part number

17

IDT70V18L

High-Speed 3.3V 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DatasheetDocumentHistory(con't.)

03/19/15::

Page 1 Addedgreenavailabilitytofeatures

Page 17 AddedgreenindicatorwithfootnotetoOrderingInformation

Page 2 RemovedIDTinreferencetofabrication

Page 2 &17 The package code PN100-1 changed to PN100 to match standard package codes

Page 17 AddedTapeandReeltoOrderingInformation

Page 17 AddedfootnotetoIndustrialtempindicatingavailability

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

DualPortHelp@idt.com

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

18

生命周期：	Obsolete	包装说明：	QFP,
Reach Compliance Code：	compliant	HTS代码：	8542.32.00.41
风险等级：	5.84	最长访问时间：	20 ns
JESD-30 代码：	S-PQFP-G100	内存密度：	589824 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	9
功能数量：	1	端子数量：	100
字数：	65536 words	字数代码：	64000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64KX9
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
并行/串行：	PARALLEL	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子位置：	QUAD	Base Number Matches：	1

型号	制造商	描述	价格	文档
70V18L20PFGI8	IDT	Dual-Port SRAM, 64KX9, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100	获取价格
70V19L15PFI9	IDT	TQFP-100, Tray	获取价格
70V19L25PF	IDT	TQFP-100, Tray	获取价格
70V19L25PFI8	IDT	TQFP-100, Reel	获取价格
70V19VL15PF	IDT	TQFP-100, Tray	获取价格
70V24	RENESAS	4K x 16 3.3V Dual-Port RAM	获取价格
70V24L15PF8	IDT	TQFP-100, Reel	获取价格
70V24L15PF9	IDT	Dual-Port SRAM, 4KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
70V24L20JI8	IDT	PLCC-84, Reel	获取价格
70V24L20PF8	IDT	TQFP-100, Reel	获取价格

70V18L20PFGI

70V18L20PFGI 概述

70V18L20PFGI 规格参数

70V18L20PFGI 数据手册

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