70V3379S4BCGI8 [IDT]
HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM;
| 型号： | 70V3379S4BCGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| 文件： | 总17页 (文件大小：729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3379S
Features:
– Data input, address, byte enable and control registers
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Self-timedwriteallowsfastcycletime
◆
◆
◆
◆
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
– Commercial:4.2/5/6ns(max.)
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
– Industrial: 5ns (max)
◆
◆
◆
Pipelined output mode
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
◆
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
Green parts available, see ordering information
FunctionalBlockDiagram
UBL
UBR
LB
R
LB
R/W
L
L
R/W
R
B
B
B B
W W
W W
0
L
1
L
1
R
0
R
CE0L
CE0R
CE1L
CE1R
OE
L
OER
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
32K x 18
MEMORY
ARRAY
,
I/O0R - I/O17R
.
I/O0 L - I/O1 7 L
Din_L
Din_R
CLK
L
CLK
R
A14L
A0L
A14R
A0R
Counter/
Address
Reg.
Counter/
Address
Reg.
ADDR_L
ADDR_R
CNTRST
L
CNTRST
R
ADS
R
ADS
L
L
CNTEN
CNTEN
R
4833 tbl 01
AUGUST 2015
1
DSC 4833/13
©2015 Integrated Device Technology, Inc.
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V3379isahigh-speed32Kx18bitsynchronousDual-Port inbursts.Anautomaticpowerdownfeature,controlledbyCE0andCE1,
RAM. The memory array utilizes Dual-Port memory cells to allow permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower
simultaneousaccessofanyaddressfrombothports.Registersoncontrol, mode.
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming
The70V3379cansupportanoperatingvoltageofeither3.3Vor2.5V
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery ononeorbothports,controllablebytheOPTpins.Thepowersupplyfor
shortcycletimes.Withaninputdataregister,theIDT70V3379hasbeen the core of the device (VDD) remains at 3.3V.
optimizedforapplicationshavingunidirectionalorbidirectionaldataflow
PinConfiguration(1,2,3,4)
1
2
3
4
5
6
7
8
9
11 12 13 14
10
16 17
15
I/O9L
V
SS
NC
A
12L
A
B
C
D
E
F
NC
NC
A
8L
NC
V
DD
A
0L
OPT
L
NC
V
SS
NC
CLK
L
CNTEN
L
A
A
A
4L
NC
VSS
NC
A
9L
V
V
SS
SS
VSS
NC
CE0L
ADS
L
VSS
VDDQR I/O8L
NC
NC
NC
A13L
A5L
1L
2L
I/O9R
VDDQR
V
DD
A14L
V
DDQ
A10L
I/O8R
UB
L
VDD
VSS
CE1L
A6L
NC
R/W
L
L
VSS
NC
I/O10L
NC
A
11L
VDD
VDDQL
I/O7R
NC
LB
L
VDD
NC
NC
A
7L
A3L
I/O7L
OE
L
C N T R S T
L
I/O11L
NC
V
DDQR I/O10R
I/O6L
NC
VSS
VSS
I/O6R
V
DDQ
I/O11R
NC
NC
V
SS
VDDQR
L
NC
V
SS
I/O12L
NC
NC
I/O5L
V
DDQL
NC
G
H
J
VDD
I/O5R
NC
V
DDQR I/O12R
NC
VDD
VSS
70V3379BF
BF-208(5)
V
DDQ
V
SS
V
DD
V
SS
VDDQR
V
DD
SS
V
SS
VSS
L
208-Pin fpBGA
Top View(6)
I/O3R
I/O4R
I/O14R
NC
VDDQL
VSS
K
L
V
I/O13R
VSS
I/O14L
NC
VDDQR
I/O13
L
I/O4L
VSS
NC
I/O3L
NC
VDDQL
I/O15R
NC
V
SS
V
SS
I/O2R
NC
V
DDQR
I/O2L
NC
M
N
P
R
T
NC
V
SS
VDDQL
I/O15L
NC
I/O1R
NC
I/O16L
I/O16
VDDQR
A8R
NC
NC
NC
A
12R
NC
I/O1L
VSS
V
V
DD
SS
CLK
C N T EN
R
A4R
R
R
A
13R
V
SS
I/O17
R
CE0R
VDDQR
NC
NC
A
9R
NC
I/O0R
ADS
R
A
5R
V
DDQL
V
SS
SS
A1R
VSS
NC
I/O17L
UBR
NC
VSS
A
14R
A
10R
CE1R
VSS
V
DDQL
A
6R
V
NC
NC
NC
R/W
R
A2R
V
SS
VDD
LBR
VDD
I/O0L
NC
A
7R
OE
R
C N TR S T
R
A3R
VDD
NC
NC
A
11R
OPTR
A
0R
U
4833 drw 02
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V3379BC
BC-256(5)
256-Pin BGA
Top View(6)
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
NC
NC
A
11L
A
8L
9L
7L
NC CE1L
CNTEN
L
A
5L
4L
A
2L
A
0L
NC
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
NC
NC
NC
A
12L
10L
A
CE0L
CNTRST
L
A
A
1L
NC
NC
UB
L
R/W
L
VDD
NC
NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
NC
A
13L
A
I/O9L
V
SS
NC
A
NC
LBL
CLK
L
ADS
L
A
6L
A
3L
I/O8L
OPT
L
NC
D1
D2
D6
D9
D11
D3
D5
DDQL
D7
D8
DDQR
D10
D12
D13
D14
D15
D16
D4
NC I/O9R
VDDQL
V
DDQL
V
DDQR
NC
V
V
DDQR
V
VDDQL
VDDQR
V
DD
NC
NC I/O8R
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
DDQL
E14
E16
E15
V
DD
V
DD
SS
SS
V
SS
V
SS
V
SS
SS
SS
V
SS
V
DD
V
DD
V
DDQR
I/O10R I/O10L NC
V
NC
I/O7R
I/O7L
F7
F5
F6
F9
F10
F1
F2
F3
F11
F13
F14
F15
F16
F8
F12
F4
V
SS
I/O11L NC I/O11R
V
DD
V
V
VSS
I/O6R NC I/O6L
DDQR
V
SS
V
VDDQL
V
SS
SS
SS
VDD
G1
G2
G3
G5
H5
G4
G6
G8
G9
G14
G15
G16
G7
G10
G12
G13
G11
NC
V
SS
NC
VDDQR
V
V
V
I/O12L
I/O5L NC
VDDQL
NC
V
SS
VSS
V
SS
V
SS
H11
H12
H16
H13
H7
H8
H9
H10
H14
H15
H6
H3
H4
H1
H2
VSS
VSS
I/O5R
V
DDQL
V
SS
V
V
SS
V
SS
NC
NC
NC
VDDQR
V
SS
VSS
NC I/O12R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O13L
V
SS
I/O14R I/O13R
V
DDQL
V
SS
SS
V
SS
V
SS
SS
V
SS
SS
V
DDQR
I/O4R
V
SS
V
SS
V
SS
I/O3R I/O4L
K6
K8
K10
K12
K13
K2
K4
K5
L5
K7
K9
K11
K15
K16
K1
K3
K14
V
V
VSS
VSS
V
DDQR
NC
V
DDQL
V
SS
V
SS
V
V
SS
NC I/O3L
NC
I/O14L
NC
L7
L8
L11
L12
L13
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
VSS
V
SS
V
SS
VDD
V
DDQL
I/O15R
VDDQR
VDD
V
SS
V
SS
V
SS
NC I/O2R
I/O15L NC
I/O2L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1
M2
M3
M4
M16
M14
M15
V
DD
V
DD
VSS
V
SS
V
SS
V
SS
V
DD
VDD
V
DDQL
I/O16R I/O16L NC
VDDQR
NC
I/O1R I/O1L
N8
N12
N13
N16
N5
N6
DDQR
N7
N9
N10
N11
N4
N15
N1
N2
N3
N14
V
DDQL
VDDQL
NC
V
DD
V
DD
V
DDQR
V
V
DDQL
V
DDQR
V
DDQR
V
DDQL
I/O0R
NC I/O17R NC
NC
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
NC I/O17L NC
NC
A13R
A7R
NC
LB
R
CLK
R
ADS
R
A
6R
NC
NC I/O0L
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
NC
A
12R
A
9R
UB
R
CE0R R/W
R
CNTRST
R
NC
NC
NC
NC
NC
A
4R
A1R OPTR
NC
T2
T3
T1
T4
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
2R
T14
NC
NC
NC
NC
A
14R
NC CE1R
NC
NC
A
11R
A
8R
OE
R
CNTEN
R
A
5R
A
A
0R
4833 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
A
A
1L
0L
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A
14L
NC
OPT
NC (VSS
IO8L
IO8R
NC (VSS
V
V
IO7L
IO7R
V
V
IO6L
IO6R
IO5L
IO5R
V
V
V
V
IO4R
IO4L
IO3R
IO3L
IO2R
IO2L
V
V
IO1R
IO1L
V
V
L
VSS
NC
IO9L
IO9R
DDQL
(7)
(7)
)
)
V
SS
V
IO10L
IO10R
SS
DDQL
9
10
V
DDQR
SS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SS
V
DDQR
IO11L
IO11R
IO12L
IO12R
V
V
V
V
IO13R
IO13L
IO14R
IO14L
DD
70V3379PRF
PK-128(5)
DD
DD
SS
SS
DD
SS
SS
128-Pin TQFP
Top View(6)
IO15R
IO15L
V
DDQL
SS
SS
V
DDQL
IO16R
IO16L
V
DDQR
SS
V
SS
DDQR
IO17R
IO17L
NC
NC
NC
IO0R
IO0L
OPT
A
A
R
0R
1R
A
14R
4833 drw 02a
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as Vss. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
6.42
4
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables
CE0L
,
CE1L
CE0R, CE1R
R/W
L
R/W
R
Read/Write Enable
Output Enable
OEL
OER
A
0L - A14L
I/O0L - I/O17L
CLK
ADS
CNTEN
CNTRST
UB - LB
A
0R - A14R
I/O0R - I/O17R
CLK
ADS
CNTEN
CNTRST
UB - LB
Address
Data Input/Output
Clock
L
R
Address Strobe Enable
Counter Enable
L
R
L
R
Counter Reset
L
R
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
L
L
R
R
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)(1)
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
V
DDQL
V
DDQR
(1,2)
OPT
L
OPTR
Option for selecting VDDQX
Power (3.3V)(1)
V
V
DD
SS
Ground (0V)
4833 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte Lower Byte
CLK
↑
CE
H
H
H
H
H
H
H
H
1
R/W
X
I/O9-18
High-Z
High-Z
I/O0-8
MODE
OE
X
X
X
X
L
CE
0
UB
H
H
L
LB
H
L
L
L
L
L
L
L
L
L
High-Z
All Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to Both Bytes
L
DIN
↑
H
L
L
DIN
High-Z
↑
L
L
DIN
DIN
↑
H
L
L
H
H
H
X
High-Z
DOUT
Read Lower Byte Only
Read Upper Byte Only
Read Both Bytes
↑
L
H
L
DOUT
High-Z
↑
L
L
DOUT
DOUT
↑
H
L
L
High-Z
High-Z
Outputs Disabled
↑
4833 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.42
5
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous
Address
Addr
Used
Address
CLK(6)
I/O(3)
MODE
ADS CNTEN CNTRST
X
An
An
X
X
X
0
An
X
L(4)
X
L(4)
H
D
I/O(0)
I/O (n) External Address Used
I/O(p) External Address Blocked—Counter disabled (Ap reused)
DI/O(p+1) Counter Enabled—Internal Address generation
Counter Reset to Address 0
↑
↑
↑
↑
X
D
Ap
Ap
Ap
H
H
L(5)
H
D
Ap + 1
H
H
4833 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
RecommendedOperating
RecommendedDCOperating
Conditions with VDDQ at 2.5V
TemperatureandSupplyVoltage(1)
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
2.375 2.5
Max.
3.45
2.625
0
Unit
V
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
V
+
+
DD
V
DD
DDQ
SS
3.3V
3.3V
150mV
150mV
V
V
Industrial
0V
V
0
0
V
V
V
DDQ + 125mV(2)
Input High Voltage(3)
1.7
V
____
4833 tbl 04
V
IH
NOTE:
(Address & Control Inputs)
1. This is the parameter TA. This is the "instant on" case tempereature.
V
IH
IL
Input High Voltage - I/O(3)
1.7
-0.3(1)
DDQ + 125mV(2)
0.7
V
____
____
V
Input Low Voltage
V
4833 tbl 05a
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
AbsoluteMaximumRatings(1)
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be
supplied as indicated above.
Symbol
Rating
Commercial
& Industrial
Unit
(2)
V
TERM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
3.15 3.3
Max.
Unit
V
V
DD
DDQ
SS
3.45
TSTG
Storage
Temperature
V
3.45
V
IOUT
DC Output Current
mA
4833 tbl 06
V
0
0
0
V
Input High Voltage
2.0
V
V
DDQ + 150mV(2)
V
____
V
IH
NOTES:
(Address & Control Inputs)(3)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
V
IH
IL
Input High Voltage - I/O(3)
2.0
-0.3(1)
DDQ + 150mV(2)
0.8
V
V
____
____
V
Input Low Voltage
4833 tbl 05b
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
6
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3)
C
OUT
V
10.5
pF
4833 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3379S
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
CE = VIH or CE = VIL, VOUT = 0V to VDDQ
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Min.
Max.
10
Unit
µA
µA
V
___
___
___
|
V
|
10
0
1
V
OL (3.3V) Output Low Voltage(2)
OH (3.3V) Output High Voltage(2)
OL (2.5V) Output Low Voltage(2)
OH (2.5V) Output High Voltage(2)
I
0.4
___
V
I
2.4
___
V
V
I
0.4
___
V
V
I
2.0
V
4833 tbl 08
NOTES:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
6.42
7
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3379S4
Com'l Only
70V3379S5
Com'l
70V3379S6
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
375
Max.
460
Typ.(4)
Max.
Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
mA
mA
mA
mA
CE and CE = VIL
,
OutLputs DisaRbled,
S
S
S
S
S
S
285
285
105
105
190
190
360
415
145
175
260
300
245
310
____
____
____
____
(1)
IND
Ports Active)
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
= CE
R
= VIH
COM'L
IND
145
190
95
125
(1)
f = fMAX
____
____
____
____
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
COM'L
IND
265
325
175
225
Active Port Outputs Disabled,
____
____
____
____
(1)
f=fMAX
ISB3
Full Standby Current Both Ports CE
L
and
COM'L
IND
S
S
6
15
6
6
15
30
6
15
(Both Ports - CMOS CE
R > VDDQ - 0.2V,
Level Inputs)
VIN > VDDQ - 0.2V or VIN < 0.2V,
____
____
____
____
f = 0(2)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
CE"A" < 0.2V and
COM'L
IND
S
S
265
325
180
180
260
300
170
225
CE"B" > VDDQ - 0.2V(5)
V
IN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
____
____
____
____
(1)
f = fMAX
4833 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
8
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
2.5V
AC Test Conditions
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3 0V/GND to 2.35V
.
GND to 3.0V/GND to 2.35V
833Ω
3ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
DATAOUT
5pF*
770Ω
Figures 1, 2, and 3
4833 tbl 10
,
3.3V
50Ω
50Ω
590Ω
5pF*
,
DATAOUT
1.5V/1.25
10pF
DATAOUT
(Tester)
4833 drw 03
435Ω
Figure 1. AC Output Test load.
,
4833 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
3
∆tCD
(Typical, ns)
2
1
•
•
•
•
20.5
50
80 100
200
30
-1
Capacitance (pF)
4833 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
·
6.42
9
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3379S4
70V3379S5
70V3379S6
Com'l Only
Com'l Only
Com'l
& Ind
Symbol
Parameter
Clock Cycle Time (Pipelined)
Clock High Time (Pipelined)
Clock Low Time (Pipelined)
Clock Rise Time
Min.
7.5
3
Max.
Min.
10
Max.
Min.
12
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
t
CYC2
CH2
CL2
t
4
5
t
3
____
4
____
5
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
____
3
____
3
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
Address Setup Time
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
t
t
t
t
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
t
t
ADS Setup Time
t
ADS Hold Time
t
CNTEN Setup Time
t
CNTEN Hold Time
t
CNTRST Setup Time
t
HRST
0.7
____
0.7
____
1.0
____
CNTRST Hold Time
(1)
tOE
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Pipelined)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
4
____
5
____
6
____
t
OLZ
OHZ
CD2
DC
CKHZ
CKLZ
0
0
0
t
1
____
4
1
____
4.5
1
____
5
t
4.2
____
5
____
6
____
t
1
1
1
1
1
1
1
1.5
1
t
3
____
4.5
____
6
____
t
Port-to-Port Delay
Clock-to-Clock Offset
____
____
____
tCO
6
8
10
ns
4833 tbl 11
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
6.42
10
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
tHC
(3)
CE1
t
SB
(5)
tHB
t
SB
tHB
UB, LB(0-3)
R/W
t
HW
t
SW
SA
t
t
HA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
t
CD2
Qn + 1
Qn + 2 (5)
(1)
tCKLZ
t
OHZ
t
OLZ
OE (1)
tOE
NOTES:
4833 drw 06
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
NOTES:
4833 drw 07
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3379 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
11
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2)
CLK
L
tSW
tHW
R/W
L
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
ADDRESS
L
t
t
DATAINL
(3)
CO
t
CLKR
t
CD2
R/WR
t
SW
t
HW
HA
t
SA
t
NO
MATCH
ADDRESS
R
MATCH
VALID
DATAOUTR
tDC
4833 drw 08
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
tCD2
tCD2
(1)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(4)
WRITE
READ
4833 drw 09
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
ADDRESS(3)
DATAIN
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
t
SA
tHA
t
SD
tHD
Dn + 2
tCD2
tCD2
t
CKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
4833 drw 10
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
t
SCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
4833 drw 11
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
13
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
EXTERNAL
ADDRESS
4833 drw 12
Timing Waveform of Counter Reset(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax
0
1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
t
SCN tHCN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS n ADDRESS n+1
ADDRESS 1
NOTES:
4833 drw 13
1. CE0,
, and R/W = VIL; CE1 and CNTRST = VIH.
UB, LB
CE0,
= VIL; CE1 = VIH.
2.
UB, LB
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
14
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
TheIDT70V3379providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide minimal set-up and hold times on
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclock signal,however,theself-timedinternalwrite
pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
The IDT70V3379 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
TheIDT70V3379canalsobeusedinapplicationsrequiringexpanded
width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enablesalloweasierbankingofmultipleIDT70V3379sfordepthexpan-
sion configurations. Two cycles are required with CE0 LOW and CE1
HIGHtore-activatetheoutputs.
A15
IDT70V3379
IDT70V3379
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3379
IDT70V3379
CE1
CE1
CE0
CE0
UB, LB
R/W,
Control Inputs
Control Inputs
OE,
CLK,
ADS,
.
4833 drw 14
CNTRST,
CNTEN
Figure 4. Depth and Width Expansion with IDT70V3379
6.42
15
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
01/18/98:
03/15/99:
04/28/99:
06/08/99:
06/11/99:
07/14/99:
08/04/99:
10/04/99:
11/12/99:
02/28/00:
05/01/00:
InitialPublicRelease
Page 10 AdditionalNotes
AddedfpBGApackage
Page 2 Changed package body height from 1.5mm to 1.4mm
Page 5 Deletednote6forTableII
Page 2 CorrectedpintoT3toVDDQL
Page 6 Improved power numbers
Upgradedspeedto133MHz, added2.5VI/Ocapability
ReplacedIDTlogo
AddednewBGApackage,addedfull2.5Vinterfacecapability
Page 2 Addedballpitch
Page 3 Renamed pins
Page 6 MadecorrectionstoTruthTable
Page 9 Changed Ω numbers in figure 2
Page 4 Addedinformationtopinandpinnotes
Page 6 Increasedstoragetemperatureparameter
ClarifiedTA Parameter
06/07/00:
Page 8 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Removednote7onDCElectricalCharacteristicstable
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16
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(con't)
01/10/01:
Page 1 Changed 64K to 32K in block drawing
RemovedPreliminarystatus
04/10/01:
12/12/01:
AddedIndustrialTemperatureRangesandremovedrelatednotes
Page 2, Addeddaterevisiontopinconfigurations
3& 4
Page 6 Removedindustrialtempfootnotefromtable04
Page 8 Removedindustrialtempfor6nsfromDC&ACElectricalCharacteristics
& 10
Page 16 Removedindustrialtempfrom6nsinorderinginformation
Addedindustrialtempfootnote
Page 1 Replaced TM logo with ® logo
& 17
01/05/06:
Page 1 Addedgreenavailabilitytofeatures
Page 16 AddedgreenindicatortoOrderingInformation
Page 5 Changed footnote 2 for Truth Table I from ADS, CNTEN, CNTRST = VIH to ADS, CNTEN, CNTRST = X
Page 8 Corrected a typo in the DC Chars table
Page 16 Removed "IDT" from orderable part number
Page 2 & 3 Removed date from all of the pin configurations 206-pin fpBGA, 128-pin TQFP & 256-pin PGA respectively
Page 16 Added Tape & Reel to Ordering Information
02/08/06:
07/25/08:
01/19/09:
08/11/15:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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相关型号：
70V3379S4BFG8
Application Specific SRAM, 32KX18, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208
IDT
70V3379S4PRFG8
Application Specific SRAM, 32KX18, 4.2ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, TQFP-128
IDT
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