概述
数据手册70V37L15PFGI8 概述
HIGH-SPEED 3.3V 32K x 18 DUAL-PORT STATIC RAM
70V37L15PFGI8 数据手册
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PDF下载HIGH-SPEED 3.3V
32K x 18 DUAL-PORT
STATIC RAM
IDT70V37L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆
◆
◆
◆
Busy and Interrupt Flags
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
◆
Low-power operation
◆
◆
– IDT70V37L
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Active:440mW(typ.)
Standby:660µW(typ.)
◆
◆
◆
◆
◆
Dual chip enables allow for depth expansion without
external logic
IDT70V37 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
Green parts available, see ordering information
Functional Block Diagram
R/
WL
R/WR
UBL
UBR
CE0L
CE0R
CE1L
CE1R
OE
R
OE
L
L
LBR
LB
I/O 9-17L
I/O 0-8L
I/O9-17R
I/O0-8R
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSY
R
BUSY
L
.
32Kx18
14L
A
14R
0R
A
Address
Decoder
Address
Decoder
MEMORY
ARRAY
70V37
A
0L
A
15
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0R
CE1R
CE0L
CE1L
OER
OEL
R/WR
R/W
L
SEM
L
L
SEM
R
(2)
(2)
INTR
INT
M/S(1)
4851 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JUNE 2015
1
DSC-4851/6
©2015 Integrated Device Technology, Inc.
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
TheIDT70V37isahigh-speed32Kx18Dual-PortStaticRAM. The reads or writes to any location in memory. An automatic power down
IDT70V37 is designed to be used as a stand-alone 576K-bit feature controlled by the chip enables (either CE0 or CE1)
Dual-PortRAMorasacombinationMASTER/SLAVEDual-PortRAMfor permittheon-chipcircuitryofeachporttoenteraverylowstandbypower
36-bit-or-more word system. Using the IDT MASTER/SLAVE mode.
Dual-PortRAMapproachin36-bitorwidermemorysystemapplications
Fabricated using CMOS high-performance technology, these de-
resultsinfull-speed,error-freeoperationwithouttheneedforadditional vices typically operate on only 440mW of power. The IDT70V37 is
discretelogic. packaged in a 100-pin Thin Quad Flatpack (TQFP).
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
PinConfigurations(1,2,3)
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A
9L
A
8R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
A10L
A11L
A12L
A13L
A14L
A
9R
A10R
A11R
A12R
A13R
A14R
3
4
5
6
NC
7
NC
LB
UBR
CE0R
CE1R
SEM
R/W
V
8
LB
UB
CE0L
CE1L
SEM
R/W
OE
L
9
R
L
IDT70V37PF
PN100(4)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
L
L
L
100-Pin TQFP
Top View(5)
R
R
SS
V
DD
VSS
OE
V
I/O17R
V
R
SS
I/O17L
I/O16L
SS
V
SS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4851 drw 02a
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.422
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
R/W
OE
CE0R, CE1R
R/W
OE
L
R
Read/Write Enable
Output Enable
L
R
A0L - A14L
A0R - A14R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
M/S
R
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power (3.3V)
V
DD
VSS
Ground (0V)
4851 tbl 01
RecommendedDCOperating
Conditions
AbsoluteMaximumRatings(1)
Symbol
Parameter
Min.
3.0
Typ.
Max.
3.6
0
Unit
V
Symbol
Rating
Commercial
& Industrial
Unit
V
V
DD
Supply Voltage
Ground
3.3
VSS
0
0
V
(2)
____
V
TERM
Te rminal Vo ltag e
-0.5 to +4.6
-55 to +125
-65 to +150
50
V
IH
IL
NOTES:
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(2)
V
with Respect to GND
-0.3(1)
0.8
V
____
V
TBIAS
Temperature
Under Bias
oC
4851 tbl 04
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
Storage
oC
TSTG
Temperature
IOUT
DC Output Current
mA
4851 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
Max. Unit
CIN
VIN = 0V
9
pF
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
(2)
OUT
C
VOUT = 0V
10
pF
4851 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. COUT also references CI/O.
MaximumOperatingTemperature
andSupplyVoltage(1)
Grade
Ambient
GND
VDD
Temperature(1)
Commercial
Industrial
0OC to +70OC
0V
0V
3.3V
3.3V
+
0.3V
0.3V
-40OC to +85OC
+
4851 tbl 03
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
6.42
3
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable(1,2)
CE
1
Mode
CE
CE0
V
IL
V
IH
Port Selected (TTL Active)
L
< 0.2V
>VDD -0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
V
IH
X
V
X(3)
IL
H
>VDD -0.2V
X(3)
<0.2V
4852 tbl 06
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VDD-0.2V.
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
(2)
R/W
X
I/O9-17
I/O0-8
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
CE
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
X
L
L
L
L
L
L
X
High-Z
High-Z
X
H
L
H
DATAIN
High-Z
L
H
L
H
L
L
H
DATAIN
DATAOUT
High-Z
H
H
H
X
L
H
L
H
Read Upper Byte Only
L
H
L
H
DATAOUT Read Lower Byte Only
DATAOUT Read Both Bytes
L
L
H
DATAOUT
High-Z
H
X
X
X
High-Z
Outputs Disabled
4851 tbl 07
NOTES:
1. A0L — A14L ≠ A0R — A14R
2. Refer to Truth Table I - Chip Enable.
Truth Table III – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
(2)
R/W
H
I/O9-17
DATAOUT
DATAOUT
DATAIN
I/O0-8
Mode
CE
OE
L
UB
X
LB
X
SEM
H
X
H
X
L
L
L
L
L
L
L
DATAOUT Read Data in Semaphore Flag
DATAOUT Read Data in Semaphore Flag
H
L
H
X
H
X
X
DATAIN
Write I/O
0
into Semaphore Flag
into Semaphore Flag
↑
X
H
L
H
X
DATAIN
______
DATAIN
______
Write I/O
0
↑
X
X
Not Allowed
Not Allowed
______
______
L
X
X
X
L
4851 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.
2. Refer to Truth Table I - Chip Enable.
6.442
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V37L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
DD = 3.6V, VIN = 0V to VDD
CE(2) = VIH, VOUT = 0V to VDD
Min.
___
Max.
Unit
µA
µA
V
|ILI|
V
5
5
___
___
|ILO
|
V
OL
I
OL = +4mA
0.4
___
V
OH
Output High Voltage
IOH = -4mA
2.4
V
4851 tbl 09
NOTES:
1. At VDD < 2.0V, input leakages are undefined.
2. Refer to Truth Table I - Chip Enable.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 0.3V)
70V37L15
Com'l Only
70V37L20
Com'l
& Ind
Unit
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(1) Max. Typ.(1) Max.
mA
IDD
Dynamic Operating
Current
L
L
L
L
L
L
L
L
L
L
145
235
135
135
35
205
220
55
CE = VIL, Outputs Disabled
SEM = (V2)IH
___
___
(Both Ports Active)
IND
f = fMAX
mA
mA
mA
mA
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
40
70
CE
L
= CE = VIH
R
SEM = SEM
L
= VIH
f = fMRAX
(2)
___
___
35
65
(4)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
100
155
90
140
150
3.0
3.0
135
145
CE"A" = VIL and CE = V
Active Port Outputs"BD"isablIeHd,
(2)
___
___
90
f=fMAX
,
SEM
R
= SEM = VIH
L
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and CE
R
> VDD - 0.2V,
COM'L
IND
0.2
___
3.0
___
0.2
0.2
90
V
IN > VDD - 0.2V or VIN < 0.2V, f = 0(3)
SEM = SEML > VDD - 0.2V
R
CE"A" < 0.2V and CE > V - 0.2V(4)
,
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
95
150
SEM = SEM > V "-B"0.2V,DD
90
V
IN >RVDD - 0.L2V orDDVIN < 0.2V,
___
___
(2)
Active Port Outputs Disabled, f = fMAX
4851 tbl 10
NOTES:
1. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 90mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels
of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
6.42
5
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
590Ω
590Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
30pF
435Ω
5pF*
435Ω
4851 tbl 11
4851 drw 03
4851 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Load
* Including scope and jig.
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE(6)
OE
(4)
tAOE
(4)
t
ABE
UB, LB
R/W
DATAOUT
BUSYOUT
t
OH
(1)
tLZ
VALID DATA(4)
(2)
tHZ
(3,4)
4851 drw 05
tBDD
Timing of Power-Up Power-Down
CE(6)
tPU
tPD
ICC
50%
50%
.
4851 drw 06
ISB
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer toTruth Table I - Chip Enable.
6.462
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V37L15
70V37L20
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
____
20
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Access Time
15
15
15
20
20
20
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
Output High-Z Time(1,2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
____
____
____
____
____
____
t
t
t
10
____
12
____
t
3
3
____
____
t
3
____
3
____
t
10
____
10
____
t
0
____
0
____
t
15
____
20
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
t
Semaphore Address Access Time
15
20
ns
4851 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70V37L15
Com'l Only
70V37L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
t
t
t
Write Pulse Width
12
0
15
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
____
15
____
t
10
____
10
____
t
0
____
0
____
t
10
____
10
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
4851 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
6.42
7
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9,10)
UB or LB(9)
R/W
(3)
(2)
(6)
tWR
tAS
tWP
(7)
t
OW
t
WZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
4851 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9,10)
UB or LB(9)
(6)
AS
(3)
(2)
t
WR
tEW
t
R/W
tDW
tDH
DATAIN
4851 drw 08
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Truth Table I - Chip Enable.
6.482
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
t
ACE
tEW
SEM
tOH
tSOP
tDW
OUT
DATA
VALID(2)
I/O
IN
DATA VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
4851 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) (Refer to Truth Table I - Chip Enable).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
4851 drw 10
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH or both UB and LB = VIH (Refer to Truth Table I - Chip Enable).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
6.42
9
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V37L15
70V37L20
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
15
____
17
____
t
5
____
5
____
BUSY Disable to Valid Data(3)
t
15
____
17
____
(5)
t
Write Hold After BUSY
12
15
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
12
15
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
30
25
45
30
ns
tDDD
ns
4851 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6.1402
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
t
DH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
t
BAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
4851 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Truth Table I - Chip Enable.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
.
4851 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
6.42
11
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1,3)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
tBDC
BUSY"B"
4851 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
t
BAA
tBDA
BUSY"B"
4851 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable .
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V37L15
70V37L20
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
____
0
____
t
15
15
20
20
____
____
t
Interrupt Reset Time
ns
4851 tbl 15
6.1422
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
t
INS
4851 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
tINR
INT"B"
4851 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Table I - Chip Enable.
Truth Table IV — Interrupt Flag(1,4,5)
Left Port
Right Port
R/W
L
A
14L-A0L
7FFF
X
R/W
R
A
14R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
L
CE
R
OE
R
INTR
L
X
X
X
L
X
X
L
X
X
X
L(3)
H(2)
X
X
L
X
X
L(2)
H(3)
X
R
X
X
L
7FFF
7FFE
X
R
X
X
L
L
X
L
L
7FFE
X
X
X
X
L
4851 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Truth Table I - Chip Enable.
6.42
13
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V —
Address BUSY Arbitration(4)
Inputs
Outputs
A
-A
AOORL-A1144RL
Function
Normal
Normal
Normal
(1)
(1)
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
4851 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V37 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Truth Table I - Chip Enable.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left
D0
- D17 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
4851 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V37.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Truth Table III - Semaphore Read/Write Control.
FunctionalDescription
TheIDT70V37providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
in memory. The IDT70V37 has an automatic power down feature
controlled by CE. The CE0 and CE1 control the on-chip power down
circuitrythatpermitstherespectiveporttogointoastandbymodewhen
not selected (CE=HIGH). Whenaportisenabled, accesstotheentire
memoryarrayispermitted.
(HEX),whereawriteisdefinedasCER=R/WR =VIL pertheTruthTable.
Theleftportclearstheinterruptthroughaccessofaddresslocation7FFE
when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
7FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
the memory location 7FFF. The message (18 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAM location. If the interrupt
functionisnotused, addresslocations7FFEand7FFFarenotusedas
mailboxes,butaspartoftherandomaccessmemory.RefertoTruthTable
IV fortheinterruptoperation.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)isassignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 7FFE
6.1442
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted data in the
slave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
TheIDT70V37isanextremelyfastDual-Port32Kx18CMOSStatic
RAMwithanadditional8addresslocationsdedicatedtobinarysemaphore
TheuseofBUSYlogicisnotrequiredordesirableforallapplications. flags.TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether PortRAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefined
and use any BUSY indication as an interrupt source to flag the event of bythesystemdesigner’ssoftware.Asanexample,thesemaphorecan
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis beusedbyoneprocessortoinhibittheotherfromaccessingaportionof
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave the Dual-Port RAM or any other shared resource.
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
TheDual-PortRAMfeaturesafastaccesstime,withbothportsbeing
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying completelyindependentofeachother.Thismeansthattheactivityonthe
the BUSY pins HIGH. If desired, unintended write operations can be leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
prevented to a port by tying the BUSY pin for that port LOW.
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom
TheBUSYoutputsontheIDT70V37RAMinmastermode,arepush- orwrittentoatthesametimewiththeonlypossibleconflictarisingfromthe
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese simultaneous writing of, or a simultaneous READ/WRITE of, a non-
RAMs are being expanded in depth, then the BUSY indication for the semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
resulting array requires the use of an external AND gate.
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected.Thisistheconditionwhichisshownin
Truth Table III where CE and SEM are both HIGH.
A15
CE0
CE0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
L
BUSYL
SystemswhichcanbestusetheIDT70V37containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
a performance increase offered by the IDT70V37s hardware sema-
phores,whichprovidealockoutmechanismwithoutrequiringcomplex
programming.
CE
1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
L
BUSY
L
BUSYR
BUSY
R
.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT70V37doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
4851 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V37 RAMs.
Width Expansion with Busy Logic
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
Master/SlaveArrays
WhenexpandinganIDT70V37RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSY signal as a write inhibit signal. Thus on the IDT70V37 RAM the
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)asshown
in Figure 3.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatasharedresourceisinuse.Ifthe
leftprocessorwantstousethisresource,itrequeststhetokenbysetting
thelatch. Thisprocessorthenverifiesitssuccessinsettingthelatchby
readingit. Ifitwassuccessful,itproceedstoassumecontrolovertheshared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
6.42
15
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
shared resource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
performanothertaskandoccasionallyattemptagaintogaincontrolofthe
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished
thetoken,theleftsideshouldsucceedingainingcontrol.
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
TheeightsemaphoreflagsresidewithintheIDT70V37inaseparate
memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed
byplacingalowinputontheSEMpin(whichactsasachipselectforthe
semaphoreflags)andusingtheothercontrolpins(Address,CE,andR/
W)astheywouldbeusedinaccessingastandardStaticRAM. Eachof
the flags has a unique address which can be accessed by either side
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table VI). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
4851 drw 18
Figure 4. IDT70V37 Semaphore Logic
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
thesametime,theassignmentwillbearbitrarilymadetooneportorthe
other.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
or misinterpreted, a software error can easily happen.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTable
VI). As an example, assume a processor writes a zero to the left port at
afreesemaphorelocation.Onasubsequentread,theprocessorwillverify
thatithaswrittensuccessfullytothatlocationandwillassumecontrolover
the resource in question. Meanwhile, if a processor on the right side
attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
6.1462
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
A
XXXXX
A
999
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I(1)
G(2)
PF
Green
100-pin TQFP (PN100)
15
20
Commercial Only
Commercial & Industrial
Speed in nanoseconds
L
Low Power
70V37 576K (32K x 18) Dual-Port RAM
4851 drw 19
NOTES:
1. ContactyoursalesofficeforIndustrialTemperaturerangeinotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.
DatasheetDocumentHistory:
08/01/99:
01/02/02:
InitialPublicOffering
Page 1 & 17 Replaced IDT logo
Page 3 Increasedstoragetemperatureparameter
ClarifiedTA Parameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Added Truth Table I - Chip Enable as note 5
Corrected±200mVto0mVinnotes
Page 5, 7, 10 & 12 Added Industrial Temperature range for 20ns to DC & AC Electrical Characteristics
RemovedPreliminarystatus
06/17/04 :
08/15/08:
Page 1 & 17 Replaced old logo with new TM logo
Page 2 Added date revision to pin configuration
Page 2 - 5 Changed naming conventions from VCC to VDD and from GND to VSS
Page 1 Addedgreenavailabilitytofeatures
Page 17 Addedgreenindicatortoorderinginformation
Page 1 & 17 Updated old TM logo with new logo
01/19/09:
06/18/15:
Page 17 Removed "IDT" from orderable part number
Page 2 RemovedIDTinreferencetofabrication
Page 2 Removeddatefromthe100-pinTQFPconfiguration
Page 2 & 17 The package code PN100-1 changed to PN100 to match standard package codes
Page 17 AddedTape&ReelindicatortotheOrderingInformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
17
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| 70V37L20PFG | IDT | Dual-Port SRAM, 32KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100 | 获取价格 |
|
| 70V37L20PFG8 | IDT | Application Specific SRAM, 32KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100 | 获取价格 |
|
| 70V37L20PFGI | IDT | HIGH-SPEED 3.3V 32K x 18 DUAL-PORT STATIC RAM | 获取价格 |
|
| 70V37L20PFGI8 | IDT | HIGH-SPEED 3.3V 32K x 18 DUAL-PORT STATIC RAM | 获取价格 |
|
| 70V38 | RENESAS | 64K x 18 3.3V Dual-Port RAM | 获取价格 |
|
| 70V38L15PFG | IDT | HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM | 获取价格 |
|
| 70V38L15PFG8 | IDT | HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM | 获取价格 |
|
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