70V5378S133BGI [IDT]
PBGA-272, Tray;
| 型号： | 70V5378S133BGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PBGA-272, Tray 时钟 静态存储器 内存集成电路 |
| 文件： | 总29页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 64/32K X 18
SYNCHRONOUS
IDT70V5388/78
FOURPORT™ STATIC RAM
Features
◆
Counter wrap-around control
– Internal mask register controls counter wrap-around
– Counter-Interrupt flags to indicate wrap-around
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and
256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
◆
True four-ported memory cells which allow simultaneous
access of the same memory location
Synchronous Pipelined device
◆
◆
◆
◆
◆
◆
– 64/32K x 18 organization
◆
◆
Pipelined output mode allows fast 200MHz operation
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x
4 ports)
◆
◆
◆
◆
◆
◆
LVTTL I/O interface
High-speed clock to data access 3.0ns (max.)
3.3V Low operating power
Interrupt flags for message passing
Width and depth expansion capabilities
Counter readback on address lines
◆
◆
◆
◆
MBIST (Memory Built-In Self Test) controller
Green parts available, see ordering information
Port - 1 Logic Block Diagram(2)
R/
W
P1
0
1
1/0
UBP1
CE0P1
CE1P1
LBP1
OEP1
I/O9P1 - I/O17P1
I/O0P1 - I/O8P1
Port 1
I/O
Control
TRST
TMS
JTAG
TCK
TDI
Controller
MBIST
TDO
CLKMBIST
Addr.
Read
Back
Port 1
Readback
Register
MRST
(1)
A
0P1 - A15P1
Port 1
Mask
,
Register
CNTRDP1
MKRDP1
MKLDP1
Port 1
Address
Decode
64KX18
Memory
Array
Priority
Decision
Logic
Port 1
CNTINCP1
CNTLDP1
CNTRSTP1
Counter/
Address
Register
CLKP1
R/
WP1
Port 1
Interrupt
Logic
CE0P1
CE1P1
CLKP1
MRST
CNTINTP1
INTP1
MRST
5649 drw 01
NOTE:
1. A15x is a NC for IDT70V5378.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
OCTOBER 2008
1
DSC-5649/5
©2008IntegratedDeviceTechnology,Inc.
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Description
TheIDT70V5388/78isahigh-speed64/32Kx18bit tions specially designed to facilitate system operations.
synchronous FourPort RAM. The memory array utilizes These include full-boundary, maskable address counters
FourPort memory cells to allow simultaneous access of with associated interrupts for each port, mailbox interrupt
anyaddressfromallfourports.Registersoncontrol,data, flags on each port to facilitate inter-port communications,
andaddressinputsprovideminimalsetupandholdtimes. Memory Built-In Self-Test (MBIST), JTAG support and an
The timing latitude provided by this approach allows sys- asynchronous Master Reset to simplify device initializa-
tems to be designed with very short cycle times.
tion. In addition, the address lines have been set up as I/O
With an input data register and integrated burst pins,topermitthesupportofCNTRD (theabilitytooutputthe
counters,the70V5388/78hasbeenoptimizedforapplica- currentvalueoftheinternaladdresscounterontheaddress
tions having unidirectional or bi-directional data flow in lines)andMKRD(theabilitytooutputthecurrentvalueofthe
bursts.Anautomaticpowerdownfeature,controlledbyCE0 counter mask register). For specific details on the device
andCE1,permitstheon-chipcircuitryofeachporttoenter operation, please refer to the Functional Description and
a very low standby power mode.
TheIDT70V5388/78providesawiderangeoffunc-
subsequent explanatory sections, beginning on page 21.
2
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
(4)
PinConfiguration
70V5388/78BG
BG-272(2)
272-Pin BGA
Top View(3)
09/25/02
1
LB
2
I/O17
P2
3
I/O15
4
I/O13
5
I/O11
6
I/O9
7
I/O16
P1
8
9
10 11 12 13 14 15 16 17 18 19 20
I/O14 I/O12
P1
I/O10
P1
I/O16
P4
LB
P4
I/O10
P4
I/O12 I/O14
P4 P4
I/O
P3
9
I/O11
P3
I/O13
P3
I/O15
P3
I/O17
P3
A
B
C
D
E
F
A
B
C
D
E
F
P1
P2
P2
P2
P2
P1
I/O16
P2
I/O14
P2
I/O12
P2
I/O10
P2
I/O17
P1
I/O13
P1
I/O11
P1
I/O11 I/O13
P4 P4
I/O17
P4
UB
P1
I/O10
P3
I/O12
P3
I/O14
P3
I/O16
P3
UB
P4
V
DD
TMS
TCK
TDI
V
DD
(1)
15
(1)
CE1
P4
A
A14
P4
I/O
9
CE
0
A
P1
14
I/O15
P1
I/O15
P4
R/W
P4
A15
CE0
P1
CE
1
R/W
P1
I/O
P4
9
V
SS
TDO
VSS
V
SS
V
V
SS
SS
P4
P1
P4
P1
P1
A12
OE
P4
A12
A
13
OE
P1
A
13
V
SS
V
DD
VSS
V
SS
V
SS
V
SS
V
DD
VDD
V
DD
VDD
VDD
V
SS
VSS
P4
P1
P1
P4
A
P1
10
A11
P1
MKRD CNTRD
P1
A
11
A10
CNTRD MKRD
P4
P1
P4
P4
P4
A
P1
7
A8
P1
A9
P1
CNTINT
P1
A
8
A7
P4
A9
P4
CNTINT
P4
P4
A
P1
5
A6
P1
CNTINC
P1
A
P4
5
A
P4
6
CNTINC
P4
V
SS
V
SS
G
H
J
G
H
J
A
P1
3
A4
P1
MKLD CNTLD
P1 P1
A
P4
4
A
P4
3
CNTLD MKLD
P4 P4
A
P1
1
A
2
A2
P4
A
P4
1
GND(5) GND(5) GND(5)
GND(5)
V
DD
V
DD
VDD
VDD
P1
CLK
P1
CLK
P4
GND(5)
A
P1
0
GND(5) GND(5) GND(5)
CNTRST
P4
INT CNTRST
P1 P1
INT
P4
A
P4
0
K
L
K
L
GND(5) GND(5) GND(5) GND(5)
A
P2
0
INT CNTRST
P2 P2
CNTRST
P3
INT
P3
A0
P3
V
SS
VSS
,
GND(5)
GND(5) GND(5) GND(5)
A
P2
1
A
P2
2
CLK
P2
CLK
P3
A2
P3
A
P3
1
V
DD
V
DD
M
N
P
R
T
M
N
P
R
T
A
P2
3
A4
P2
A
P3
4
A
P3
3
MKLD CNTLD
P2
CNTLD MKLD
P3
P3
P2
A
P2
5
A
P2
6
A6
P3
A
P3
5
CNTINC
P2
CNTINC
P3
V
SS
V
SS
A
P2
7
A8
P2
A
8
A
9
A
9
A
P3
7
CNTINT
P2
CNTINT
P3
P3
P2
P3
A
P2
10
A11
P2
MKRD
P3
A11
P3
MKRD CNTRD
P2
CNTRD
P3
A
P3
10
P2
A
P3
12
OE
P3
A
P2
12
A
P2
13
OE
P2
A13
P3
V
SS
V
DD
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
VDD
V
SS
U
V
W
Y
U
V
(1)
A15
P3
A
P3
14
CE
1
I/O
P2
0
(1)
15
CE
0
A
P2
14
I/O
P2
6
I/O
P3
6
R/W
P3
CE
0
CE
P2
1
R/W
P2
I/O
P3
0
A
V
SS
NC
V
SS
TRST
MRST
V
SS
VSS
P3
P3
P2
P2
I/O
5
I/O
P1
3
I/O
P1
1
I/O
P1
7
I/O
P2
8
I/O
P2
4
I/O
P2
2
I/O
P3
2
I/O
P3
4
I/O8
P3
UB
P2
I/O
P4
1
I/O
3
I/O
5
I/O
7
CLKMBIST
UB
P3
V
DD
W
V
DD
P1
P4
P4
P4
.
I/O
P1
8
LB
P2
I/O
P1
6
I/O4
P1
I/O
P1
2
I/O0
P1
I/O
P2
7
I/O
P2
5
I/O
P2
3
I/O
P2
1
I/O
P3
7
LB
P3
I/O
P3
1
I/O
P3
3
I/O
P3
5
I/O
P4
0
I/O
2
I/O
4
I/O
6
I/O
P4
8
Y
P4
P4
P4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
5649 drw 03
NOTES:
1. A15x is a NC for IDT70V5378.
2. This package code is used to reference the package diagram.
3. This text does not indicate orientation of the actual part marking.
4. Package body is approximately 27mm x 27mm x 2.33mm, with 1.27mm ball-pitch.
5. Central balls are for thermal dissipation only. They are connected to device VSS.
3
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
(2)
PinConfiguration
70V5388/78BC
BC-256(3)
256-Pin BGA(4)
Top View
09/25/02
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
OE
LB
I/O16 I/O13 I/O
9
I/O10
P1
R/W
I/O
9
I/O11
P3
I/O12 I/O16
CE1
I/O14
P1
I/O15 I/O17
UB
A
B
P2
P2
P2
P1
P1
P4
P1
P4
P4
P4
P3
P3
P4
A
B
(1)
15
I/O17
P4
CE0
P4
CE
1
I/O17
P2
I/O10 I/O15 I/O11
P2
I/O12 I/O16
P3
A
I/O13
P4
R/W
P4
UB
P1
I/O14
P2
LB
TDI
P1
P1
P1
P3
P1
P4
(1)
15
P4
I/O12 I/O17 I/O12 I/O
9
P1
I/O14
P3
A
A
14
P4
A
14
P1
A
13
P1
I/O15
P2
CE
0
I/O11 I/O15 I/O10
OE
P4
TDO
C
P2
P1
P1
C
P3
P1
P4
P4
A
10
P1
A
12
P1
A
11
P1
A
9
P1
I/O13
P3
I/O13
P1
I/O10
P4
I/O11 I/O16
I/O9
I/O14
P4
A
11
P4
A
12
P4
A
13
P4
TCK
TMS
D
E
P1
P2
P3
D
E
A
P1
6
A
P1
5
A
P4
10
A
P1
8
A
6
P4
A
7
P4
A
P4
8
A9
P4
A
P1
7
V
DD
V
DD
SS
VDD
VDD
V
DD
DD
VDD
VDD
A
P1
3
A
P1
4
A
P1
2
A
1
P4
A
P4
3
A
P1
1
A
2
P4
A
P4
5
A
P4
4
V
DD
V
DD
V
V
SS
SS
VSS
V
VDD
F
F
CLK
P1
A
P1
0
CNTINC
P1
CNTRD
P1
A
P4
0
CLK
P4
CNTINC CNTRD
P4
CNTLD
P4
G
V
DD
VSS
VSS
VSS
VSS
V
VSS
VSS
VSS
G
P4
CNTRST
P1
CNTLD
SS
CNTINT
P1
CNTRST
P4
MKRD
P4
INT
P4
INT
P1
CNTINT
P4
MKLD
P1
MKLD
P4
VSS
V
VSS
VSS
VSS
H
J
P1
H
J
CNTRST
P3
CLK
P2
INT CNTINT
P3
CNTRST
P2
CLK
P3
CNTINT
P2
MKLD
P3
INT
P2
MKRD
P1
VSS
VSS
V
SS
SS
V
SS
SS
VSS
P3
CNTINC
P2
A0
P3
CNTRD
P2
CNTLD
P2
MKRD
P2
MKLD
P2
CNTINC
P3
CNTLD
P3
MKRD
P3
CNTRD
P3
K
L
VSS
VSS
VSS
V
V
VSS
K
L
A
1
A
P2
3
A
P2
2
A
P2
1
A
P3
3
A
P3
4
A2
P3
A
P2
4
A0
P2
V
DD
V
DD
DD
V
SS
V
DD
VDD
VSS
VSS
P3
A
P2
6
A
5
P2
A
5
A8
P3
A
P2
8
A
P2
9
A
P2
7
A
P3
7
A
6
P3
M
N
P
R
T
VDD
V
VDD
VDD
VDD
VDD
VDD
M
N
P
R
T
P3
A
P2
10
I/O
P1
5
A9
P3
A
11
A
P2
12
I/O
1
P1
I/O
6
P2
I/O
2
I/O
3
A
P3
11
A
P3
12
A
10
P3
I/O
7
I/O
2
P4
CLKMBIST
TRST
MRST
P2
P2
P3
P3
A
P2
13
I/O
2
P1
I/O3
P2
I/O
0
P3
A
14
P2
I/O
P1
7
I/O
7
I/O
3
P4
I/O
4
I/O
8
A
P3
13
I/O
6
R/W
P2
CE
P3
0
A
P3
14
P2
P3
P3
P4
(1)
(1)
A15
P3
I/O
P1
8
I/O
4
P1
I/O2
P3
A
15
P2
CE
P2
1
UB
P2
I/O
0
P1
I/O5
P2
I/O
1
I/O7
P4
I/O
1
I/O
6
P3
CE
P3
1
I/O
5
P4
UB
P3
P4
P2
I/O
P1
6
I/O
3
P1
I/O
8
P2
I/O
0
LB
P3
LB
P2
OE
P3
I/O
4
I/O
1
I/O5
P3
CE
P2
0
OE
P2
I/O
0
I/O4
P4
I/O
8
R/W
P3
P2
P2
P3
P4
P4
7
1
2
3
4
5
6
8
9
10 11 12 13 14 15 16
5649 drw 04
NOTES:
1. A15x is a NC for IDT70V5378.
2. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
3. This package code is used to reference the package diagram.
4. This text does not indicate orientation of the actual part-marking.
4
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Pin Definitions
Port 1
Port 2
Port 3
Port 4
Description
Address Inputs. In the CNTRD and MKRD operations, these pins serve
as outputs for the internal address counter and the internal counter mask
register respectively.
(1)
(1)
(1)
(1)
A0P1 - A15P1
A0P2 - A15P2
A0P3 - A15P3
A0P4 - A15P4
I/O0P1 - I/O17P1
CLKP1
I/O0P2 - I/O17P2
CLKP2
I/O0P3 - I/017P3 I/O0P4 - I/O17P4 Data Bus Input/Output.
CLKP3
CLKP4
Clock Input. The maximum clock input rate is fMAX. The clock signal can
be free running or strobed depending on system requirements.
Master Reset Input. MRST is an asycnchronous input, and affects all
ports. It must be asserted LOW (MRST = VIL) at initial power-up. Master
Reset sets the internal value of all address counters to zero, and sets
the counter mask registers for each port to 'unmasked'. It also resets the
output flags for the mailboxes and the counter interrupts (INT = CNTINT
= VIH) and deselects all registered control signals.
MRST
Chip Enable Inputs. To activate any port, both signals must be asserted
= VIH). A given port is disabled if
= VIH and/or CE = VIL).
CE0P1, CE1P1
R/WPI
CE0P2, CE1P2
R/WP2
CE0P3, CE1P3
R/WP3
CE0P4, CE1P4
R/WP4
to their active states (CE
0
= VIL, CE
1
either chip enable is deasserted (CE
0
1
Read/Write Enable Input. This signal is asserted LOW (R/W = VIL) in
order to write to the FourPort memory array, and it is asserted HIGH
(R/W = VIH) in order to read from the array.
Lower Byte Select Input (I/O0 - I/O8). Asserting this signal LOW (LB = VIL)
LBP1
LBP3
UBP3
LBP2
UBP2
LBP4
UBP4
enables read/write operations to the lower byte. For read operations, this
signal is used in conjunction with OE in order to drive output data on the
lower byte of the data bus.
Upper Byte Select Input (I/O
V
9
- I/O17). Asserting this signal LOW (LB =
IL) enables read/write operations to the upper byte. For read
UBP1
operations, this signal is used in conjunction with OE in order to drive
output data on the upper byte of the data bus.
Output Enable Input. Asserting this signal LOW (OE = VIL) enables the
device to drive data on the I/O pins during read operation. OE is an
asychronous input.
OEP1
OEP2
OEP3
OEP4
Counter Load Input. Asserting this signal LOW (CNTLD = VIL) loads the
address on the address lines (A
counter for that port.
CNTLDP1
CNTLDP2
CNTLDP3
CNTLDP4
0
- A15(1)) into the internal address
Counter Increment Input. Asserting this signal LOW (CNTINC = VIL
)
increments the internal address counter for that port on each rising edge
of the clock signal. The counter will increment as defined by the counter
mask register for that port (default mode is to advance one address on
each clock cycle).
CNTINCP1
CNTRDP1
CNTINCP2
CNTRDP2
CNTINCP3
CNTRDP3
CNTINCP4
CNTRDP4
Counter Readback Input. When asserted LOW (CNTRD = VIL) causes that
port to output the value of its internal address counter on the address
lines for that port. Counter readback is independent of the chip enables
for that port. If the port is activated (CE0 = VIL and CE1 = VIH), during the
counter readback operation, then the data bus will output the data
associated with that readback address in the FourPort memory array
(assuming that the byte enables and output enables are also asserted).
Truth Table III indicates the required states for all other counter controls
during this operation. The specific operation and timing of this funcion is
described in detail in the text.
Counter Reset Input. Asserting this signal LOW (CNTRST = VIL) resets
the address counter for that port to zero.
CNTRSTP1
CNTINTP1
CNTRSTP2
CNTINTP2
CNTRSTP3
CNTINTP3
CNTRSTP4
CNTINTP4
Counter Interrupt Flag Output. This signal is asserted LOW (CNTINT =
VIL) when the internal address counter for that port 'wraps around' from
max address [(the counter will increment as defined by the counter mask
register for that port (default mode is to advance one address on each
clock cycle)] to address min. as the result of counter increment (CNTINT
= VIL). The signal goes LOW for one clock cycle, then automatically
resets.
5649 tbl 01
5
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Pin Definitions (con't.)
Port 1
Port 2
Port 3
Port 4
MKLDP4
Description
Counter Mask Register Load Input. Asserting this signal LOW (MKLD =
IL) loads the address on the address lines (A0
- A15(1)) into the counter
MKLDP1
MKLDP2
MKLDP3
V
mask register for that port. Counter mask register operations are
described in detail in the text.
Counter Mask Register Readback Input. Asserting this signal LOW
(MKRD = VIL) causes that port to output the value of its internal counter
MKRDP1
MKRDP2
MKRDP3
MKRDP4
mask register on the address lines (A0
- A15(1)) for that port. Address
Counter and Counter-Mask Operational Table indicates the required
states for all other counter controls during this operation. Counter mask
register readback is independent of the chip enables for that port. If the
port is activated (CE0 = VIL and CE1 = VIH) during the counter mask
register readback operation, then the data bus will output the data
associated with that address in the FourPort memory array ( assuming
that the byte enables and output enables are also asserted). The specific
operation and timing of this function is described in detail in the text.
Interrupt Flag Output. The FourPort is equipped with mailbox functions:
each port has a specific address wthin the memory array which, when
written by any of the other ports, will generate an interrupt flag to that
port. The port clears its interrupt by reading that address. The memory
location is a valid address for data storage: a full 18-bit word can be
stored for recall by the target port or any other port. The mailbox
functions and associated interrupts are described in detail in the text.
INTP1
INTP2
INTP3
INTP4
TMS
JTAG Input: Test Mode Select
JTAG Input: Test Mode Reset (Intialize TAP Controller and reset the
MBIST Controller)
TRST
TCK
JTAG Input: Test Clock
TDI
JTAG Input: Test Data Input (serial)
JTAG Output: Test Data Output (serial)
MBIST Input: MBIST Clock
TDO
CLKMBIST
GND
Thermal Grounds (should be treated like VSS
)
V
DD
Core Power Supply (3.3V)
Electrical Grounds (0V)
VSS
5649 tbl 02
NOTE:
1. A15x is a NC for IDT70V5378.
6
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte Lower Byte
CLK
↑
CE
1
R/W
X
X
X
L
I/O9-17
High-Z
High-Z
High-Z
High-Z
I/O0-8
High-Z
High-Z
High-Z
MODE
Deselected–Power Down
Deselected–Power Down
All Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to Both Bytes
OE
X
X
X
X
X
X
L
CE
0
UB
X
X
H
H
L
LB
X
X
H
L
H
X
L
L
L
L
L
L
L
X
X
L
↑
H
H
H
H
H
H
H
X
↑
DIN
↑
H
L
L
DIN
High-Z
↑
L
L
DIN
DIN
↑
H
L
L
H
H
H
X
High-Z
DOUT
Read Lower Byte Only
Read Upper Byte Only
Read Both Bytes
↑
L
H
L
DOUT
High-Z
↑
L
L
DOUT
DOUT
↑
H
X
X
High-Z
High-Z
Outputs Disabled
↑
5649 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CNTLD, CNTINC, CNTRST = VIH.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter & Mask Control(1,2)
Previous Internal
External
Address
Internal Address
MODE
Address
Used
CLK
↑
I/O
I/O(0)
I/O(p)
CNTLD CNTINC CNTRST
MKLD
X
(3)
X
An
An
An
X
X
0
X
X
X
X
X
H
L
D
Counter Reset to Address 0
Counter disabled (Ap reused)
I/O (n) External Address Used
External Address Blocked—Counter disabled (Ap reused)
Ap
Ap
An
Ap
H
L
D
↑
(3)
X
↑
L
H
H
H
H
H
H
D
Ap
H
DI/O(p)
↑
(5)
(4)
(5)
Ap
Ap + 1
L
H
DI/O(p+1) Counter Enabled—Internal Address generation
↑
5649 tbl 04
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, LB, UB and OE.
3. CNTLD and CNTRST are independent of all other memory control signals including CE0, CE1 and LB, UB.
4. The address counter advances if CNTINC = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, LB, UB.
5. The counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle).
7
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
AddressCounterandCounter-MaskControlOperationalTable
(Any Port)(1,2)
CLK
MRST CNTRST MKLD
CNTLD CNTINC CNTRD
MKRD
Mode
Operation
Master- Counter/Address Register Reset and Mask Register
Reset Set (resets chip as per reset state definition)
X
L
X
X
X
X
X
X
↑
↑
H
H
L
X
L
X
X
X
X
X
X
X
X
Reset Counter/Address Register Reset
H
Load
Load
Load of Address Lines into Mask Register
Load of Address Lines into Counter/Address
Register
H
H
H
H
H
X
H
H
X
L
H
X
X
L
X
X
L
X
X
X
↑
↑
↑
Increment Counter Increment
Read- Readback Counter on Address Lines
back
X
Read-
H
H
X
H
X
X
H
X
H
H
X
L
Readback Mask Register on Address Lines
back
↑
↑
(3)
X
Hold
Counter Hold
H
5649 tbl 05
NOTES:
1. "X" = "don't care", "H" = VIH, "L" = VIL.
2. Counter operation and mask register operation is independent of Chip Enable.
3. MKLD = VIL will also hold the counter. Please refer to Truth Table II.
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage(1)
Ambient
Symbol
Parameter
Min. Typ.
Max.
3.45
0
Unit
Grade
Temperature
0OC to +70OC
-40OC to +85OC
GND
VDD
V
DD
SS
IH
Supply Voltage
3.15 3.3
V
Commercial
0V
3.3V
3.3V
+
+
150mV
150mV
V
Ground
0
0
V
Industrial
0V
(2)
____
Input High Voltage
2.0
VDD + 150mV
V
V
5649 tbl 06
(Address, Control & I/O Inputs)
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
-0.3(1)
0.8
V
____
VIL
Input Low Voltage
5649 tbl 07
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDD + 150mV.
8
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
AbsoluteMaximumRatings(1)
(TA = +25°C, F = 1.0MHZ)
Symbol
Rating
Commercial
& Industrial
Unit
V
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
Max. Unit
(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
CIN
V
8
pF
pF
V
TERM
(3)
OUT
C
VOUT = 3dV
10.5
Temperature Under Bias
-55 to +125
oC
(3)
T
BIAS
STG
JN
OUT
5649 tbl 09
NOTES:
T
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
oC
oC
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
T
I
50
mA
3. COUT also references CI/O.
5623 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
3. Ambient Temperature under DC Bias. No AC conditions. Chip Deselected.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V5388/78S
Symbol
Parameter
Test Conditions
DD = Max., VIN = 0V to VDD
DD = Max., VIN = 0V to VDD
OUT = 0V to VDD, Outputs in tri-state mode
OL = +4mA, VDD = Min.
OH = -4mA, VDD = Min.
Min.
Max.
10
Unit
µA
µA
µA
V
Input Leakage Current(1)
V
___
___
___
___
|ILI
|ILI
|ILO
|
(1,2)
|
JTAG Input Leakage Current
V
30
(1)
|
Output Leakage Current
V
10
VOL
Output Low Voltage
Output High Voltage
I
0.4
___
VOH
I
2.4
V
5649 tbl 10
NOTE:
1. At VDD < 2.0V leakages are undefined.
2. Applicable only for TMS, TDI and TRST inputs.
9
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V5388/78S200 70V5388/78S166 70V5388/78S133 70V5388/78S100
Com'l Only
Com'l
& Ind
Com'l
& Ind
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
405
Max.
470
Typ.(4)
Max.
395
400
190
195
240
245
15
Typ.(4)
Max.
320
325
155
160
195
200
15
Typ.(4)
Max. Unit
CE1 = CE2 = CE3 = CE4 ,
(5) = VIL
IDD
Dynamic Operating
Current (All
Ports Active)
S
S
S
S
S
S
S
S
S
S
340
340
160
160
210
210
1.5
275
275
130
130
170
170
1.5
205
205
100
100
130
130
1.5
1.5
130
130
240
mA
245
Outputs Disabled,
f = fMAX
___
___
(1)
IND
CE1 = CE2 = CE3 = CE
4
(5) = VIH,
ISB1
Standby Current
(All Ports - TTL
Level Inputs)
COM'L
IND
195
225
120
mA
125
Outputs Disabled,
___
___
(1)
f = fMAX
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE
A
= VIL and CEB = CEC = CED = VIH
Active Port, Outputs Disabled,
COM'L
IND
250
290
150
mA
155
___
___
(1)
f=fMAX
ISB3
Full Standby Current (All All Ports Outputs Disabled,
Ports - CMOS
Level Inputs)
COM'L
IND
1.5
15
15
CE(5) > VDD - 0.2V, VIN > VDD - 0.2V
mA
___
___
(2)
1.5
15
1.5
15
15
or VIN < 0.2V, f = 0
(5)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
CE
V
A
< 0.2V and CEB = CEC = CE
D
> VDD - 0.2V
COM'L
IND
250
290
210
210
240
245
170
170
195
200
150
mA
155
IN > VDD - 0.2V or VIN < 0.2V
___
___
(1)
Active Port, Outputs Disabled, f = fMAX
5649 tbl 11
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Parameters are identical for all ports.
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V
"X" represents indicator for appropriate port.
10
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V
GND to 3.0V
2ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figure 1
5649 tbl 12
50Ω
50Ω
,
DATAOUT
1.5V
10pF
(Tester)
5649 drw 05
Figure 1. AC Output Test Load
*(For tLZ, tHZ, tWZ, tOW)
7
6
5
∆
tCD
(Typical, ns)
4
3
2
1
0
0
20
40
60
80
100
120
140
160
5649 drw 07
∆
Capacitance (pF) from AC Test Load
Figure 2. Typical Output Derating (Lumped Capacitive Load).
11
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V5388/78S200
Com'l Only
70V5388/78S166
Com'l
70V5388/78S133
Com'l
70V5388/78S100
Com'l
& Ind
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
f
MAX
CYC2
CH2
CL2
SA
HA
SC
HC
SW
HW
SD
HD
SB
HB
SCLD
HCLD
SCINC
HCINC
SCRST
HCRST
SCRD
HCRD
SMLD
HMLD
SMRD
HMRD
OE
OLZ(1 5)
OHZ (1,5)
CD2
CA2
CM 2
DC
CKHZ (1,2,5)
CKLZ (1,2,5)
2
Maximum Frequency
Clock Cycle Time
200
166
133
100
____
____
____
____
t
5
6
7.5
2.6
2.6
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
10
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Clock HIGH Time
2.0
2.0
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
2.1
2.1
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
t
Clock LOW Time
4
t
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
2
t
0.7
2
t
t
0.7
2
t
t
R/W Hold Time
0.7
2
t
Input Data Setup Time
Input Data Hold Time
Byte Setup Time
t
0.7
2
t
t
Byte Hold Time
0.7
2
t
CNTLD Setup Time
t
0.7
2
CNTLD Hold Time
t
CNTINC Setup Time
CNTINC Hold Time
t
0.7
2
t
CNTRST Setup Time
CNTRST Hold Time
CNTRD Setup Time
CNTRD Hold Time
t
0.7
2
t
t
0.7
2
t
MKLD Setup Time
t
0.7
2
MKLD Hold Time
t
MKRD Setup Time
t
0.5
0.5
0.5
0.7
MKRD Hold Time
____
____
____
____
t
Output Enable to Data Valid
OE to LOW-Z
4.0
4.0
4.2
5
,
____
____
____
____
t
1
1
1
1
t
1
3.4
3.0
3.4
1
3.6
3.2
3.6
1
4.2
3.4
4.2
1
4.5
3.6
5
OE to HIGH-Z
____
____
____
____
t
Clock to Data Valid
____
____
____
____
____
____
____
____
t
Clock to Counter Address Readback Valid
Clock to Mask Register Readback Valid
Data Output Hold After Clock HIGH
Clock HIGH to Output HIGH-Z
Clock HIGH to Output LOW-Z
t
3.4
3.6
4.2
5
____
____
____
____
t
1
1
1
1
1
1
1
1
1
1
1
1
t
3
3
3
3
____
____
____
____
t
5649 tbl 13a
12
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V5388/78S200
Com'l Only
70V5388/78S166
Com'l
70V5388/78S133 70V5388/78S100
Com'l
& Ind
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Interrupt Timing
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SINT
RINT
SCINT
RCINT
Clock to INT Set Time
5
5
5
5
6
6
6
6
7.5
7.5
7.5
7.5
10
10
10
10
ns
ns
ns
ns
t
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset Time
t
t
Master Reset Timing
____
____
____
____
____
____
____
____
t
RS
RSR
ROF
Master Reset Pulse Width
7.5
7.5
7.5
10
ns
ns
ns
t
Master Reset Recovery Time
7.5
7.5
7.5
10
____
____
____
____
t
Master Resetto Output Flags Reset Time
6.5
6.5
6.5
8
Port to Port Delays
____
____
____
____
CCS(3)
Clock-to-Clock Setup Time
4.5
5
6.5
9
ns
t
JTAG Timing(4
)
____
____
____
____
Maximum JTAG TAP Controller Frequency
TCK Clo ck Cycle Time
TCK Clo ck High Time
TCK Clo ck Low Time
JTAG Setup
10
10
10
10
MHz
ns
f
JTAG
____
____
____
____
100
100
100
100
tTCYC
____
____
____
____
t
TH
TL
JS
JH
JCD
40
40
20
40
40
20
40
40
20
40
40
20
ns
____
____
____
____
____
____
____
____
ns
t
ns
t
____
____
____
____
20
20
20
20
t
JTAG Hold
ns
____
____
____
____
t
TCK Clock Low to TDO Valid (JTAG Data Output)
20
20
20
20
ns
____
____
____
____
0
0
ns
t
JDC
TCK Clock Low to TDO Invalid (JTAG Data Output Hold)
Maximum CLKMBIST Frequency
0
0
____
____
____
____
fBIST
200
166
133
100
MHz
ns
____
____
____
____
2
2.5
3
4
t
BH
BL
JRST
JRSR
CLKMBIST High Time
CLKMBIST Low Time
JTAG Reset
____
____
____
____
____
____
____
____
____
____
____
____
2
2.5
50
3
4
t
ns
50
50
50
t
ns
50
50
50
50
t
JTAG Reset Recovery
ns
5649 tbl 13b
NOTES:
1. Guaranteed by design (not production tested).
2. Valid for both data and address outputs.
3. This parameter defines the time necessary for one port to complete a write and have valid data available at that address for access from the other port(s).
Attempting to read data before tCCS has elapsed will result in the output of indeterminate data.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
5. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1).
13
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Switching Waveforms
Timing Waveform of Read Cycle(2)
tCYC2
tCH2
t
CL2
CLK
CE
0
t
SC
(3)
tHC
t
SC
t
HC
HB
CE1
t
SB
tHB
t
SB
t
(5)
LB, UB
R/W
t
HW
HA
t
SW
SA
t
t
ADDRESS(4)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (5)
DATAOUT
Qn + 1
(1)
tCKLZ
t
OHZ
tOLZ
OE (1)
,
tOE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. CNTLD = VIL, CNTINC and CNTRST = VIH.
5649 drw 08
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, LB, UB = VIH following the next rising edge of the clock. Refer to Truth Table I.
4. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If LB, UB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A0
A1
tSC tHC
tSC tHC
tCD2
tCD2
tCKHZ
tCD2
Q0
Q3
A5
Q
1
DATAOUT(B1)
tDC
tCKLZ
tDC
tCKHZ
tSA tHA
A6
A4
A3
A2
A0
A1
ADDRESS(B2)
tSC tHC
CE0(B2)
tSC tHC
tCD2
tCKHZ
tCD2
,
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
NOTES:
5649 drw 09
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V5388/78 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. LB, UB, OE, and CNTLD = VIL; CE1(B1), CE1(B2), R/W, CNTINC, and CNTRST = VIH.
14
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Port A Write to Port B Read(1,2,4)
CLK"A"
tSW
tHW
R/W"A"
ADDRESS"A"
DATAIN"A"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
CCS
t
CLK"B"
t
CD2
R/W"B"
t
SW
SA
t
HW
t
tHA
NO
ADDRESS"B"
DATAOUT"B"
MATCH
MATCH
VALID
t
DC
5649 drw 10
NOTES:
1. CE0, LB, UB, and CNTLD = VIL; CE1, CNTINC, CNTRST, MRST, MKLD, MKRD and CNTRD = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCCS < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite
port will be tCCS + 2 tCYC2 + tCD2). If tCCS > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to
valid read on opposite port will be tCCS + tCYC2 + tCD2).
4. All timing is the same for all ports. Port "A" may be any port. Port "B" is any other port on the device.
Timing Waveform of Read-to-Write-to-Read (OE = VIL)(2)
t
CYC2
tCH2
tCL2
CLK
CE0
t
SC
tHC
CE1
t
SB
tHB
LB, UB
tSW tHW
R/W
tSW tHW
(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
t
CD2
t
CD2
(1)
tCKHZ
Qn + 3
Qn
DATAOUT
t
CKLZ
READ
NOP(4)
WRITE
READ
,
5649 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CNTLD = VIL; CNTINC, and CNTRST, MRST, MKLD, MKRD and CNTRD = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
15
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read-to-Write-to-Read (OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
CE1
tSB
tHB
LB, UB
tSW tHW
R/W
t
SW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD2
tCD2
(1)
Qn
Qn + 4
DATAOUT
(4)
tCKLZ
t
OHZ
OE
READ
WRITE
READ
,
5649 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CNTLD = VIL; CNTINC, CNTRST, MRST, MKLD, MKRD and CNTRD = VIH.
3. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK;
numbers are for reference use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSCLD tHCLD
CNTLD
tSCLD tHCLD
CNTINC
SCLD tHCLD
t
tCD2
,
Qn + 2(2)
Qx - 1(2)
Qn + 3
Qn + 1
Qn
Qx
DATAOUT
tDC
READ
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
5649 drw 13
NOTES:
1. CE0, LB and UB = VIL; CE1, CNTRST, MRST, MKLD, MKRD and CNTRD = VIH.
2. If there is no address change via CNTLD = VIL (loading a new address) or CNTINC = VIL (advancing the address), i.e. CNTLD = VIH and CNTINC = VIH, then
the data output remains constant for subsequent clocks.
16
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSCLD tHCLD
CNTLD
tSCINC tHCINC
CNTINC
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5649 drw 14
Timing Waveform of Counter Reset(2)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax
A1
A0
An
An + 1
tSW tHW
R/
W
CNTLD
tSCLD
tHCLD
CNTINC
tSCINC tHCINC
tSCRST tHCRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Q1
Qn
Q0
DATAOUT
EXECUTE(6)
CNTRST
WRITE
READ
READ
READ
A0
READ
A1
A
0
ADDRESS n ADDRESS n+1
5649 drw 15
NOTES:
1. CE0, LB, UB, and R/W = VIL; CE1 and CNTRST, MRST, MKLD, MKRD, and CNTRD = vIH.
CE0, LB, UB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when CNTLD = VIL and equals the counter value when CNTLD = VIH.
4. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during CNTRST operation. A READ or WRITE cycle may be coincidental with the counter CNTRST cycle: Address 0000h will be
accessed. Extra cycles are shown here simply for clarification. For more information on CNTRST function refer to Truth Table II.
7. CNTINC = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address
is written to during this cycle.
17
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Master Reset(1)
t
CYC2
tCH2
t
CL2
CLK
tRS
MRST
tROF
ALL ADDRESS/
DATA LINES
tRSR
(2)
tS
ALL OTHER
INPUTS
INACTIVE
ACTIVE
CNTINT
INT
5649 drw 16
NOTES:
1. Master Reset will reset the device. For JTAG and MBIST reset please refer to the JTAG Timing specification.
2. tS is the set-up time required for all input control signals.
18
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Load and Read Address Counter(1,2,3)
t
CYC2
(2)
(3)
t
CH2 tCL2
CLK
tCA2
tSA
tCKHZ
tCKLZ
tHA
(4)
An+2
An
A0
-
A15
tSCLD
tHCLD
CNTLD
CNTINC
tSCINC
tHCINC
tHCRD
tSCRD
CNTRD
INTERNAL
ADDRESS
A
n+1
An+2
A
n
An+2
An+2
,
tDC
tCD2
Qn+2
DATAOUT
Qn+2
Qx
Qn+1
Qn+2
Qx-1
Qn
READ
INTERNAL
ADDRESS
LOAD
EXTERNAL
ADDRESS
READ DATA WITH COUNTER
5649 drw 17
NOTES:
1. CE0, OE, LB and UB = VIL; CE1, R/W, CNTRST, MRST, MKLD and MKRD = VIH.
2. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle.
3. Address in input mode. Host can drive address bus after tCKHZ.
4. This is the value of the address counter being read out on the address lines.
Timing Waveform of Load and Read Mask Register(1,2,3,4)
t
CYC2
t
CH2 CL2
t
(2)
(1)
CLK
tCA2
tSA
tHA
tCKHZ
tCKLZ
(4)
A
n
A0 - A15
An
tSMLD
tHMLD
MKLD
tSMRD
tHMLD
MKRD
MASK
INTERNAL
VALUE
An
A
n
An
An
A
n
An
,
READ
LOAD
MASK-REGISTER
VALUE
MASK REGISTER
VALUE
5649 drw 18
NOTES:
1. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle.
2. Address in input mode. Host can drive address bus after tCKHZ.
3. CE0, OE, LB and UB = VIL; CE1, R/W, CNTRST, MRST, CNTLD, CNTRD and CNTINC = VIH.
4. This is the value of the mask register being read out on the address lines.
19
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Counter Interrupt(1,3)
t
CYC2
t
CH2 CL2
t
CLK
EXTERNAL
ADDRESS
007Fh
xx7Dh
tHMLD
tSMLD
MKLD
tSCLD
tHCLD
CNTLD
tSCINC
tHCINC
CNTINC
COUNTER
INTERNAL
ADDRESS
xx7Eh
xx7Fh
xx00h
xx7Dh
A
n
xx00h
,
tRCINT
tSCINT
(2)
CNTINT
5649 drw 19
Timing Waveform of Mailbox Interrupt Timing(4,6)
t
CYC2
t
CH2 CL2
t
CLKP1
tSA tHA
PORT-1
ADDRESS
FFFE
An
An+1
An+2
An+3
(5)
tSINT
INTP2 (7)
tRINT
t
CYC2
t
CH2 CL2
t
CLKP2
tSA tHA
PORT-2
ADDRESS
,
FFFE
Am
Am+1
Am+3
A
m+4
(5)
5649 drw 20
NOTES:
1. CE0, OE, LB and UB = VIL; CE1, R/W, CNTRST, MRST, CNTRD and MKRD = VIH.
2. CNTINT is always driven.
3. CNTINT goes LOW as the counter address increments (via CNTINC = VIL) past the maximum value programmed into the mask register and 'wraps around' to xx00h
CNTINT stays LOW for one cycle, then resets. In this example, the mask register was programmed at xx7Fh ('x' indicates "Don't Care"). The Counter Mask Register
operations are detailed on page 24.
4. CNTRST, MRST, CNTRD CNTINC , MKRD and MKLD = VIH. The mailbox interrupt circuitry relies on the state of the chip enables, the read/write signal, and the
address location to generate or clear interrupts as appropriate - other control signals such as OE, LB and UB are "Don't Care". Please refer to Truth Table III (page
22) for further explanation.
5. Address FFFEh is the mailbox location for Port 2 of IDT70V5388. Refer to Truth Table III for mailbox location of other Ports (page 22).
6. Port 1 is configured for a write operation (setting the interrupt) in this example, and Port 2 is configured for a read operation (clearing the interrupt). Ports 1 and 2 are
used for an example: any port can set an interrupt to any other port per the operations in Truth Table III (page 22).
7. The interrupt flag is always set with respect to the rising edge of the writing port's clock, and cleared with respect to the rising edge of the reading port's clock.
20
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
TheIDT70V5388/78providesatruesynchronous
oftCCS mayproduceindeterminatedatafortheread.Twoor
more ports attempting to write the same address location
simultaneouslywillresultinindeterminatedatarecordedat
that address.
Eachportisequippedwithdualchipenables, CE0
and CE1. A HIGH on CE0 or a LOW on CE1 for one clock
cycle on any port will power down the internal circuitry on
thatportinordertoreducestaticpowerconsumption. The
multiplechipenablesalsoalloweasierbankingofmultiple
IDT70V5388/78sfordepthexpansionconfigurations.One
cycleisrequiredwithchipenablesreassertedtoreactivate
the outputs.
FourPort Static RAM interface. Registered inputs provide
minimal set-up and hold times on address, data, and all
critical control inputs. All internal registers are clocked on
therisingedgeoftheclocksignal, however, theself-timed
internal write pulse is independent of the LOW to HIGH
transition of the clock signal and the duration of the R/W
input signal. This is done in order to offer the fastest
possible cycle times and highest data throughput. At 200
MHz,thedevicesupportsacycletimeof5ns,andprovides
a pipelined data output of 3.0 ns from clock edge to data
valid. Four ports operating at 200 MHz, each with a bus
width of 18 bits, results in a data throughput rate of nearly
14 Gbps.
Depth and Width Expansion
Asatruesynchronousdevice,theIDT70V5388/78
providestheflexibilitytoclockeachportindependently:the
portsmayrunatdifferentfrequenciesand/oroutofsynchro-
nization with each other. As a true FourPort device, the
IDT70V5388/78 is capable of performing simultaneous
reads from all ports on the same address location. Care
shouldbetakenwhenattemptingtowriteandreadaddress
locations simultaneously: the timing diagrams depict the
critical parameter tCCS, which determines the amount of
timeneededtoensurethatthewritehassuccessfullybeen
completedandsovaliddataisavailableforoutput.Violation
The IDT70V5388/78 features dual chip enables
(refertoTruthTableI)inordertofacilitaterapidandsimple
depth expansion with no requirements for external logic.
Figure 4 illustrateshowtocontrolthevariouschipenables
in order to expand two devices in depth.
The IDT70V5388/78 can also be used in applica-
tions requiring expanded width, as indicated in Figure 3.
Throughcombiningthecontrolsignals,thedevicescanbe
grouped as necessary to accommodate applications re-
quiring36-bitsorwider.
(1)
A16/A15
IDT70V5388/78
IDT70V5388/78
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V5388/78
IDT70V5388/78
CE1
CE1
UB, LB
R/W,
OE,
CE0
CE0
Control Inputs
Control Inputs
CLK,
CNTLD,
CNTRST,
CNTINC
5649 drw 21
Figure 3. Depth and Width Expansion with IDT70V5388/78
NOTE:
1. A16 is for IDT70V5388, A15 is for IDT70V5378.
21
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
MailboxInterrupts
possible to do so by disabling the byte enables during that
write cycle.
TheIDT70V5388/78supportsmailboxinterrupts,
facilitatingcommunicationamongthedevicesattachedto
each port. If the user chooses the interrupt function, then
each of the upper four address locations in the memory
arrayareassignedasamailboxforoneoftheports:FFFFh
(7FFFh for IDT70V5378) is the mailbox for Port 1, FFFEh
(7FFEh for IDT70V5378) is the mailbox for Port 2, FFFDh
(7FFDh for IDT70V5378) is the mailbox for Port 3, and
FFFCh (7FFCh for IDT70V5378) is the mailbox for Port 4.
TruthTableIIIdetailstheoperationofthemailboxinterrupt
functions.
Once INT has gone LOW for a specific port, that
port can reset the INT by reading its assigned mailbox. In
the case of Port 1, it would clear its INT signal by reading
FFFFh(7FFFhforIDT70V5378).Asstatedpreviously,the
interrupt operation executes based on the state of the
address pins, the chip enables, and the R/W pin: it is
possible to clear the interrupt by asserting a read to the
appropriatelocationwhilekeepingtheoutputenable(OE)or
the byte enables deasserted, and so avoid having to drive
data on the I/O bus. The INT is reset, or goes HIGH again,
in relation to the reading port’s clock signal.
A given port’s interrupt is set (i.e., INT goes LOW)
whenever any other port on the device writes to the given
port’saddress.Forexample,Port1’sINTwillgoLOWifPort
2,Port3,orPort4writetoFFFFh(7FFFhforIDT70V5378).
The INT will go LOW in relation to the clock on the writing
port (see also the Mailbox Interrupt Timing waveform on
page 20). If a port writes to its own mailbox, no interrupt is
generated.
The mailbox location is a valid memory address:
the user can store an 18-bit data word at that location for
retrievalbythetargetport.Intheeventthattwoormoreports
attempt to set an interrupt to the same port at the same
time, theinterruptsignalwillgoLOW, butthedataactually
stored at that location will be indeterminate. The actual
interrupt is generated as a result of evaluating the state of
the address pins, the chip enables, and the R/W pin: if the
user wishes to set an interrupt to a specific port without
changing the data stored in that port’s mailbox, it is
MasterReset
TheIDT70V5388/78isequippedwithanasynchro-
nousMasterResetinput,whichcanbeassertedindepen-
dentlyofallclockinputsandwilltakeeffectpertheMaster
Resettimingwaveformonpage18.TheMasterResetsets
theinternalvalueofalladdresscounterstozero, andsets
the counter mask register on each port to all ones (i.e.,
completelyunmasked).Italsoresetsallmailboxinterrupts
and counter interrupts to HIGH (i.e., non-asserted) and
sets all registered control signals to a deselected state. A
MasterResetoperationmustbeperformedafterpower-up,
inordertoinitializethevariousregistersonthedevicetoa
knownstate.MasterResetwillresetthedevice.ForJTAG
andMBISTresetpleaserefertotheJTAGSectiononpage
25.
Truth Table III—Mailbox Interrupt Flag Operations
(1,2)
(1,2)
(1,2)
(1,2)
Port 1
Port 2
Port 3
Port 4
(4)
(4)
(4)
(4)
CE
X
L
INT
L
CE
L
INT
X
X
L
CE
L
INT
X
X
X
X
L
CE
INT
X
X
X
X
X
X
L
R/W
A
15-
A
0
R/W
L
A
15-
A
0
R/W
L
A
15-
A
0
R/W
L
A
15-
A
0
Function
X
X
FFFF
X
FFFF
X
L
X
L
FFFF
X
Set Port 1 INT Flag(3)
Reset Port 1 INT Flag
Set Port 2 INT Flag(3)
Reset Port 2 INT Flag
Set Port 3 INT Flag(3)
Reset Port 3 INT Flag
Set Port 4 INT Flag(3)
Reset Port 4 INT Flag
H
FFFF
FFFE
X
H
X
X
X
X
X
X
X
X
H
L
X
X
L
X
L
X
L
X
L
L
L
X
FFFE
X
FFFE
X
X
X
L
FFFE
FFFD
X
H
X
X
X
X
X
X
H
L
X
X
L
X
L
X
L
L
FFFD
X
L
X
FFFD
X
X
X
L
X
L
X
L
FFFD
FFFC
X
H
X
X
X
X
H
X
X
L
L
X
FFFC
X
FFFC
X
L
X
X
X
X
X
X
FFFC
H
5649 tbl 14
NOTES:
1. The status of OE is a "Don't Care" for the interrupt logic circuitry. If it is desirable to reset the interrupt flag on a given port while keeping the I/O bus in a tri-state
condition, then this can be accomplished by setting OE = VIH while the read access is asserted to the appropriate address location.
2. The status of the LB and UB controls are "Don't Care" for the interrupt circuitry. If it is desirable to set the interrupt flag to a specific port without overwriting the
data value already stored at the mailbox location, then this can be accomplished by setting LB = UB = VIH during the write access for that specific mailbox.
Similarly, if it desirable to reset the interrupt flag on a given port while keeping the I/O bus in a tri-state condition, then this can be accomplished by setting LB
= UB = VIH while the read access is asserted to the appropriate address location.
3. The interrupt to a specific port can be set by any one of the other three ports. The appropriate control states for the other three ports are depicted above. In the
event that two or more ports attempt to set the same interrupt flag simultaneously via a valid data write, the data stored at the mailbox location will be
indeterminate.
4. A15 is a NC for IDT70V5378, therefore Mailbox Interrupt Addresses are 7FFF, 7FFE, 7FFD and 7FFC. Address comparison will be for A0 - A14.
22
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Address Counter Control Operations
EachportontheIDT70V5388/78isequippedwith
an internal address counter, to ease the process of
burstingdataintooroutofthedevice.TruthTableIIdepicts
the specific operation of the counter functions, to include
theorderofpriorityamongthesignals.Allcountercontrols
areindependentofchipenables.Thedevicesupportsthe
ability to load a new address value on each access, or to
loadanaddressvalueonagivenclockcycleviatheCNTLD
controlandthenallowthecountertoincreasethatvalueby
preset increments on each successive clock via the
CNTINC control (see also the Counter Mask Operations
section that follows). The counter can be suspended on
any clock cycle by disabling the CNTINC, and it can be
reset to zero on any clock cycle by asserting the CNTRST
control.CNTRST onlyaffectstheaddressvaluestoredinthe
counter: it has no effect on the counter mask register.
Whenthecounterreachesthemaximumvaluein
thearray(i.e.,addressFFFFhforIDT70V5388andaddress
7FFFh for IDT70V5378) or it reaches the highest value
permitted by the Counter Mask Register, it then ‘wraps
around’tothebeginningofthearray.WhenAddressMinis
reached via counter increment (i.e., not as a result of an
externaladdressload),thentheCNTINT signalforthatport
isdrivenlowforoneclockcycle,automaticallyresettingon
the next cycle.
When the CNTRD control is asserted, the
IDT70V5388/78willoutputthecurrentaddressstoredinthe
internalcounterforthatportasnotedintheLoadandRead
AddressCountertimingwaveformonpage19.Theaddress
will be output on the address lines. During this output, the
data I/Os will be driven in accordance with the settings of
the chip enables, byte enables, and the output enable on
that port: the device does not automatically tri-state these
pins during the address readback operation.
CNTRD
MKRD
Read Back
Register
Addr.
Read
Back
MKLD
Memory
Array
Mask
Register
Address
(I/O)
Counter/
Address
Register
CNTLD
CNTINC
CNTRST
,
CLK
5649 drw 22
Figure 4. Logic Block Diagram for Read Back Operations
23
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Counter-MaskRegister
CNTINT
Load
Counter-Mask
Register = FF
H
0 0
0's 0 1 1 1 1 1 1 1 1
STEP 1
A
15(2)
A14
A8
A7
A6
A5
A4
A3
A1 A0
A2
Masked Address
Counter Address
Load
Address
Counter = FD
STEP 2
H
H
L
0 0
0's 0 1 1 1 1 1 1 0 1
A
15(2)
A14
A8
A7
A6
A5
A4
A3
A1 A0
A2
Max
Address
Register
STEP 3
STEP 4
,
X X
X's
1 1 1 1 1 1 1
1
X
A
15(2)
A14
A8 A7 A6 A5 A4 A3 A2 A1 A0
Max + 1
Address
Register
X X
X's X 0 0 0 0 0 0 0 0
A
15(2)
A14
A8 A7 A6 A5 A4 A3 A2 A1 A0
5649 drw 23
Figure 5. Programmable Counter-Mask Register Operation(1)
NOTE:
1. The "X's" in this diagram represent the upper bits of the counter.
2. A15 is a NC for IDT70V5378.
The internal address counter on each port has an operation, the CNTINT output for this port is automatically
associatedCounterMaskRegisterthatallowsforconfigu- triggered – it will go low for one clock cycle and then reset.
ration of the internal address counter on that port. Truth
TheexampledepictedinFigure 5isaverysimple
TableIIIgroupstheoperationsoftheaddresscounterwith one: it is also possible to mask non-contiguous bits, such
thoseofthecountermaskregister,toincludeMasterReset asloading5555hinthemaskregister.Asstatedpreviously,
andapplicablereadbackoperations.
theaddresscountersimplyconcatenatesallbitsthathave
Each bit in the mask register controls the corre- not been masked and continues to increment those bits in
spondingbitintheinternaladdresscounter:writinga“1”to accordance with the CNTINC control: in this fashion, if the
a bit in the mask register allows that bit to increment in mask register is set at 5555h and a start address of 0007h
responsetoCNTINC,whilewritinga“0”toabitmasksit(i.e., is asserted via CNTLD, the next value the counter will
locks it at whatever value is loaded via CNTLD). The mask increment to in response to the CNTINC control is 0012h,
register is extremely flexible: every bit can be controlled then 0013h, then 0016h, etc.
independentlyofeveryotherbit.Thecountersimplyconcat-
Besides supporting precise control of which por-
enates those bits that have not been masked, giving the tions of the array are available to a particular port in burst
user great selectivity in determining which portions of the operations, the independent control on the mask register
memory array are available to a particular port for burst bits also provides excellent flexibility in determining the
operations.
value by which the counter will increment. For example,
Figure 5 illustrates the operation of the Counter settingbit0ofthemaskregisterto“0”masksitfromcounter
Mask Register in simply constraining a port to a selected operation, effectively configuring that port to count by
portionofthearray,specificallyaddresses0000hto00FFh. incrementsoftwo.Thiscanbeveryusefulinconfiguringtwo
Instepone,themaskregisterisloadedwith00FFhviaMKLD ports to work in combination, effectively creating a single
(see also the Load and Read Mask Register timing wave- 36-bit port. Thus, Port 1 can be configured to count by two
formonpage19).Insteptwo,astartingaddressof00FDis starting on even addresses (the start point is asserted via
assertedforthestartpointofaburst,andtheCNTINC control CNTLD), and Port 2 can be configured to count by two
is enabled. Step three indicates the address counter startingonoddaddresses(againviaCNTLD).Thetwoports
incrementing to 00FFh. In step four, the internal counter together will operate on 36-bit data words, storing half of
determinesthatalladdressvaluesgreaterthan00FFhhave eachwordinaneven-numberedaddress, theotherhalfin
beenmasked, andsoitincrementspastthis‘max’valueto anodd-numberedaddress.Settingbits1and0ofthemask
0000h. As a result of reaching 0000h via the CNTINC register on a given port to “0” configures that port to count
24
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
in increments of four: masking bits 2, 1, and 0 configures
that port to count in increments of eight, and so on. The
ability to set the increments by which the counters will
advance gives the user the ability to interleave memory
operationsamongtheports, minimizingtheconcernsthat
a given address might be written by more than one port at
any given point in time (an operation that would have
indeterminateresults).
whilea"1"indicatesthatthememoryarraypassed.Therest
of the MRR contains the total number of failed read cycles
in the entire MBIST sequence.
The IDT70V5388/78 MBIST function has been
supplemented with the ability for the user to force a failure
reportfromthedevice. Thisallowstheusertheflexibilityof
validating the MBIST function itself, by verifying that the
deviceisabletoreportfaultsaswellaspassingresults.The
two modes of operation, normal MBIST testing and forced
error reporting, are controlled via the JTAG TAP interface
usingtheinstructionPROGRAM_MBIST_MODE_SELECT.
For further detail, please refer to the System Interface
Parameters table on page 28.
TheMBISTfunctionexecutesoncetheRUNBIST
instructionisinputviatheJTAGinterface.TheentireMBIST
test will be performed with a deterministic number of TCK
cycles depending on the TCK and CLKMBIST frequency.
This can be calculated by using the following formula:
JTAGSupport
The IDT70V5388/78 provides a serial boundary
scan test access port . The JTAG tables starting on page
29providethespecificdetailsfortheJTAGimplementation
on this device.
The IDT70V5388/78 executes a JTAG test logic
resetuponpower-up. Thispower-upresetwillinitializethe
TAP controller and MBIST controller. In most power
environmentsnofurtheractionisrequired. However,ifthe
user has any concern about the system’s voltage states
during power-up, then the user can use the optional TRST
input as part of a board’s power on reset sequence. The
TRST pinalsoprovidesanalternatemeansofresettingthe
JTAG test logic when required, and is available for use by
externalJTAGcontrollersasanasynchronousresetsignal.
IftheuserdoesnotplantorelyontheoptionalTRST pin,but
wantstouseJTAGfunctionality,theTRST pinshouldeither
betiedHIGH(preferredimplementation)orleftfloating.
IfJTAGoperationsarenotdesired,theuserhasa
tCYC[CLKMBIST]
x m + SPC, where:
tCYC =
tCYC[TCK]
tCYC is the total number of TCK cycles required to run
MBIST.
SPC is the synchronization padding cycles (typically 4-6
cycles, to accommodate state machine overhead, turn-
around cycles, etc.)
number of options for disabling the JTAG functions. One
wouldbetosimplytieTCKLOW,leavingallotherJTAGpins
floating (alternatively, TDI and TMS could be tied HIGH).
Since the device executes a JTAG reset upon power-up:
withTCKtiedLOW,nofurtherclockingoftheTAPwilloccur
and no JTAG operations will take place. Alternatively, the
user can opt to tie TRST LOW(eitherinlieuoforinaddition
to tying TCK LOW) and the TAP will be locked in a reset
condition, blocking all JTAG operations.
misaconstantthatrepresentsthenumberofreadandwrite
operations required to run the internal MBIST algorithms
(14,811,136)forbothIDT70V5388andIDT70V5378.
MemoryBuilt-In-TestOperations
Go-NoGo Testing
The IDT70V5388/78 is equipped with a self-test
functionthatcanberunbytheuserastheresultofasingle
instruction, implemented via the JTAG TAP interface. If
multipleFourPortdevicesareusedonthesameboard,all
can execute MBIST simultaneously, facilitating board
checkout.
The MBIST function executes a Go-NoGo test
withinthedevice,whichthencapturespass-failinformation
and failure count in a special register called the MBIST
Result Register (MRR). Upon completion of the test, the
MRRcanbescannedoutviatheJTAGinterface,usingthe
internalscanoperation. BitzerooftheMRR(MRR[0])isa
don'tcare.BitoneoftheMRR(MRR[1])indicatesthepass/
fail status: a "0" indicates some sort of failure was noted,
25
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
JTAG/BIST TAP Controller Block Diagram
0
Bypass Register (BYR)
1
0
MBIST Mode Select Register (MSR)
3
2
1
0
Instruction Register (IR)
25 24
MBIST Result Register (MRR)
31 30 29
Selection
Circuitry
TDI
X
TDO
1
0
(MUX)
,
Identification Register (IDR)
0
391
Boundary Scan Register (BSR)
MBIST
CONTROLLER
TCK
TAP
CONTROLLER
TMS
CLKMBIST
TRST
MEMORY
CELL
5649 drw 25
26
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
tTCYC
tTL
t
TH
TCK
Device Inputs(1)/
TDI/TMS
t
JDC
t
JH
tJS
Device Outputs(2)/
TDO
t
JRSR
t
JCD
TRST
5649 drw 26
,
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
3. To reset the test (JTAG) port without resetting the device, TMS must be held LOW for 5 cycles, or TRST must be held LOW for one cycle.
27
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
(1)
IDT Device ID (27:12)
Defines IDT part number
0x31D
0x33
1
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5649 tbl 15
NOTE:
1. Device ID for IDT70V5378 is 0x31E.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
MBIST Mode Select Register (MSR)
Bypass (BYR)
2
1
Identification (IDR)
32
392 Note (3)
26
Boundary Scan (BSR)
MBIST Result (MRR)
5649 tbl 16
SystemInterfaceParameters
Instruction
Code
0000
Description
EXTEST
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
0111
Places the bypass register (BYR) between TDI and TDO.
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0110
0001
Places the bypass register (BYR) between TDI and TDO. Forces all
device outputdrivers to a High-Z state.
HIGHZ
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
Places the MBIST Mode Register between TDI and TDO. A value of '00'
written into this register will allow MBIST to run in standard memory test
mode, outputting valid results as appropriate via the MBIST Result
Register. A value of '11' written into the MBIST Mode Register will force
the MBIST Result Register (MRR) to report a result of 'FAIL'., with 8E0000
failed read cycles noted (i.e., the MRR content = (8E0000h, 0, x). The
value of the MBIST Mode Register is not guaranteed at power-up and is
not affected by Master reset and JTAG reset.
MBIST_MODE_SELECT
1010
1000
Invokes MBIST. Internally updates MBIST result register with Go-NoGo
information and number of issues. PROGRAM_MBIST_MODE_REGISTER
must be run prior to executing RUNBIST in order to ensure valid results.
There is no need to repeat this instruction unless the mode of operation
is changed: the MMR will retain its programmed value until overwritten or
the device is powered down.
RUNBIST
Scans out partial information. Places MBIST result register (MRR)
between TDI & TDO.
INT_SCAN
CLAMP
0100
0101
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the Bypass register (BYR) between TDI & TDO.
Several combinations are reserved. Do notuse codes other than those
identified above.
RESERVED
PRIVATE
0010, 0011
Several combinations arePRIVATE (for IDT internal use). Do not use
codes other than those identified above.
1001, 1011, 1100, 1101, 1110
5649 tbl 17
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
28
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
272-ball BGA (BG272-1)
256-ball BGA (BC256-1)
BG
BC
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
200
166
133
100
Speed in MH
Z
S
Standard Power
1152K (64K x 18) 3.3V FourPort™ RAM
576K (32K x 18) 3.3V FourPort™ RAM
70V5388
70V5378
5649 drw 27
NOTES:
1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
08/20/02:
09/25/02:
08/20/03:
InitialPublicDatasheet
Added0.5MDensitytoDatasheet
ChangedpowernumbersinDCElectricalCharacteristicstable
RemovedPreliminarystatus
Page 10
01/31/06:
10/23/08:
Page 1
Page 29
Page 29
Addedgreenavailabilitytofeatures
Addedgreenindicatortoorderinginformation
Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
29
6.42
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