70V9199L7PF中文资料_数据手册_规格书

HIGH-SPEED 3.3V

128K x9/x8

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

IDT70V9199/099L

Features:

◆

Counter enable and reset features

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:6/7.5/9/12ns(max.)

– Industrial:9ns (max.)

◆

Full synchronous operation on both ports

– 3.5ns setup to clock and 0ns hold on all control, data, and

addressinputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

◆

Low-power operation

– IDT70V9199/099L

– 10ns cycle time, 100MHz operation in Pipelined output mode

LVTTL- compatible, single 3.3V (±0.3V) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP)

Green parts available, see ordering information

Active:500mW(typ.)

Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

Dual chip enables allow for depth expansion without

additional logic

◆

FunctionalBlockDiagram

R/W

R

R/W

L

OE

OER

CE0R

CE1R

CE

CE1⁰L^L

1

0

0/1

1

0

0/1

0

1

0

0/1

FT/PIPE

R

FT/PIPE

L

.

(1)

I/O0R - I/O8R

I/O0L - I/O8L

I/O

Control

I/O

Control

A16L

A16R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

A

0L

A

C⁰L^RK

R

CLK

L

ADS

CNTEN

ADS

CNTEN

CNTRST

R

L

R

CNTRST

L

4859 drw 01

NOTE:

1. I/O^0X- I/O7X for IDT70V9099.

JANUARY 2006

1

DSC-4859/4

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Description:

Withaninputdataregister,theIDT70V9199/099hasbeenoptimized

forapplicationshavingunidirectionalorbidirectionaldataflowinbursts.An

automaticpowerdownfeature,controlledbyCE⁰andCE1, permitsthe

on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typicallyoperate ononly500mWofpower.

The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to

allowsimultaneousaccessofanyaddressfrombothports.Registerson

control,data,andaddressinputsprovideminimalsetupandholdtimes.

The timing latitude provided by this approach allows systems to be

designedwithveryshortcycletimes.

PinConfiguration^(1,2,3)

04/02/03

Index

96 95 94

100 99 98 97

93 92 91 90

84 83 82 81 80 79 78 77 76

89 88 87 86 85

1

2

3

NC

75

74

73

72

71

A

7R

A

7L

8L

9L

10L

11L

8R

A

4

5

6

7

8

9

9R

10R

11R

12R

13R

14R

70

69

68

A12L

A13L

A14L

67

66

10

11

12

13

A

15R

65

64

63

62

61

60

59

58

57

56

55

54

A

15L

16L

70V9199PF

PN100-1

A

V

16R

SS

(4)

VDD

NC

CE0R

CE1R

CNTRST

14

NC

CE0L

CE1L

15

16

17

18

19

20

21

100-Pin TQFP

Top View

(5)

.

R

CNTRST

L

R/W

OE

R

R/W

OE

R

22

23

24

25

53

52

51

FT/PIPE

GND

NC

R

FT/PIPE

L

NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

4859 drw 02

NOTES:

1. All V^DDpins must be connected to power supply.

2. All V^SSpins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

2

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

PinConfiguration^(1,2,3)(con't.)

04/04/03

Index

91

89

83 82 81 80 79 78

88 87 86 85 84

100 99 98 97 96 95 94 93 92

90

77 76

75

1

2

3

4

5

6

7

8

9

NC

A7L

A8L

A9L

A10L

A11L

A12L

NC

A7R

A8R

74

73

72

71

70

69

68

67

A9R

A10R

A11R

A12R

A13R

A14R

A15R

A16R

V^SS

NC

CE0R

CE1R

CNTRSTR

R/WR

OER

FT/PIPER

V^SS

NC

A13L

A14L

A15L

A16L

V^DD

10

11

66

65

70V9099PF

PN100-1⁽⁴⁾

64

63

62

61

60

59

58

57

56

55

54

53

52

51

12

13

14

15

16

17

18

19

NC

100-Pin TQFP

Top View⁽⁵⁾

NC

CE0L

CE1L

CNTRSTL

R/WL

OEL

20

21

22

23

24

25

FT/PIPEL

NC

40 41

26 27 28 29 30 31 32 33 34 35 36 37 38 39

42 43 44 45 46 47 48 49 50

4859 drw 02a

NOTES:

1. All V^DDpins must be connected to power supply.

2. All V^SSpins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

3

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

Chip Enables

CE^0L,CE1L

R/W

OE

CE0R, CE1R

R/W

OE

L

R

Read/Write Enable

Output Enable

Address

L

R

A0L - A16L

A0R - A16R

(1)

I/O0L - I/O8L

I/O0R - I/O8R

Data Input/Output

Clock

CLKL

CLKR

Address Strobe Enable

Counter Enable

Counter Reset

Flow-Through / Pipeline

Power (3.3V)

ADS

CNTEN

CNTRST

FT/PIPE

L

ADS

CNTEN

CNTRST

FT/PIPE

R

L

R

L

R

NOTE:

1. I/O^0X- I/O7X for IDT70V9099.

L

R

V

DD

VSS

Ground (0V)

4859 tbl 01

Truth Table I—Read/Write and Enable Control^(1,2,3)

(4)

CLK

CE1

R/W

I/O0-8

MODE

OE

X

L

CE0

↑

H

X

L

X

L

X

High-Z

DATA^IN

DATA^OUT

High-Z

Deselected–Power Down

Write

↑

X

↑

H

L

↑

H

Read

H

X

Outputs Disabled

4859 tbl 02

NOTES:

1. "H" = V^IH,"L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

4. I/O⁰- I/O7 for IDT70V9099.

Truth Table II—Address Counter Control^(1,2)

Address

Internal

Address

Used

MODE

External

Address

(3)

CLK

↑

I/O

ADS

CNTEN CNTRST

(4)

X

An

X

0

An

X

H

L

D

I/O(0)

I/O(n)

I/O(p)

DI/O(p+1) Counter Enabled—Internal Address generation

Counter Reset to Address 0

(4)

↑

L

H

D

External Address Loaded into Counter

↑

Ap

H

D

External Address Blocked—Counter disabled (Ap reused)

(5)

↑

Ap + 1

L

4859 tbl 03

NOTES:

1. "H" = V^IH,"L" = VIL, "X" = Don't Care.

2. CE⁰and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other signals including CE⁰and CE1.

5. The address counter advances if CNTEN = V^ILon the rising edge of CLK, regardless of all other signals including CE0 and CE1.

6.42

4

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

RecommendedDCOperating

Conditions

RecommendedOperating

TemperatureandSupplyVoltage⁽¹⁾

Symbol

Parameter

Supply Voltage

Ground

Min.

Typ.

Max.

3.6

0

Unit

V

Ambient

Grade

Commercial

Temperature⁽²⁾

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

VDD

V

DD

SS

IH

IL

3.0

3.3

3.3V

+

0.3V

V

0

V

Industrial

0V

0.3V

(2)

____

V

Input High Voltage

Input Low Voltage

2.0

VDD+0.3V

V

4859 tbl 04

____

V

-0.3⁽¹⁾

0.8

V

NOTES:

1. This is the parameter T^A. This is the "instant on" case temperature.

4859 tbl 05

NOTES:

1. V^IL> -1.5V for pulse width less than 10 ns.

2. V^TERMmust not exceed VDD +0.3V.

AbsoluteMaximumRatings⁽¹⁾

Capacitance⁽¹⁾

(TA = +25°C, f = 1.0MHZ)

Symbol

Rating

Commercial

& Industrial

Unit

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions⁽²⁾

IN = 3dV

Max. Unit

(2)

V

TERM

Terminal Voltage

with Respect to

GND

-0.5 to +4.6

V

CIN

V

9

pF

(3)

OUT

(3)

TBIAS

Te mp e rature

Under Bias

-55 to +125

-65 to +150

^oC

C

VOUT = 3dV

10

pF

4859 tbl 07

NOTES:

Storage

Te mp e rature

TSTG

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

TJN

Junction Temperature

DC Output Current

+150

50

IOUT

mA

3. C^OUTalso references CI/O.

4859 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V^TERMmust not exceed VDD +0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.

3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)

70V9199/099L

Symbol

|I^LI

|I^LO

Parameter

Test Conditions

Min.

Max.

5

Unit

µA

V

(1)

___

|

Input Leakage Current

Output Leakage Current

Output Low Voltage

VDD = 3.6V, VIN = 0V to VDD

|

5

CE = V^IHor CE

OL = +4mA

OH = -4mA

1 = VIL, VOUT = 0V to VDD

VOL

I

0.4

___

VOH

Output High Voltage

I

2.4

V

4859 tbl 08

NOTE:

1. At V^DD< 2.0V input leakages are undefined.

6.42

5

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range⁽³⁾(VDD = 3.3V ± 0.3V)

70V9199/099L6

Com'l Only

70V9199/099L7

Com'l Only

70V9199/099L9

Com'l & Ind

70V9199/099L12

Com'l Only

Symbol

Parameter

Test Condition

= VIL

Version

COM'L

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

Max.

230

240

65

Typ.⁽⁴⁾

Max.

Unit

IDD

Dynamic Operating

Current (Both

Ports Active)

mA

L

220

280

200

250

175

180

40

150

200

CE

L

and CE

R

,

Outputs Disabled,

____

(1)

____

IND

f = fMAX

ISB1

Standby Current

(Both Ports - TTL

Level Inputs)

mA

COM'L

IND

60

85

50

75

30

50

CEL

= CE

R

= VIH

(1)

f = fMAX

____

50

70

ISB2

Standby

COM'L

IND

145

185

130

165

110

145

95

130

CE^"A"= VIL and

(5)

Current (One

Port - TTL

Level Inputs)

CE^"B"= VIH

Active Port Outputs Disabled,

____

110

0.4

100

155

2

(1)

f=fMAX

ISB3

Full Standby

Current (Both

Ports - CMOS

Level Inputs)

Both Ports CE

CE > VDD - 0.2V,

IN > VDD - 0.2V or

IN < 0.2V, f = 0⁽²⁾

L

and

mA

COM'L

IND

L

0.4

2

0.4

2

0.4

2

R

V

____

2

ISB4

Full Standby

Current (One

Port - CMOS

Level Inputs)

COM'L

IND

L

145

180

130

160

140

90

125

CE^"A"< 0.2V and

(5)

CE^"B"> VDD - 0.2V

IN > VDD - 0.2V or

IN < 0.2V, Active Port,

Outputs Disabled, f = fMAX

V

____

100

155

(1)

4859 tbl 09

NOTES:

1. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. V^DD= 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).

5. CE^X= VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V

CE^X> VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

6.42

6

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

Figures 1, 2, and 3

4859 tbl 10

3.3V

590Ω

DATAOUT

30pF

435Ω

5pF*

435Ω

4859 drw 03

4859 drw 04

Figure 2. Output Test Load

(For t^CKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

Figure 1. AC Output Test load.

8

7

6

5

- 10pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

tCD

(Typical, ns)

1

,

4

3

2

1

2

0

20 40 60 80 100 120 140 160 180 200

Capacitance (pF)

-1

.

4859 drw 05

Figure 3. Typical Output Derating (Lumped Capacitive Load).

6.42

7

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)⁽³⁾(VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)

70V9199/099L6

Com'l Only

70V9199/099L7

Com'l Only

70V9199/099L9

Com'l & Ind

70V9199/099L12

Com'l Only

Symbol

Parameter

Clock Cycle Time (Flow-Through)⁽²⁾

Min.

19

Max.

Min.

22

Max.

Min.

25

15

12

6

Max.

Min.

30

20

12

8

Max.

Unit

ns

____

t

CYC1

CYC2

CH1

CL1

CH2

CL2

____

t

Clock Cycle Time (Pipelined)⁽²⁾

Clock High Time (Flow-Through)⁽²⁾

Clock Low Time (Flow-Through)⁽²⁾

10

12

t

6.5

4

7.5

5

t

(2)

t

Clock High Time (Pipelined)

t

Clock Low Time (Pipelined)⁽²⁾

Clock Rise Time

4

5

6

8

____

tR

3

____

tF

Clock Fall Time

3

____

t

SA

HA

SC

HC

SW

HW

SD

HD

SAD

HAD

SCN

HCN

SRST

HRST

OE

OLZ

OHZ

CD1

CD2

DC

CKHZ

CKLZ

Address Setup Time

Address Hold Time

Chip Enable Setup Time

Chip Enable Hold Time

R/W Setup Time

3.5

0

4

0

4

0

4

0

4

0

4

0

4

0

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

____

t

3.5

0

t

3.5

0

t

R/W Hold Time

t

Input Data Setup Time

Input Data Hold Time

ADS Setup Time

3.5

0

t

3.5

0

t

ADS Hold Time

t

3.5

0

CNTEN Setup Time

CNTEN Hold Time

CNTRST Setup Time

CNTRST Hold Time

Output Enable to Data Valid

t

3.5

t

0

1

____

t

6.5

7.5

9

12

(1)

____

t

Output Enable to Output Low-Z

2

(1)

t

Output Enable to Output High-Z

1

7

1

7

1

7

1

7

____

t

Clock to Data Valid (Flow-Through)⁽²⁾

15

18

20

25

(2)

____

t

Clock to Data Valid (Pipelined)

6.5

7.5

9

12

____

t

Data Output Hold After Clock High

2

(1)

t

Clock High to Output High-Z

9

(1)

____

t

Clock High to Output Low-Z

Port-to-Port Delay

____

t

CWDD

Write Port Clock High to Read Data Delay

Clock-to-Clock Setup Time

24

8

28

10

35

15

40

15

ns

tCCS

ns

4859 tbl 11

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed

characterization, but is not production tested.

by device

2. The Pipelined output parameters (t^CYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply

when FT/PIPE = V^ILfor that port.

3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE^R, and FT/PIPEL.

6.42

8

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for

Flow-Through Output (FT/PIPE"X" = VIL)^(3,6)

t

CYC1

tCH1

tCL1

CLK

CE0

t

SC

tHC

t

SC

tHC

CE1

R/

W

t

SW

SA

t

HW

HA

t

ADDRESS⁽⁵⁾

DATAOUT

An

An + 1

An + 2

An + 3

t

DC

(1)

tCD1

tCKHZ

Qn

Qn + 1

Qn + 2

(1)

OHZ

(1)

tDC

t

CKLZ

t

(1)

tOLZ

OE⁽²⁾

..

tOE

4859 drw 06

Timing Waveform of Read Cycle for Pipelined Operation

(FT/PIPE"X" = VIH)^(3,6)

t

CYC2

tCH2

t

CL2

CLK

CE

0

tSC

tHC

tSC

tHC

(4)

CE1

R/

W

tHW

tSW

tHA

tSA

ADDRESS⁽⁵⁾

DATAOUT

An

An + 1

An + 2

Qn

An + 3

(1 Latency)

tDC

tCD2

(6)

Qn + 1

Qn + 2

(1)

tCKLZ

(1)

t

OHZ

(1)

t

OLZ

OE ⁽²⁾

t

OE

4859 drw 07

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

3. ADS = V^IL, CNTEN and CNTRST = VIH.

4. The output is disabled (High-Impedance state) by CE⁰= VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.

5. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

6. 'X' here denotes Left or Right port. The diagram is with respect to that port.

6.42

9

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of a Bank Select Pipelined Read^(1,2)

t

CYC2

tCH2

tCL2

CLK

ADDRESS(B1)

CE0(B1)

t

SA

tHA

A6

A5

A4

A3

A

2

A

0

A1

tSC

tHC

t

SC

tHC

(3)

tCD2

tCKHZ

tCD2

Q

0

Q3

Q

1

DATAOUT(B1)

ADDRESS(B2)

(3)

tDC

tCKLZ

tCKHZ

t

DC

tSA

tHA

A6

A5

A4

A3

A2

A

0

A1

tSC

tHC

CE0(B2)

tSC

tHC

(3)

tCD2

tCKHZ

tCD2

DATAOUT(B2)

Q4

Q2

(3)

tCKLZ

4859 drw 08

Timing Waveform with Port-to-Port Flow-Through Read^(4,5,7)

CLK "A"

tSW

tHW

R/W "A"

ADDRESS "A"

DATAIN "A"

CLK "B"

t

SA

MATCH

SD HD

VALID

tHA

NO

MATCH

t

(6)

tCCS

tCD1

R/W "B"

tHW

tSW

t

HA

tSA

NO

MATCH

ADDRESS "B"

DATAOUT "B"

MATCH

(6)

t

CD1

tCWDD

VALID

tDC

t

DC

4859 drw 09

NOTES:

1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9199/099 for this waveform, and are setup for depth expansion in this

example. ADDRESS^(B1)= ADDRESS(B2) in this situation.

2. OE and ADS = V^IL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.

3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

4. CE⁰and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

5. OE = V^ILfor the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

6. If t^CCS< maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.

If t^CCS> maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.

7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".

6.42

10

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)⁽³⁾

tCYC2

tCH2

tCL2

CLK

CE

0

1

tSC

tHC

CE

tSW tHW

R/W

tSW tHW

(4)

An + 4

An + 3

An

An +1

An + 2

ADDRESS

tSA

tHA

tSD

tHD

DATAIN

Dn + 2

(1)

tCD2

(2)

tCKLZ

tCKHZ

Qn + 3

Qn

DATAOUT

READ

NOP⁽⁵⁾

WRITE

READ

4859 drw 10

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)⁽³⁾

t

CYC2

tCH2

tCL2

CLK

CE0

tSC

tHC

CE1

tSW tHW

R/W

tSW tHW

ADDRESS⁽⁴⁾

An + 4

An

An +1

An + 2

An + 3

Dn + 3

An + 5

t

SA

tHA

t

SD

tHD

DATAIN

Dn + 2

(1)

tCKLZ

tCD2

(2)

Qn

Qn + 4

DATAOUT

(1)

OHZ

t

OE

READ

WRITE

READ

4859 drw 11

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

3. CE⁰and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

11

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)⁽³⁾

t

CYC1

tCH1

tCL1

CLK

CE0

tSC

tHC

CE1

t

SW tHW

R/W

tSW tHW

(4)

An + 4

An

An + 3

An +1

An + 2

ADDRESS

tSA

tHA

t

SD

tHD

DATAIN

Dn + 2

tCD1

(2)

Qn + 3

Qn

READ

Qn + 1

DATAOUT

(1)

tDC

tCKLZ

tDC

t

CKHZ

NOP⁽⁵⁾

READ

WRITE

4859 drw 12

TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)⁽³⁾

tCYC1

tCH1

tCL1

CLK

CE0

tSC

tHC

CE1

tSW tHW

R/W

(4)

An + 5

An

An + 4

An +1

An + 2

An + 3

Dn + 3

ADDRESS

DATAIN

t

SA

tHA

t

SD tHD

Dn + 2

t

OE

tDC

tCD1

t

CD1

(2)

Qn + 4

Qn

DATAOUT

(1)

CKLZ

(1)

t

tDC

tOHZ

OE

READ

WRITE

READ

4859 drw 13

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

3. CE⁰and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

12

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read with Address Counter Advance⁽¹⁾

t

CYC2

t

CH2

tCL2

CLK

t

SA

tHA

An

ADDRESS

tSAD tHAD

ADS

t

SAD tHAD

CNTEN

tSCN tHCN

t

CD2

Qn + 2⁽²⁾

Qn + 3

Qx - 1⁽²⁾

Qn + 1

Qn

Qx

DATAOUT

tDC

READ

EXTERNAL

ADDRESS

READ

WITH

COUNTER

HOLD

READ WITH COUNTER

4859 drw 14

TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance⁽¹⁾

t

CYC1

tCH1

tCL1

CLK

tSA

tHA

An

ADDRESS

t

SAD tHAD

t

SAD

tHAD

ADS

tSCN

tHCN

CNTEN

tCD1

Qn + 3⁽²⁾

Qx⁽²⁾

Qn + 4

Qn + 1

Qn + 2

Qn

DATAOUT

t

DC

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

WITH

COUNTER

4859 drw 15

NOTES:

1. CE⁰and OE = VIL; CE1, R/W, and CNTRST = VIH.

2. If there is no address change via ADS = V^IL(loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data

output remains constant for subsequent clocks.

6.42

13

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-Through or Pipelined Outputs)⁽¹⁾

t

CYC2

tCH2

tCL2

CLK

tSA

tHA

An

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An⁽⁷⁾

An + 4

An + 2

An + 1

An + 3

tSAD tHAD

ADS

CNTEN⁽⁷⁾

tSD tHD

Dn + 4

Dn + 1

Dn + 3

Dn

Dn + 1

Dn + 2

DATAIN

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

WRITE

COUNTER HOLD

WRITE WITH COUNTER

4856 drw 16

Timing Waveform of Counter Reset (Pipelined Outputs)⁽²⁾

t

CYC2

tCH2

tCL2

CLK

tSA tHA

ADDRESS⁽⁴⁾

An + 2

An

An + 1

INTERNAL⁽³⁾

ADDRESS

Ax⁽⁶⁾

0

1

An

An + 1

tSW tHW

R/W

ADS

t

SAD

SCN

tHAD

CNTEN

tHCN

tSRST

tHRST

CNTRST

tSD

tHD

D

0

DATAIN

(5)

Qn

Q1

Q0

DATAOUT

COUNTER⁽⁶⁾

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

ADDRESS n ADDRESS n+1

4856 drw 17

NOTES:

1. CE⁰and R/W = VIL; CE1 and CNTRST = VIH.

CE⁰= VIL; CE1 = VIH.

2.

3. The "Internal Address" is equal to the "External Address" when ADS = V^ILand equals the counter output when ADS = VIH.

4. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR⁰will be accessed. Extra cycles

are shown here simply for clarification.

7. CNTEN = V^ILadvances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.

The ‘An +1’ Address is written to during this cycle.

6.42

14

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

FunctionalDescription

Depth and Width Expansion

TheIDT70V9199/099providesatruesynchronousDual-PortStatic

TheIDT70V9199/099featuresdualchipenables(refertoTruthTable

RAMinterface.Registeredinputsprovideminimalset-upandholdtimes I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-

onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare mentsforexternallogic.Figure4illustrateshowtocontrolthevarioiuschip

clocked on the rising edge of the clock signal, however, the self-timed enables in order to expand two devices in depth.

internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock

signal.

The IDT70V9199/099 can also be used in applications requiring

expandedwidth,asindicatedinFigure4.Sincethebanksareallocated

An asynchronous output enable is provided to ease asynchronous atthediscretionoftheuser,theexternalcontrollercanbesetuptodrive

bus interfacing. Counter enable inputs are also provided to staff the theinputsignalsforthevariousdevicesasrequiredtoallowfor18/16-bit

operationoftheaddresscountersforfastinterleavedmemoryapplications. orwiderapplications.

CE⁰=VILandCE1=VIHforoneclockcyclewillpowerdowntheinternal

circuitrytoreducestaticpowerconsumption.Multiplechipenablesallow

easierbankingofmultipleIDT70V9199/099'sfordepthexpansioncon-

figurations.WhenthePipelinedoutputmodeisenabled,twocyclesare

required with CE0 = VIH or CE1 = VIL to re-activate the outputs.

A17

IDT70V9199/099

Control Inputs

IDT70V9199/099

Control Inputs

CE

0

CE

0

1

CE1

CE

VDD

V

DD

IDT70V9199/099

Control Inputs

IDT70V9199/099

Control Inputs

CE

1

0

CE

1

0

CE

CNTRST

CLK

ADS

CNTEN

R/W

4859 drw 18

Figure 4. Depth and Width Expansion with IDT70V9199/099

OE

6.42

15

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

99

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

I ⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

G⁽²⁾

Green

PF

100-pin TQFP (PN100-1)

Commercial Only

6

7

9

Speed in nanoseconds

Commercial & Industrial

12

Commercial Only

L

Low Power

.

70V9199 1152K (128K x 9-Bit) Synchronous Dual-Port RAM

70V9099 1024K (128K x 8-Bit) Synchronous Dual-Port RAM

4859 drw 19

NOTES:

1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

IDT Clock Solution for IDT70V9199/099 Dual-Port

Dual-Port I/O Specitications

Dual-Port Clock Specifications

IDT

PLL

Clock Devices

IDT

IDT Dual-Port Part

Number

Input Duty

Maximum

Cycle

Non-PLL Clock

Devices

Input

Capacitance

Jitter

Tolerance

Voltage

I/O

Frequency

Requirement

FCT3805

FCT3805D/E

FCT3807

IDT2305

IDT2308

IDT2309

70V9199/099

3.3

LVTTL

9pF

40%

100

150ps

FCT3807D/E

4859 tbl12

6.42

16

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

DatasheetDocumentHistory

09/30/99:

11/12/99:

01/10/01:

InitialPublicRelease

Replaced IDT logo

ChangedinformationinTruthTableII

Increasedstoragetemperatureparameters

ClarifiedTAparameter

Page 3

Page 4

Page 5

DCElectricalparameters–changedwordingfrom"open"to"disabled"

Changed±200mVto0mVinnotes

RemovedPreliminarystatus

04/09/03:

Consolidatemultipledevicesintoonedatasheet

Changednamingconventions fromVCC toVDD andfromGNDtoVSS

Addeddaterevisiontopinconfigurations

AddedjunctiontemperaturetoAbsoluteMaximumRatingsTable

AddedAmbientTemperaturefootnote

Page 2 & 3

Page 5

Page 1, 6 & 16

Page 6

Page 8

Added 6ns speed grade

AddedupdatedDCpowernumberstotheDCElectricalCharacteristicsTable

Added6ns speedACtimingnumbers andchangedt^OEtobe equaltotCD2 intheACElectrical

CharacteristicsTable

Page 16

Page 1

AddedIDTClockSolutionTable

Addedgreenavailabilitytofeatures

01/10/06:

Page 16

Addedgreenindicatortoorderinginformation

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

17

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	针数：	100
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.83
最长访问时间：	18 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	83 MHz	I/O 类型：	COMMON
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e0
长度：	14 mm	内存密度：	1179648 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端口数量：	2	端子数量：	100
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX9
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.002 A
最小待机电流：	3 V	子类别：	SRAMs
最大压摆率：	0.25 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	14 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
70V9199L7PFG8	IDT	TQFP-100, Reel	获取价格
70V9199L9PF	IDT	TQFP-100, Tray	获取价格
70V9199L9PFG	IDT	Dual-Port SRAM, 128KX9, 9ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100	获取价格
70V9199L9PFG8	IDT	Application Specific SRAM, 128KX9, 9ns, CMOS, PQFP100	获取价格
70V9199L9PFGI	IDT	HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM	获取价格
70V9199L9PFI	IDT	TQFP-100, Tray	获取价格
70V9199L9PFI8	IDT	TQFP-100, Reel	获取价格
70V9269	RENESAS	16K x 16 Sync, 3.3V Dual-Port RAM, Pipelined/Flow-Through	获取价格
70V9269L7PRF	IDT	Multi-Port SRAM, 16KX16, 7.5ns, CMOS, PQFP128	获取价格
70V9269L7PRF8	IDT	Multi-Port SRAM, 16KX16, 18ns, CMOS, PQFP128	获取价格

70V9199L7PF

70V9199L7PF 概述

70V9199L7PF 规格参数

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