70V9279S15PRF8 [IDT]
Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128;
| 型号： | 70V9279S15PRF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128 静态存储器 |
| 文件： | 总19页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V9279/69S/L
Features:
◆
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
◆
◆
–
4ns setup to clock and 1ns hold on all control, data,
andaddress inputs
– Commercial:6.5/7.5/9/12/15ns(max.)
– Industrial:7.5ns (max.)
Low-power operation
–
–
Data input, address, and control registers
Fast 6.5ns clock to data out in the Pipelined output mode
◆
– IDT70V9279/69S
Active:429mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V9279/69L
Active:429mW(typ.)
Standby: 1.32mW (typ.)
– Self-timedwriteallowsfastcycletime
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
◆
◆
◆
Flow-through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
◆
Available in a 128-pin Thin Quad Flatpack (TQFP) package
◆
FunctionalBlockDiagram
R/
W
L
L
R/
W
R
R
UB
UB
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LB
OE
L
L
LB
OE
R
R
1a 0a
a
0a 1a
1b 0b
0b 1b
0/1
b
0/1
FT/PIPE
L
a
b
FT/PIPER
,
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
(1)
(1)
A
A
14R
A
14L
Counter/
Address
Reg.
Counter/
Address
Reg.
C0LRK
R
R
A
0L
MEMORY
ARRAY
CLK
L
L
ADS
ADS
CNTEN
R
CNTEN
L
L
CNTRST
CNTRST
R
3743 drw 01
NOTE:
1. A14X is a NC for IDT70V9269.
OCTOBER 2004
1
©2004IntegratedDeviceTechnology,Inc.
DSC 3743/9
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
Withaninputdataregister,theIDT70V9279/69hasbeenoptimizedfor
applicationshavingunidirectionalorbidirectionaldataflowinbursts.An
automaticpowerdownfeature,controlledbyCE0andCE1, permitsthe
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typicallyoperate ononly429mWofpower.
The IDT70V9279/69 is a high-speed 32/16K x 16 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allowsimultaneousaccessofanyaddressfrombothports.Registerson
control,data,andaddressinputsprovideminimalsetupandholdtimes.
The timing latitude provided by this approach allows systems to be
designedwithveryshortcycletimes.
PinConfiguration(2,3,4)
01/15/04
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O10R
I/O9R
N/C
N/C
N/C
V
SS
N/C
I/O8R
N/C
N/C
I/O7R
N/C
A
A
A
A
A
9R
8R
7R
6R
5R
V
DD
9
10
A
4R
I/O6R
I/O5R
I/O4R
A
A
A
A
3R
2R
1R
0R
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
V
SS
I/O3R
V
DD
N/C
CNTEN
CLK
I/O2R
I/O1R
I/O0R
R
R
R
70V9279/69PRF
PK-128(5)
ADS
V
SS
V
SS
VDD
V
DD
I/O0L
I/O1L
ADS
CLK
L
L
128-Pin TQFP
Top View(6)
V
SS
CNTEN
L
I/O2L
I/O3L
N/C
A
A
0L
1L
V
SS
I/O4L
I/O5L
A2L
A3L
A4L
A5L
A6L
A7L
I/O6L
I/O7L
V
DD
N/C
N/C
I/O8L
N/C
A8L
A
9L
N/C
N/C
N/C
N/C
VDD
I/O9L
I/O10L
3743 drw 02
NOTES:
1. A14X is a NC for IDT70V9269.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables(3)
CE0L, CE1L
R/W
OE
0L - A14L
I/O0L - I/O15L
CLK
CE0R, CE1R
R/W
OE
0R - A14R
I/O0R - I/O15R
CLK
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
A
Data Input/Output
Clock
L
R
(2)
Upper Byte Select
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
L
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
R
(2)
Lower Byte Select
Address Strobe Enable
Counter Enable
L
R
NOTES:
L
R
1. Address A14X is a NC for IDT70V9269.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CE0 and CE1 are single buffered when FT/PIPE = VIL,
CE0 and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
L
R
Counter Reset
L
R
Flow-Through / Pipeline
Power (3.3V)
L
R
V
DD
VSS
Ground (0V)
3743 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte
I/O8-15
Lower Byte
I/O0-7
(5)
(5)
(4)
(4)
MODE
CLK
CE1
R/W
X
X
X
L
OE
X
X
X
X
X
X
L
CE0
UB
LB
H
X
L
L
L
L
L
L
L
L
X
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
X
H
L
H
L
L
H
L
L
X
H
H
L
L
H
L
L
L
↑
H
H
H
H
H
H
H
H
↑
DIN
↑
L
High-Z
DATAIN
DATAOUT
High-Z
↑
L
↑
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
↑
L
DATAOUT
High-Z
↑
H
Outputs Disabled
↑
3743 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4
LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.42
3
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2,3)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
(3)
CLK
↑
I/O
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(0) Counter Reset to Address 0
ADS CNTEN CNTRST
(4)
An
X
X
An
An
L
H
H
X
X
H
H
D
(5)
↑
An + 1
An + 1
L
H
X
D
↑
X
An + 1
X
H
D
(4)
↑
X
A0
L
3743 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage(1,2)
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
0
Typ.
Max.
3.6
0
Unit
V
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
V
DD
SS
IH
IL
3.3
3.3V
3.3V
+
0.3V
V
0
V
Industrial
0V
+
0.3V
(2)
____
V
Input High Voltage
Input Low Voltage
2.2
VDD+0.3V
V
3743 tbl 04
NOTES:
(1)
____
V
-0.3
0.8
V
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
3743 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD + 0.3V.
AbsoluteMaximumRatings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
CIN
VIN = 0V
9
pF
(2)
OUT
C
VOUT = 0V
10
pF
(3)
T
BIAS
STG
JN
OUT
Temperature Under Bias
StorageTemperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
oC
3743 tbl 07
NOTES:
T
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
T
I
50
mA
3743 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
6.42
4
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9279/69S
70V9279/69L
Symbol
|ILI
|ILO
Parameter
Test Conditions
DD = 3.6V, VIN = 0V t
CE0 = VIH or CE
OL = +4mA
OH = -4mA
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
___
___
|
Input Leakage Current
Output Leakage Current
Output Low Voltage
V
o VDD
___
___
|
10
5
1
= VIL, VOUT = 0V to VDD
VOL
I
0.4
0.4
___
___
VOH
Output High Voltage
I
2.4
2.4
V
3743 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6) (VDD = 3.3V ± 0.3V)
70V9279/69X6
Com'l Only
70V9279/69X7
Com'l
70V9279/69X9
Com'l Only
& Ind
Symbol
Parameter
Dynamic
Operating
Current (Both
Ports Active)
Test Condition
= VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
180
Max.
Unit
IDD
S
L
220
220
395
350
200
200
335
290
260
225
mA
CEL
and CE
R
,
180
Outputs Disabled,
(1)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
200
200
370
335
I
SB1
Standby
COM'L
IND
S
L
70
70
145
130
60
60
115
100
50
50
75
65
mA
mA
CE
L
= CER = VIH
Current (Both
Ports - TTL
Level Inputs)
(1)
f = fMAX
____
____
____
____
____
____
____
____
S
L
60
60
130
115
ISB2
Standby
COM'L
IND
S
L
150
150
280
250
130
130
240
210
110
110
170
150
CE"A" = VIL and
(5)
Current (One
Port - TTL
Level Inputs)
CE"B" = VIH
Active Port Outputs Disabled,
____
____
____
____
____
____
____
____
(1)
S
L
130
130
265
240
f=fMAX
ISB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
IN < 0.2V, f = 0(2)
L
and
COM'L
IND
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
mA
R
V
V
____
____
____
____
____
____
____
____
S
L
1.0
0.4
20
15
ISB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
mA
COM'L
IND
S
L
140
140
270
240
120
120
230
200
100
100
160
140
CE"A" < 0.2V and
(5)
CE"B" > VDD - 0.2V
IN > VDD - 0.2V or
IN < 0.2V, Active Port,
Outputs Disabled, f = fMAX
V
V
____
____
____
____
____
____
____
____
S
L
120
120
255
230
(1)
3743 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of VSS to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6.42
5
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6) (VDD = 3.3V ± 0.3V)(Cont'd)
70V9279/69X12
Com'l Only
70V9279/69X15
Com'l Only
Symbol
Parameter
Dynamic
Operating
Current (Both
Ports Active)
Test Condition
= VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Unit
IDD
S
L
150
150
240
205
130
130
220
185
mA
CE
L
and CE
R
,
Outputs Disabled,
(1)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
I
SB1
Standby
COM'L
IND
S
L
40
40
65
50
30
30
55
35
mA
mA
CE
L
= CER = VIH
Current (Both
Ports - TTL
Level Inputs)
(1)
f = fMAX
____
____
____
____
____
____
____
____
S
L
ISB2
Standby
COM'L
IND
S
L
100
100
160
140
90
90
150
130
CE"A" = VIL and
(5)
Current (One
Port - TTL
Level Inputs)
CE"B" = VIH
Active Port Outputs Disabled,
____
____
____
____
____
____
____
____
(1)
S
L
f=fMAX
ISB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
IN < 0.2V, f = 0(2)
L
and
COM'L
IND
S
L
1.0
0.4
5
3
1.0
0.4
5
3
mA
R
V
V
____
____
____
____
____
____
____
____
S
L
ISB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
mA
COM'L
S
L
90
90
150
130
80
80
140
120
CE"A" < 0.2V and
(5)
CE"B" > VDD - 0.2V
IN > VDD - 0.2V or
IN < 0.2V, Active Port,
Outputs Disabled, f = fMAX
V
V
____
____
____
____
____
____
____
____
IND
S
L
(1)
3743 tbl 09b
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of VSS to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6.42
6
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
1.5V
Figures 1, 2, and 3
7343 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
3743 drw 03
3743 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
6
5
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD1,
tCD2
4
3
2
1
(Typical, ns)
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
,
3743 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
7
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)
70V9279/69X6
Com'l Only
70V9279/69X7
Com'l
70V9279/69X9
Com'l Only
& Ind
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
19
Max.
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
10
12
t
6.5
6.5
4
7.5
7.5
5
t
t
t
4
5
6
____
____
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
t
SA
HA
SC
HC
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
Address Hold Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
3.5
0
t
t
3.5
0
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
t
t
3.5
0
t
ADS Hold Time
t
3.5
0
CNTEN Setup Time
t
CNTEN Hold Time
t
3.5
CNTRST Setup Time
CNTRST Hold Time
t
0
0
1
____
____
____
t
Output Enable to Data Valid
6.5
7.5
9
(1)
____
____
____
t
Output Enable to Output Low-Z
2
2
2
(1)
t
Output Enable to Output High-Z
1
7
1
7
1
7
____
____
____
t
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
15
18
20
____
____
____
t
6.5
7.5
9
____
____
____
t
2
2
2
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
9
9
(1)
____
____
____
t
Clock High to Output Low-Z
Port-to-Port Delay
____
____
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
24
9
28
10
35
15
ns
tCCS
ns
3743 tbl 11a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)(Cont'd)
70V9279/69X12
Com'l Only
70V9279/69X15
Com'l Only
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
30
20
12
12
8
Max.
Min.
35
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
____
____
____
____
____
____
____
____
____
____
t
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
25
t
12
(2)
t
Clock Low Time (Flow-Through)
12
t
Clock High Time (Pipelined)(2)
10
(2)
t
Clock Low Time (Pipelined)
8
10
____
____
tR
Clock Rise Time
3
3
____
____
tF
Clock Fall Time
3
3
____
____
t
SA
HA
SC
HC
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
t
t
t
ADS Hold Time
t
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
t
t
t
1
1
____
____
t
12
15
(1)
____
____
t
Output Enable to Output Low-Z
2
2
(1)
t
Output Enable to Output High-Z
1
7
1
7
____
____
t
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
25
30
____
____
t
12
15
____
____
t
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
9
(1)
____
____
t
Clock High to Output Low-Z
Port-to-Port Delay
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
40
15
50
20
ns
tCCS
ns
3743 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.42
9
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
CE1
tSB
tHB
tHB
UB, LB
tSB
R/W
tSW
tHW
tSA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
(1)
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
OHZ
(1)
tDC
tCKLZ
t
(1)
tOLZ
OE(2)
tOE
3743 drw 06
Timing Waveform of Read Cycle for Pipelined Output
(FT/PIPE"X" = VIH)(3,7)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
tHC
(4)
CE1
t
SB
tHB
tHB
tSB
(6)
UB, LB
R/W
tHW
tSW
tHA
tSA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
(6)
Qn + 1
Qn + 2
(1)
CKLZ
t
(1)
t
OHZ
(1)
tOLZ
OE(2)
tOE
NOTES:
3743 drw 07
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X" denotes Left or Right port. The diagram is with respect to that port.
6.42
10
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
tCD2
tCKHZ
tCD2
t
CD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
t
DC
HC
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
t
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
3743 drw 08
Timing Waveform of a Bank Select Flow-Through Read(6)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
(1)
t
CD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
t
CKLZ
tCKLZ
tDC
t
CKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
t
HC
(1)
(1)
tCD1
tCKHZ
tCD1
tCKHZ
D4
DATAOUT(B2)
D2
(1)
(1)
t
CKLZ
tCKLZ
3743 drw 08a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9279/69 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.42
11
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(4)
tCCS
tCD1
R/W "B"
tHW
t
SW
t
HA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(4)
tCD1
tCWDD
VALID
VALID
tDC
t
DC
3743 drw 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
R/W"A
"
t
SA
MATCH
SD HD
VALID
t
HA
NO
MATCH
ADDRESS"A"
DATAIN"A"
t
t
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
tSW
tHW
tSA
t
HA
NO
ADDRESS"B"
DATAOUT"B"
MATCH
MATCH
VALID
,
t
DC
3743 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
6.42
12
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
t
CYC2
t
CH2
t
CL2
CLK
CE
0
1
t
SC
tHC
CE
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(4)
An + 4
An + 3
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
tSD
t
HD
DATAIN
Dn + 2
(1)
tCKHZ
(1)
tCKLZ
tCD2
tCD2
(2)
Qn + 3
Qn
DATAOUT
NOP(5)
WRITE
READ
,
READ
3743 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE
0
1
t
SC
tHC
CE
t
SB
t
HB
UB, LB
tSW tHW
R/
W
t
SW
SA
t
HW
(4)
An + 4
An
tHA
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
t
SD
tHD
DATAIN
Dn + 2
(1)
tCKLZ
t
CD2
tCD2
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
,
3743 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
13
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
t
SC
tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
CKHZ
NOP(5)
(1)
CKLZ
tDC
t
t
DC
t
,
READ
WRITE
3743 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(3)
t
CYC1
t
CH1
tCL1
CLK
CE
0
1
tSC
tHC
CE
t
SB
tHB
UB, LB
t
SW tHW
tSW tHW
R/
W
(4)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
t
SA
tHA
t
SD tHD
Dn + 2
t
OE
tDC
tCD1
tCD1
t
CD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
OHZ
t
tDC
t
OE
,
READ
WRITE
READ
3743 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
14
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
t
CL2
CLK
t
SA
tHA
An
ADDRESS
t
SAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
t
CD2
,
Qn + 2(2)
Qn + 3
Qx - 1(2)
Qn + 1
Qn
Qx
DATAOUT
t
DC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3743 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
t
SAD tHAD
t
SAD
t
HAD
ADS
t
SCN
t
HCN
CNTEN
t
CD1
,
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
t
DC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
3743 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
15
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
t
CH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN(7)
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
,
3743 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
t
CH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
1
An
An + 1
t
SW tHW
R/W
ADS
t
SA
D
tHAD
CNTEN
tSCN tHCN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q
1
Q
0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
,
ADDRESS n ADDRESS n+1
3743 drw 18
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’Address is written to during this cycle.
6.42
16
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
The IDT70V9279/69 provides a true synchronous Dual-Port Static
TheIDT70V9279/69featuresdualchipenables(refertoTruthTable
RAMinterface.Registeredinputsprovideminimalset-upandholdtimes I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare mentsforexternallogic.Figure4illustrateshowtocontrolthevarioiuschip
clocked on the rising edge of the clock signal, however, the self-timed enables in order to expand two devices in depth.
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT70V9279/69 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Sincethebanksareallocated
An asynchronous output enable is provided to ease asynchronous atthediscretionoftheuser,theexternalcontrollercanbesetuptodrive
bus interfacing. Counter enable inputs are also provided to staff the theinputsignalsforthevariousdevicesasrequiredtoallowfor32-bitor
operationoftheaddresscountersforfastinterleavedmemoryapplications. widerapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V9279/69's for depth
expansionconfigurations.WhenthePipelinedoutputmodeisenabled,two
cycles are required with CE0 LOW and CE1 HIGH to re-activate the
outputs.
(1)
A15/A14
IDT70V9279/69
Control Inputs
IDT70V9279/69
Control Inputs
CE
0
CE
0
1
VDD
VDD
CE1
CE
IDT70V9279/69
Control Inputs
IDT70V9279/69
Control Inputs
CE
1
CE
1
,
CE0
CE
0
CNTRST
CLK
ADS
CNTEN
R/W
3743 drw 19
Figure 4. Depth and Width Expansion with IDT70V9279/69
LB, UB
OE
NOTE:
1. A15 is for IDT70V9279. A14 is for IDT70V9269.
6.42
17
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PRF
128-pin TQFP (PK128-1)
6
Commercial Only
7
Commercial & Industrial
Speed in nanoseconds
Commercial Only
9
12
15
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
70V9279 512K (32K x 16-Bit) Synchronous Dual-Port RAM
70V9269 256K (16K x 16-Bit) Synchronous Dual-Port RAM
3743 drw 20
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70V927S/L25
70V9279S/L12
70V927S/L30
70V9279S/L15
3743 tbl 12
IDT Clock Solution for IDT70V9279/69 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
Input Duty
IDT
PLL
Clock Device
IDT
IDT Dual-Port
Part Number
Non-PLL Clock
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
I/O
Cycle
Device
Requirement
49FCT3805
49FCT3805D/E
74FCT3807
2305
2308
2309
70V9279/69
3.3
LVTTL
9pF
40%
100
150ps
74FCT3807D/E
3743 tbl 13
6.42
18
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory
1/12/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Page14AddedDepth&WidthExpansionsection
Page 4 Deleted note 6 for Table II
Page 7 Corrected typo in heading
Replaced IDT logo
6/15/99:
9/29/99:
11/10/99:
3/31/00:
CombinedPipelined70V9279/69familyandFlow-through70V927familyofferingsintoonedatasheet
Changed±200mVinwaveformnotesto0mV
Addedcorrespondingpartchartwithorderinginformation
1/17/01:
Page 4 ChangedinformationinTruthTableII
Increasedstoragetemperatureparameters
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
RemovedPreliminarystatus
02/25/04:
Consolidatedmultipledevicesintoonedatasheet
Changednamingconventions fromVCC toVDD andfromGNDtoVss
Page 2 Addeddaterevisionforpinconfiguration
Page 3 Added footnotes forUB,LB, CE0 and CE1 buffer conditions when FT or PIPE
Page 4 AddedjunctiontemperaturetoAbsoluteMaximumRatingsTable
AddedAmbientTemperaturefootnote
Page 5 AddedI-tempnumbersfor9nsspeed toDCElectricalCharacteristicsTable
Added6ns speedDCpowernumbers totheDCElectricalCharacteristics Table
Page 7 AddedI-tempfor9nsspeedtoACElectricalCharacteristicsTable
Added6nsspeedACtimingnumberstotheACElectricalCharacteristicsTable
Page 18 Added6ns speedgrade and9ns I-temptoorderinginformation
AddedIDTClockSolutionTable
Page 1 & 19 Updated IDT logo, replaced IDTTM logo with IDT® logo
Page 1 & 18 Added 7ns speed grade to ordering information
Page 5 Added7ns speedDCpowernumbers totheDCElectricalCharacteristics Table
Page 8 Added7nsspeedACtimingnumberstotheACElectricalCharacteristicsTable
Page 4 UpdatedCapacitancetable
05/04/04:
10/11/04:
Page 5 Added7nsI-tempandremoved9nsI-tempDCpowernumbersfromtheDCElectricalCharacteristicstable
Page 8 Added7nsI-tempandremoved9nsI-tempfromtheACElectricalCharacteristicstable
Page 12 AddedTimingWaveformofLeftPortWritetoPipelinedRightPortRead
Page 18 Added7nsI-tempandremoved9nsI-tempfromorderinginformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
19
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