71342LA25PFGI [IDT]
HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM;
| 型号： | 71342LA25PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM |
| 文件： | 总14页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH SPEED
IDT71342SA/LA
4K X 8 DUAL-PORT
STATIC RAM
WITH SEMAPHORE
Features
◆
◆
High-speed access
Fully asynchronous operation from either port
Full on-chip hardware support of semaphore signalling be-
tween ports
Battery backup operation—2V data retention (LA only)
TTL-compatible; single 5V (±10%) power supply
Available in plastic packages
◆
– Commercial:20/25/35/45/55/70ns(max.)
– Industrial: 25ns (max.)
Low-power operation
◆
◆
◆
◆
◆
– IDT71342SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT71342LA
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Active: 700mW (typ.)
Standby: 1mW (typ.)
FunctionalBlockDiagram
R/WR
R/W
L
CER
CEL
OER
OEL
I/O
CONTROL
I/O
CONTROL
I/O0R - I/O7R
I/O0L- I/O7L
MEMORY
ARRAY
SEMAPHORE
LOGIC
SEMR
SEM
L
ADDRESS
DECODER
ADDRESS
DECODER
A0R- A11R
A0L- A11L
2721 drw 01
SEPTEMBER 2012
1
DSC 2621/14
©2012 IntegratedDeviceTechnology,Inc.
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Description
TheIDT71342isahigh-speed4Kx8Dual-PortStaticRAMwithfull time. An automatic power down feature, controlled by CE and SEM,
on-chip hardware support of semaphore signalling between the two permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower
ports.
The IDT71342 provides two independent ports with separate
mode (both CE and SEM HIGH).
Fabricated using CMOS high-performance technology, this device
control, address, and I/O pins that permit independent, asynchronous typically operates on only 700mW of power. Low-power (LA) versions
access for reads or writes to any location in memory. To assist in offer battery backup data retention capability, with each port typically
arbitrating between ports, a fully independent semaphore logic block consuming200µWfroma2Vbattery.Thedeviceispackagedineithera
is provided. This block contains unassigned flags which can be 64-pin TQFP or a 52-pin PLCC.
accessedbyeitherside;however,onlyonesidecancontroltheflagatany
Pin Configurations(1,2,3)
INDEX
7
6
5
4
3
2
52 51 50 49 48 47
1
46
8
A1L
OER
9
45
44
A
A
2L
3L
A
A
A
A
A
A
A
A
A
A
0R
10
11
12
13
14
15
16
17
18
19
20
1R
2R
3R
4R
5R
6R
7R
8R
9R
43
42
41
40
39
38
37
36
A
4L
5L
A
IDT71342J
J52-1(4)
A6L
A7L
A8L
A9L
52-Pin PLCC
Top View(5)
I/O0L
I/O1L
I/O2L
I/O3L
35
34
N/C
I/O7R
21 22 23 24 25 26 27 28 29 30 31 32 33
2721 drw 02
INDEX
OE
L
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
OER
A0L
A
A
A
A
A
A
A
0R
1R
2R
3R
4R
5R
6R
A1L
A2L
A3L
A4L
A5L
A6L
71342PF
PN64-1(4)
64-Pin TQFP
Top View(5)
N/C
N/C
10
11
12
A
7L
8L
9L
A
A
A
7R
8R
9R
A
A
N/C
I/O0L
I/O1L
I/O2L
13
14
15
36
35
34
33
N/C
N/C
I/O7R
I/O6R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
16
3. J52 package body is approximately .79 in x .79 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2721 drw 03
6.42
2
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum Operating
TemperatureandSupplyVoltage(1,2)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
V
TERM
Te r m i nal Vo l tag e
-0.5 to +7.0
V
with Respect
to GND
Commercial
Industrial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
Temperature
Under Bias
-55 to +125
-65 to +150
1.5
oC
oC
W
-40OC to +85OC
10%
TBIAS
2721 tbl 03
NOTES:
Storage
Temperature
TSTG
1. This is the parameter TA. This is the "instant on" case temperature.
P
T
Power
Dissipation
DC Output
Current
50
mA
IOUT
Recommended DC Operating
Conditions
2721 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Min.
Typ.
Max. Unit
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
V
-0.5(1)
V
2721 tbl 04
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
CIN
V
IN = 3dV
9
pF
COUT
V
OUT = 3dV
10
pF
2721 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage (VCC = 5V ± 10%)
71342SA
71342LA
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
___
___
___
___
___
___
|
V
CC = 5.5V, VIN = 0V to VCC
5
5
|
10
CE = VIH, VOUT = 0V to VCC
OL = 6mA
OL = 8mA
OH = -4mA
I
0.4
0.4
Output Low Voltage
V
OL
I
0.5
0.5
V
___
___
V
OH
Output High Voltage
I
2.4
2.4
V
2721 tbl 05
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
3
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
71342X20
71342X25
Com'l & Ind
71342X35
Com'l Only
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
SA
LA
170
170
280
240
160
160
280
240
150
150
260
200
mA
CE = VIL
,
Outputs Disabled
SEM = Don't Care
____
____
____
____
(3)
IND
SA
LA
160
160
310
260
150
150
300
250
f = fMAX
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
SA
LA
25
25
80
80
25
25
80
50
25
25
75
45
mA
mA
mA
mA
CE
SEM
f = fMAX
L
and CE
R
= VIH
L
= SEMR > VIH
(3)
____
____
____
____
SA
LA
25
25
100
80
25
25
75
55
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
SA
LA
105
105
180
150
95
95
180
150
85
85
170
140
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
SA
LA
95
95
210
170
85
85
200
160
ISB3
Full Standby Current (Both
Ports -
CMOS Level Inputs)
Both Ports CE
CE > VCC - 0.2V,
IN > VCC - 0.2V or VIN < 0.2V
SEM = SEM > VCC - 0.2V
f = 0(3)
L
and
COM'L
IND
SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
R
V
____
____
____
____
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
L
R
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE"A" or
CE"B" > VCC - 0.2V
COM'L
IND
SA
LA
105
105
170
130
95
95
170
120
85
85
150
110
VIN > VCC - 0.2V or VIN < 0.2V
____
____
____
____
SA
LA
95
95
210
190
85
85
190
130
SEM
L
= SEMR > VCC - 0.2V
Active Port Outputs Disabled,
(3)
f = fMAX
2721 tbl 06a
71342X45
Com'l Only
71342X55
Com'l Only
71342X70
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
COM'L
SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
CE = VIL
,
Outputs Disabled
SEM = Don't Care
____
____
____
____
____
____
____
____
(3)
IND
SA
LA
140
140
270
220
f = fMAX
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
mA
mA
mA
mA
CE
SEM
f = fMAX
L
and CE
R
= VIH
L
= SEM
R > VIH
(3)
____
____
____
____
____
____
____
____
SA
LA
25
25
70
50
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
SA
LA
75
75
180
150
ISB3
Full Standby Current (Both
Ports -
CMOS Level Inputs)
Both Ports CE
CE > VCC - 0.2V,
IN > VCC - 0.2V or VIN < 0.2V
SEM = SEM > VCC - 0.2
f = 0(3)
L and
COM'L
IND
SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
R
V
____
____
____
____
____
____
____
____
L
R
V
SA
LA
1.0
2.0
30
10
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE"A" or
CE"B" > VCC - 0.2V
COM'L
IND
SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
VIN > VCC - 0.2V or VIN < 0.2V
____
____
____
____
____
____
____
____
SEM
L
= SEM
R
> VCC - 0.2V
SA
LA
75
75
170
120
Active Port Outputs Disabled,
(3)
f = fMAX
2721 tbl 06b
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
6.42
4
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Data Retention Characteristics
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
CC for Data Retention
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
V
DR
CCDR
(3)
V
2.0
___
I
Data Retention Current
VCC = 2V, CE > VHC
COM'L. & IND.
100
1500
µA
ns
___
___
t
CDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
SEM > VHC
IN > VHC or < VLC
(3)
(2)
___
___
t
R
V
tRC
ns
2721 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Data Rention Waveform
DATA RETENTION MODE
DR > 2V
VCC
4.5V
4.5V
V
t
CDR
tR
VDR
CE
VIH
VIH
2721 drw 04
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1 and 2
2721 tbl 08
+5V
+5V
1250Ω
1250Ω
DATAOUT
775Ω
DATAOUT
775Ω
5pF *
30pF
,
,
2721 drw 05
2721 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
5
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
71342X20
71342X25
Com'l & Ind
71342X35
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
WDD
DDD
SAA
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
20
20
25
25
35
35
Chip Enable Access Time(3)
____
____
____
____
____
____
t
t
Output Enable Access Time
15
15
20
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
0
0
0
____
____
____
t
0
0
0
Output High-Z Time(1,2)
15
15
20
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
SEM Flag Update Pulse (OE or SEM)
Write Pulse to Data Delay(4)
0
0
0
____
____
____
____
____
____
t
50
50
50
____
____
____
t
10
10
15
____
____
____
t
40
50
30
25
60
35
35
Write Data Valid to Read Data Delay(4)
Semaphore Address Access Time
30
____
____
____
____
____
____
t
____
t
ns
2721 tbl 09a
71342X45
Com'l Only
71342X55
Com'l Only
71342X70
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
WDD
DDD
SAA
Read Cycle Time
45
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
45
45
55
55
70
70
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time (1,2)
____
____
____
____
____
____
t
t
25
30
40
____
____
____
t
0
0
0
____
____
____
t
5
5
5
Output High-Z Time(1,2)
20
25
30
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
SEM Flag Update Pulse (OE or SEM)
Write Pulse to Data Delay(4)
Write Data Valid to Read Data Delay(4)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
50
50
50
____
____
____
t
15
20
20
____
____
____
t
70
45
45
80
55
55
90
70
70
____
____
____
____
____
____
t
t
ns
2721 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (SA or LA).
5. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
6.42
6
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
t
AA or tSAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2721 drw 07
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
t
SOP
tACE
CE or SEM (5)
(2)
(4)
AOE
tSOP
t
tHZ
OE
(2)
(1)
tHZ
tLZ
DATAOUT
VALID DATA(4)
(1)
t
LZ
tPU
tPD
I
CC
CURRENT
50%
50%
I
SB
2721 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA
5. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and tSAA is for Semaphore Address Access.
Timing Waveform of Write with Port-to-Port Read(2,3)
tWC
ADDR "A"
MATCH
tWP
(1)
R/W "A"
tDH
tDW
DATAIN "A"
ADDR "B"
VALID
MATCH
tWDD
VALID
DATAOUT "B"
tDDD
2721 drw 09
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. CE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
7
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureSupplyVoltage(5)
71342X20
Com'l Only
71342X25
Com'l & Ind
71342X35
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWR
SPS
Write Cycle Time
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
15
0
20
0
25
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
15
15
20
____
____
____
t
15
15
20
t
Data Hold Time(4)
0
0
3
____
____
____
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
15
20
____
____
____
t
____
____
____
t
3
3
3
____
____
____
____
____
____
t
10
10
10
10
10
10
t
ns
2721 tbl 10a
71342X45
Com'l Only
71342X55
Com'l Only
71342X70
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWR
SPS
Write Cycle Time
45
40
40
0
55
50
50
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
40
0
50
0
60
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
20
25
30
____
____
____
t
20
25
30
t
Data Hold Time(4)
3
3
3
____
____
____
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
20
25
30
____
____
____
t
____
____
____
t
3
3
3
____
____
____
____
____
____
t
10
10
10
10
10
10
t
ns
2721 tbl 10b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
6.42
8
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
OE
(6)
tAS
(3)
tAW
tWR
CE or SEM(9)
(7)
(2)
tHZ
tWP
R/W
(7)
(7)
tWZ
tHZ
t
LZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDH
tDW
2721 drw 10
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
t
WC
ADDRESS
tAW
CE or SEM(9)
(2)
(6)
AS
(3)
t
tEW
t
WR
R/W
t
DW
t
DH
DATAIN
2721 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE =VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
9
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read After Write Timing, Either Side(1)
tSAA
tOH
A0 - A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tDW
tSOP
OUT
VALID
DATA
DATA
0
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
tSOP
2721 drw 12
Test Cycle
(Read Cycle)
Write Cycle
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Condition(1,3,4)
A0"A" - A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B" - A2"B"
MATCH
SIDE(2) "B"
R/W"B"
SEM"B"
2721 drw 13
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from the point where R/W "A" or SEM "A" goes HIGH until R/W "B" or SEM "B" goes HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
10
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
test sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port RAM to claim a privilege over the other processor
forfunctionsdefinedbythesystemdesigner’ssoftware.Asanexample,
the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
TheeightsemaphoreflagsresidewithintheIDT71342inaseparate
memory space from the Dual-Port RAM. This address space is
accessed by placing a LOW input on the SEMpin (which acts as a chip
select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing
a standard Static RAM. Each of the flags has a unique address
which can be accessed by either side through the address pins A0–A2.
When accessing the semaphores, none of the other address pins has
any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other (see Truth Table II). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
fromtheothersideispending)andthencanbewrittentobybothsides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphoreflagsusefulininterprocessorcommunications.(Athorough
discussionontheuseofthisfeaturefollowsshortly.)Azerowritteninto
the same location from the other side will be stored in the semaphore
request latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side’s semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence of WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as a one, a fact which the processor will verify by the
subsequent read (see Truth Table II). As an example, assume a
processorwritesazerointheleftportatafreesemaphorelocation. On
a subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the resource
in question. Meanwhile, if a processor on the right side attempts to
write a zero to the same semaphore flag it will fail, as will be verified
by the fact that a one will be read from that semaphore on the right side
during a subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on
the left port in no way slows the access time of the right port. Both ports
are identical in function to standard CMOS Static RAMs and can be
read from or written to at the same time, with the only possible conflict
arising from the simultaneous writing of, or a simultaneous READ/
WRITE of, a non-semaphore location. Semaphores are protected
against such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion of the
Dual-Port SRAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port SRAM enable, and SEM, the
semaphoreenable. TheCEand SEMpinscontrolon-chippowerdown
circuitry that permits the respective port to go into standby mode when
not selected. This is the condition which is shown in Truth Table I
where CE and SEM are both HIGH.
Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT71342’s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT71342 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
of the Dual-Port RAM. These latches can be used to pass a flag, or
token, from one port to the other to indicate that a shared resource is
inuse.Thesemaphoresprovideahardwareassistforauseassignment
method called “Token Passing Allocation.” In this method, the state of
asemaphorelatchisusedasatokenindicatingthatasharedresource
is in use. If the left processor wants to use this resource, it requests the
token by setting the latch. This processor then verifies its success in
setting the latch by reading it. If it was successful, it proceeds to
assume control over the shared resource. If it was not successful in
setting the latch, it determines that the right side processor had set the
latch first, has the token and is using the shared resource. The left
processor can then either repeatedly request that semaphore’s status
or remove its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the set and
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simplelogicdiagramofthesemaphoreflaginFigure3.Twosemaphore
11
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
request latches feed into a semaphore flag. Whichever latch is first to sidereceivesthetoken.Ifonesideisearlierthantheotherinmakingthe
present a zero to the semaphore flag will force its side of the request, the first side to make the request will receive the token. If both
semaphore flag LOW and the other side HIGH. This condition will requestsarriveatthesametime,theassignmentwillbearbitrarilymade
continue until a one is written to the same semaphore request latch. to one port or the other.
Should the other side’s semaphore request latch have been written to
One caution that should be noted when using semaphores is that
a zero in the meantime, the semaphore flag will now stay LOWuntil its semaphores alone do not guarantee that access to
semaphore request latch is written to a one. From this it is easy to a resource is secure. As with any powerful programming technique, if
understand that, if a semaphore is requested and the processor which semaphores are misused or misinterpreted, a software error can
requesteditnolongerneedstheresource,theentiresystemcanhangup easily happen. Code integrity is of the utmost importance when
untilaoneiswrittenintothatsemaphorerequestlatch.
semaphores are used instead of slower, more restrictive hardware
The critical case of semaphore timing is when both sides request intensive schemes.
a single token by attempting to write a zero into it at the same time. The
Initialization of the semaphores is not automatic and must be
semaphore logic is specially designed to resolve this problem. If handledviatheinitializationprogramatpowerup.Sinceanysemaphore
simultaneous requests are made, the logic guarantees that only one request flag which contains a zero must be reset to a one, all
Truth Table I — Non-Contention Read/Write Control(2)
Left or Right Port(1)
R/W
X
D
0-7
Function
CE
H
H
X
SEM
H
OE
X
Z
Port Disabled and in Power Down Mode
H
L
L
DATAOUT Data in Semaphore Flag Output on Port
X
X
H
X
Z
Output Disabled
Port Data Bit D0 Written Into Semaphore Flag
↑
H
L
L
DATAIN
H
H
L
DATAOUT Data in Memory Output on Port
L
L
H
X
DATAIN
Data on Port Written Into Memory
Not Allowed
____
X
L
L
X
2721 tbl 11
NOTE:
1. AOL - A11L ≠ A0R - A11R.
2. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z" = High-Impedance.
Truth Table II — Example Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D15 Left
D0
- D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTE:
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2721 tbl 12
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
6.42
12
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
semaphores on both sides should have a one written into them at two processors to swap 2K blocks of Dual-Port RAM with each other.
initialization from both sides to assure that they will be free when
needed.
The blocks do not have to by any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-PortRAMorothersharedresourcesintoeightparts.Semaphores
canevenbeassigneddifferentmeaningsondifferentsidesratherthan
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices had determined
which memory area was “off limits” to the CPU, both the CPU and the
I/Odevicescouldaccesstheirassignedportionsofmemorycontinuously
without any wait states.
Using Semaphores–Some
examples
Perhapsthesimplestapplicationofsemaphoresistheirapplication
as resource markers for the IDT71342’s Dual-Port RAM. Say the 4K
x 8 RAM was to be divided into two 2K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of the memory.
To take a resource, in this example the lower 2K of Dual-Port RAM,
the processor on the left port could write and then read a zero into
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 2K. Meanwhile, the right processor would attempt to
perform the same function. Since this processor was attempting to
gain control of the resource after the left processor, it would read back
a one in response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain control of the
second 2K section by writing, then reading a zero into Semaphore 1.
If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Anotherapplicationisintheareaofcomplexdatastructures. Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby
guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D
Q
Q
D
D0
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
2721 drw 14
Figure 3. IDT71342 Semaphore Logic
13
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Ordering Information
A
XXXX
A
999
A
A
A
Device Type Power
Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
G
Green
J
PF
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
Commercial Only
20
25
35
45
55
70
Commercial & Industrial
Commercial Only
Speed in nanoseconds
Commercial Only
Commercial Only
Commercial Only
Standard Power
Low Power
SA
LA
32K (4K x 8-Bit) Dual-Port RAM w/ Semaphore
71342
2721 drw 15
DatasheetDocumentHistory
01/12/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
AddedIndustrialTemperatureRangesandremovedcorrespondingnotes
Replaced IDT Logo
Madecorrectionstodrawing
Increasedstoragetemperatureparameters
ClarifiedTAparameter
06/09/99:
10/01/99:
11/10/99:
12/22/99:
06/26/00:
Page 1
Page 3
Page 4
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±500mVto0mVinnotes
01/12/00:
Pages 1 & 2
Page 1
Moved "Description" to page 2 and adjusted page layouts
Added "(LA only)" to paragraph
Page 2
FixedJ52packagedescriptioninnotes
Page 8
Page 14
Page 1
Replacedbottomtablewithcorrect10btable
Removed "IDT" from orderable part number
Industrial speed access update for 35 & 55
Removed"IDT's"fromdescriptiontext
01/29/09:
09/26/12:
Page 2
Page 3
RemovedfootnotenotationfromPTinAbsoluteMaximumRatingstable01
Page 4, 6 & 8
Replaced"&Ind"withCom'lonlyforspeedgrades35& 55intheDCChars,ACCharsRead&Writetables
06a, 06b, 09a, 09b, 10a & 10b
Page 12
Page 12
Page 14
Added the word "system" to How the Semaphore Flags Work paragraph
Corrected equation for footnote 1 . Changed symbol "=" to - and "1" to not equal (≠)
Added T&R and Green indicators to the ordering information as well as updated the "commercial only"
offering for speed grades 35 & 55
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
14
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