71421LA20TFGI8 [IDT]
HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM;
| 型号： | 71421LA20TFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM |
| 文件： | 总18页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH SPEED
IDT71321SA/LA
IDT71421SA/LA
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
High-speed access
◆
MASTER IDT71321 easily expands data bus width to 16-or-
◆
more-bits using SLAVE IDT71421
◆
◆
◆
◆
◆
◆
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V 10% power supply
Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and
64-Pin STQFP
◆
– IDT71321/IDT71421SA
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71321/421LA
◆
◆
— Active: 325mW (typ.)
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
— Standby: 1mW (typ.)
◆
Two INT flags for port-to-port communications
Green parts available, see ordering information
Functional Block Diagram
OE
R
OE
L
L
CE
CER
R/W
L
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
I/O
Control
Control
BUSY (1,2)
L
(1,2)
R
BUSY
A
10L
A
10R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A0R
11
11
ARBITRATION
and
INTERRUPT
LOGIC
CE
L
L
CE
OE
R/W
R
R
OE
R
R/W
L
(2)
R
(2)
L
INT
INT
2691 drw 01
NOTES:
1. IDT71321(MASTER):BUSYisopendrainoutputandrequirespullupresistorof270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-2691/16
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
The IDT71321/IDT71421 devices are packaged in 52-pin PLCC,
52-pin STQFP, 64-pin TQFP, and 64-pin STQFP.
logic.
Both devices provide two independent ports with separate control,
Pin Configurations(1,2,3)
9 8
19 18 17 16 15 14 13 12 11 10
20
21
I/O4L
I/O5L
I/O6L
I/O7L
NC
7
6
5
4
3
2
A0L
22
23
24
25
26
27
28
29
OE
L
A10L
INTL
BUSYL
L
R/W
GND
0R
CEL
I/O
1
71321/421
J52(4)
52
51
50
49
48
47
CC
V
1R
I/O
2R
I/O
CE
R
I/O3R
I/O4R
I/O5R
I/O6R
30
31
32
33
R/W
R
R
BUSY
INT
R
A10R
46
34 35 36 37 38 39 40 41 42 43 44 45
2691 drw 02
4847464544434241403938 37363534 33
32
49
N/C
N/C
A10R
INTR
I/O5R
I/O4R
N/C
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
N/C
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BUSYR
R/WR
CER
VCC
VCC
CEL
71321/421
PN64 / PP64(4)
R/WL
BUSYL
INTL
NOTES:
A10L
N/C
N/C
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52 packagebodyisapproximately.75inx.75inx.17in.
PN64 packagebodyisapproximately14mmx14mmx1.4mm.
PP64 packagebodyisapproximately10mmx10mmx1.4mm.
4. This package code is used to reference the package diagram.
I/O3L
10 111213141516
1 2 3 4 5 6 7 8 9
2691 drw 03
INDEX
2
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Pin Configurations (continued)(1,2,3)
INDEX
OER
39
A1L
A2L
1
38
37
36
35
34
A0R
A1R
A2R
A3R
A4R
A5R
2
3
4
5
6
A3L
A4L
A5L
A6L
NOTES:
33
32
A7L
A8L
7
8
71321/421
PP52(4)
A6R
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PP52packagebodyisapproximately10mmx10mmx1.4mm.
4. Thispackagecodeisusedtoreferencethepackagediagram.
A7R
A8R
A9L
31
30
9
10
I/O0L
A9R
I/O1L
I/O2L
I/O3L
29
11
N/C
28
27
12
13
I/O7R
,
2691 drw 03a
Capacitance(1)
Recommended Operating
(TA = +25°C, f = 1.0MHz) TQFP Only
Temperature and Supply Voltage(1,2)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
Grade
Ambient
Temperature
GND
Vcc
CIN
V
9
pF
Commercial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
COUT
V
10
pF
Industrial
-40OC to +85OC
10%
2691 tbl 00
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2691 tbl 02
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Min.
Typ.
Max. Unit
(2)
V
TERM
Terminal Voltage
-0.5 to +7.0
V
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
with Respect
to GND
GND
Ground
0
0
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
V
-0.5(1)
V
____
TSTG
Storage
Temperature
2691 tbl 03
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
IOUT
DC Output
Current
mA
2691 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4) (VCC = 5.0V ± 10%)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.
110
Max.
250
Typ.
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
SA
LA
110
110
220
170
mA
CEL and CER = VIL,
Outputs Disabled
f = fMAX
110
200
(2)
____
____
____
____
IND
SA
LA
110
110
270
220
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
SA
LA
30
30
65
45
30
30
65
45
mA
mA
mA
CE
f = fMAX
L and CER = VIH
(2)
____
____
____
____
SA
LA
30
30
75
55
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
SA
LA
65
65
165
125
65
65
150
115
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(2)
f=fMAX
____
____
____
____
SA
LA
65
65
170
140
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
COM'L
IND
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
CE
L
and
> VCC - 0.2V,
CE
V
R
IN > VCC - 0.2V or
____
____
____
____
V
IN < 0.2V, f = 0(3)
SA
LA
1.0
0.2
30
10
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
SA
LA
60
60
155
115
60
60
145
105
mA
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
____
____
____
____
SA
LA
60
60
165
130
(2)
f = fMAX
2691 tbl 04a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.
80
Max.
165
Typ.
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
IND
SA
LA
65
65
155
110
mA
CEL and CER = VIL,
Outputs Disabled
f = fMAX
80
120
(2)
____
____
____
____
SA
LA
65
65
190
140
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
SA
LA
25
25
65
45
20
20
65
35
mA
mA
mA
CE
f = fMAX
L and CER = VIH
(2)
____
____
____
____
SA
LA
20
20
70
50
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
SA
LA
50
50
125
90
40
40
110
75
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(2)
f=fMAX
____
____
____
____
SA
LA
40
40
125
90
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
COM'L
IND
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
CE
L
and
> VCC - 0.2V,
CE
V
R
IN > VCC - 0.2V or
IN < 0.2V, f = 0(3)
____
____
____
____
SA
LA
1.0
0.2
30
10
V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
SA
LA
45
45
110
85
40
40
100
70
mA
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
____
____
____
____
SA
LA
40
40
110
85
(2)
f = fMAX
2691 tbl 04b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
4
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
71321SA
71421SA
71321LA
71421LA
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current(1)
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
___
___
|
V
CC = 5.5V, VIN = 0V to VCC
5
5
___
___
|
CE = VIH, VOUT = 0V to VCC
,
10
µA
V
CC - 5.5V
___
___
___
___
V
V
OL
Output Low Voltage (I/O
0-I/O
7)
I
OL = 4mA
0.4
0.5
0.4
0.5
V
V
Open Drain Output
IOL = 16mA
OL
Low Voltage (BUSY/INT)
___
___
V
OH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2691 tbl 05
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
____
V
DR
V
CC for Data Retention
2.0
0
____
ICCDR
Data Retention Current
µA
µA
V
V
CC = 2.0V, CE > VCC - 0.2V
IN > VCC - 0.2V or VI < 0.2V
COM'L
IND
100
1500
____
N
100
4000
(3)
____
____
t
CDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
RC
____
____
tR
t
ns
2691 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
VDR
2.0V
≥
4.5V
4.5V
tCDR
tR
VDR
CE
VIH
VIH
,
2691 drw 04
5
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.5V
Figures 1,2 and 3
2691 tbl 07
5V
5V
1250Ω
1250Ω
DATA OUT
DATA OUT
775Ω
775Ω
30pF*
5pF*
*100pF for 55ns versions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
5V
270Ω
2691 drw 05
BUSY or INT
30pF*
*100pF for 55ns versions
Figure 3. BUSY and INT
AC Output Test Load
6
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2)
71321X25
71421X25
Com'l
71321X20
71421X20
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
20
25
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
20
20
25
25
____
____
____
____
t
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,3)
t
11
12
____
____
t
3
3
____
____
t
0
0
Output High-Z Time(1,3)
10
10
____
____
t
t
Chip Enable to Power Up Time(3)
Chip Disable to Power Down Time(3)
0
0
____
____
____
____
t
20
25
ns
2691 tbl 08a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
35
35
55
55
____
____
____
____
t
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,3)
t
20
25
____
____
t
3
3
____
____
t
0
5
Output High-Z Time(1,3)
15
25
____
____
t
t
Chip Enable to Power Up Time(3)
Chip Disable to Power Down Time(3)
0
0
____
____
____
____
t
35
50
ns
2691 tbl 08b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
7
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
t
RC
ADDRESS
tOH
tAA
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2691 drw 06
(2,3)
tBDDH
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side (3)
tACE
CE
OE
(4)
(2)
tHZ
tAOE
(2)
(1)
LZ
tHZ
t
DATAOUT
VALID DATA
(1)
(4)
tLZ
tPD
tPU
ICC
CURRENT
50%
50%
I
SS
2691 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
8
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
71321X25
71421X25
Com'l
71321X20
71421X20
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time(2)
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(3)
tWP
tWR
tDW
tHZ
15
0
15
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
10
12
____
____
10
10
____
____
tDH
tWZ
tOW
0
0
(1)
____
____
Write Enable to Output in High-Z
Output Active from End-of-Write(1)
10
10
____
____
0
0
ns
2691 tbl 09a
71321X55
71321X35
71421X35
Com'l Only
71421X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(2)
35
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(3)
t
t
t
25
0
30
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
t
15
20
____
____
t
15
25
____
____
t
0
0
(1)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1)
15
30
____
____
t
0
0
ns
2691 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
9
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
OE
(7)
HZ
t
tAW
CE
(3)
WR
(6)
AS
(2)
WP
(7)
tHZ
t
t
t
R/W
(7)
WZ
t
tOW
(4)
(4)
OUT
DATA
tDW
tDH
IN
DATA
2691 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
CE
tAW
(6)
AS
(2)
tEW
(3)
WR
t
t
R/W
tDW
tDH
IN
DATA
2691 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
10
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER 71321)
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tWH
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
20
20
(5)
____
____
Write Hold After BUSY
12
15
tWDD
tDDD
tAPS
tBDD
Write Pulse to Data Delay(1)
50
50
____
____
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
35
35
____
____
____
____
5
5
____
____
25
35
BUSY INPUT TIMING (For SLAVE 71421)
____
____
____
____
tWB
Write to BUSY Input(4)
0
0
ns
ns
ns
(5)
tWH
Write Hold After BUSY
12
15
____
____
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
40
30
50
35
____
____
ns
2691 tbl 10a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
BUSY TIMING (For MASTER 71321)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
20
20
20
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
t
t
t
20
30
(5)
____
____
t
Write Hold After BUSY
20
20
t
Write Pulse to Data Delay(1)
60
80
____
____
t
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
35
55
____
____
____
____
t
5
5
____
____
t
35
50
BUSY INPUT TIMING (For SLAVE 71421)
Write to BUSY Input(4)
____
____
____
____
t
WB
WH
WDD
DDD
0
0
ns
ns
ns
(5)
t
Write Hold After BUSY
20
20
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
60
35
80
55
____
____
t
____
____
t
ns
2691 tbl 10b
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA)..
11
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
VALID
(1)
APS
t
MATCH
ADDR"B"
BUSY"B"
tBAA
tBDD
tBDA
tWDD
DATAOUT"B"
NOTES:
VALID
tDDD
2691 drw 10
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
,
R/W"B"
(2)
2691 drw 11
NOTES:
1. tWH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version (IDT71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
12
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR "A"
ADDRESSES MATCH
AND "B"
CE"B"
(2)
tAPS
CE"A"
tBAC
tBDC
BUSY"A"
2691 drw 12
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
ADDR"B"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
APS
t
t
BAA
tBDA
BUSY"B"
2691 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. IftAPSisnotsatisfied,theBUSYwillbeassertedononesideortheother,butthereisnoguaranteeonwhichsideBUSYwillbeasserted(IDT71321only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
20
20
25
25
____
____
t
Interrupt Reset Time
ns
2691 tbl 11a
NOTE:
1. 'X' in part numbers indicates power rating (SA or LA).
13
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(1)
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
25
25
45
45
____
____
t
Interrupt Reset Time
ns
2691 tbl 11b
NOTE:
1. 'X' in part numbers indicates power rating (SA or LA).
Timing Waveform of Interrupt Mode(1)
Set INT
tWC
INTERRUPT ADDRESS (2)
ADDR"A"
(4)
(3)
tAS
tWR
R/W"A"
INT"B"
(3)
tINS
2691 drw 14
Clear INT
tRC
(2)
ADDR"B"
INTERRUPT CLEAR ADDRESS
(3)
AS
t
OE"B"
(3)
t
INR
,
INT"B"
2691 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
14
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
X
D
0-7
Function
or ISB
or ISB
CE
H
H
L
OE
X
Z
Port Disabled and in Power-Down Mode, ISB
2
4
X
X
Z
CE
Data on Port Written Into Memory(2)
Data in Memory Output on Por (3)
R
= CE
L
= VIH, Power-Down Mode, ISB
1
3
L
X
DATAIN
DATAOUT
Z
H
L
L
t
H
L
H
High Impedance Outputs
2691 tbl 12
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II. Interrupt Flag(1,4)
Left Port
Right Port
R/W
L
A10L-A0L
R/WR
A10R-A0R
Function
CEL
OEL
INTL
CER
OER
INTR
L
X
X
X
L
X
X
L
X
7FF
X
X
X
X
L
L
X
X
X
L(2)
H(3)
X
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT Flag
R
Flag
X
X
X
L
7FF
7FE
X
R
Flag
X
X
L(3)
H(2)
L
X
L
L
7FE
X
X
X
L
2691 tbl 13
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Truth Table III — Address BUSY Arbitration
Inputs
Outputs
A
0L-A10L
(1)
(1)
A0R-A10R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
2691 tbl 14
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not push-
pull outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
15
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Functional Description
The IDT71321/IDT71421 provides two ports with separate control,
addressandI/Opinsthatpermitindependentaccessforreadsorwrites
to any location in memory. The IDT71321/IDT71421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
whennotselected(CE=VIH).Whenaportisenabled,accesstotheentire
memoryarrayispermitted.
beingexpandedindepth,thentheBUSYindicationfortheresultingarray
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one
masterpartisusedtodecidewhichsideoftheSRAMarraywillreceive
aBUSYindication,andtooutputthatindication.Anynumberofslavesto
beaddressedinthesameaddressrangeasthemaster, usethe BUSY
signalasawriteinhibitsignal.ThusontheIDT71321/IDT71421SRAMs
theBUSYpinisanoutputifthepartisMaster(IDT71321),andtheBUSY
pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), whereawriteisdefinedastheCER =R/WR=VIL,perTruthTable
II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag(INTR)isassertedwhentheleftportwritestomemorylocation7FF
(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe
memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
SLAVE
Dual Port
SRAM
5V
270Ω
MASTER
Dual Port
SRAM
CE
CE
5V
BUSY
L
BUSY
L
BUSY
R
BUSYR
270Ω
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSY
R
BUSY
L
BUSYR
BUSY
L
BUSY
R
BUSY
L
2691 drw 16
Busy Logic
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesabusyindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration, onaMaster, isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
TheuseofBUSYLogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use any BUSYindication as an interrupt source to flag the event of
anillegalorillogicaloperation.InslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT71321 (Master) are open drain type
outputsandrequireopendrainresistorstooperate.IftheseSRAMsare
16
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
A
999
A
A
A
A
Device Type Power Speed
Process/
Temperature
Range
Package
Tube or Tray
Tape and Reel
Blank
8
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
J
52-pin PLCC (J52)
PF
PP
TF
64-pin TQFP (PN64)
52-pin STQFP (PP52)
64-pin STQFP (PP64)
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial Only
Speed in nanoseconds
Commercial & Industrial
Low Power
Standard Power
LA
SA
71321
71421
16K (2K x 8-Bit) MASTER Dual-Port SRAM w/ Interrupt
16K (2K x 8-Bit) SLAVE Dual-Port SRAM w/ Interrupt
2691 drw 17 PP52
NOTES:
1. Contact your sales office for industrial temperature range availability in other speeds, packages and powers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
Datasheet Document History
03/24/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmetictypographicalcorrections
Pages 2 and 3
Page 3
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Replaced IDT logo
Increasedstoragetemperatureparameters
ClarifiedTA parameter
06/07/99:
11/10/99:
08/23/01:
Page 4
Page 16
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Fixed part numbers in "Width Expansion" paragraph
Changed 500mVto0mVinnotes
Page 4
IndustrialtemperaturerangeofferingaddedtoDCElectricalCharacteristicsfor25nsandremovedfor
35ns
Page 7 and 9
Page 17
Page 1
IndustrialtemperaturerangeaddedtoACElectricalCharacteristicsfor25ns
Industrialofferingremovedfor35nsorderinginformation
Addedgreenavailabilitytofeatures
01/17/06:
Page 17
Page 1 & 17
Addedgreenindicatortoorderinginformation
Replaced old IDTTM with new IDTTM logo
17
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Datasheet Document History (continued)
08/25/06:
10/29/08:
09/10/12:
Page 14
Page 17
Page 1& 2
Page 3
Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode
Removed "IDT" from orderable part number
52-pinSTQFPaddedtothefeaturesanddescription
PP52-1pinconfigurationadded
Page 9
Typo corrected
Page 17
Page 2
AddedT&RindicatorandPP52-1packageinformationtotheorderinginformation
Changed diagram for the J52 pin configuration by rotating package pin labels and pin
numbers 90 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1
Removed J52 chamfers and aligned the top and bottom pin labels in the standard direction
Changed diagram for the PN64/PP64 pin configuration by rotating package pin labels and pin
numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1
PP52 pin configuration. Added the IDT logo, changed the text to be in alignment with new diagram
markingspecs
06/10/16:
Page 3
Removedfootnote5anditsreferences
Pages 2 & 17
InpinconfigurationfootnotesandintheOrderingInformation:ThepackagecodesJ52-1,PN64-1,
PP64-1 and PP52-1changed to J52, PN64, PP64 & PP52 respectively to match standard package codes
ProductDiscontinuationNotice-PDN#SP-17-02
02/20/18:
Last time buy expires June 15, 2018
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
18
6.42
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