71P72804S250BQG8 [IDT]
CABGA-165, Reel;
| 型号： | 71P72804S250BQG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-165, Reel |
| 文件： | 总21页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18Mb Pipelined
QDR™II SRAM
Burst of 2
IDT71P72804
IDT71P72604
Features
Description
The IDT QDRIITM Burst of two SRAMs are high-speed synchro-
nous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with two data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) de-
vices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
◆
◆
18Mb Density (1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
Supports concurrent transactions
-
◆
◆
◆
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
DDR (Double Data Rate) MultiplexedAddress Bus
-
One Read and One Write request per clock cycle
◆
DDR (Double Data Rate) Data Buses
-
-
Two word burst data per clock on each port
Four word transfers per clock cycle (2 word bursts
on 2 ports)
◆
◆
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
◆
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
The QDRII has a single DDR address bus with multiplexed read
and write addresses. All read addresses are received on the first half of
the clock cycle and all write addresses are received on the second half
of the clock cycle. The read and write enables are received on the first
half of the clock cycle. The byte and nibble write signals are received on
both halves of the clock cycle simultaneously with the data they are
controlling on the data input bus.
◆
◆
◆
◆
Commercial and IndustrialTemperature Ranges
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Functional Block Diagram
(Note1)
(Note1)
(Note1)
DATA
DATA
REG
D
REG
WRITE DRIVER
(Note2)
(Note3)
ADD
REG
(Note2)
SA
(Note4)
(Note4)
(Note1)
18M
MEMORY
ARRAY
Q
R
W
BWx
CTRL
LOGIC
K
CLK
GEN
CQ
K
CQ
C
SELECT OUTPUT CONTROL
C
6109 drw 16
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 2 signal lines for x18, and 4r signal lines for x36.
4) Represents 36 signal lines for x18, and 72 signal lines for x36.
OCTOBER 2008
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6109/0A
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Echo Clock
The QDRII has echo clocks, which provide the user with a clock that
is precisely timed to the data output, and tuned with matching impedance
and signal quality. The user can use the echo clock for downstream
clocking of the data. Echo clocks eliminate the need for the user to
producealternateclockswithprecisetiming, positioning, andsignalquali-
ties to guarantee data capture. Since the echo clocks are generated by
The echo clocks, CQ andCQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge ofC generates
the rising edge ofCQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
the same source that drives the data output, the relationship to the data is improve the duty cycle of the individual signals.
not significantly affected by voltage, temperature and process, as would
be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the two words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte and nibble write signals can be used to prevent writing any indi-
vidual bytes, or combined to prevent writing one word of the burst.
Read operations are initiated by holding the read port select (R) low,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and designating with the Byte Write inputs (BWx) which bytes are to be
written. The first word of the data must also be present on the data input
bus D[X:0]. Upon the rising edge of K the first word of the burst will be
latched into the input register. After K has risen, and the designated hold
times observed, the second half of the clock cycle is initiated by present-
ing the write address to the address bus SA[X:0], theBWx inputs for the
seconddatawordoftheburst, andtheseconddataitemofthebursttothe
data bus D[X:0]. Upon the rising edge of K, the second word of the burst
will be latched, along with the designated address. Both the first and
second words of the burst will then be written into memory as designated
by the address and byte write enables.
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in two word bursts, with
addressing capability to the burst level.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
The K andKclocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, W and BWx), the read ad-
dress, and the first word of the data burst during a write operation. The
K clock is used to clock in the control signals (BWx), write address and
the second word of the data burst during a write operation. The K and
Kclocks are also used internally by the SRAM. In the event that the user
disables the C andC clocks, the K andK clocks will also be used to clock
the data out of the output register and generate the echo clock. The C
and C clocks may be used to clock the data out of the output register
during read operations and to generate the echo clocks. C and C must
be presented to the SRAM within the timing tolerances. The output data
from the QDRII will be closely aligned to the C andC input, through the
use of an internal DLL. When C is presented to the QDRII SRAM, the
DLL will have already internally clocked the first data word to arrive at
the device output simultaneously with the arrival of the C clock.
The C clock and second data word of the burst will also correspond.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and
C may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and K clocks.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLLby holding Doff low. With the DLLoff, the C andC (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
6.242
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Definitions
Symbol
Pin Function
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
Input
D[X:0]
Synchronous 1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K
clocks during write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data.
BW
BW
0
, BW
1
Input
2, BW
3
Synchronous Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW controls D[8:0] and BW controls D[17:9]
512K x 36 -- BW controls D[8:0], BW controls D[17:9], BW
0
1
0
1
2
controls D[26:18] and BW3 controls D[35:27]
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write
addresses are sampled on the rising edge of K clock during active write operations. These address inputs are
multiplexed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when
the appropriate port is deselected.
Input
Synchronous
SA
Output
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising
Q[X:0]
Synchronous edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the
Read port is deselected, Q[X:0] are automatically three-stated.
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write
operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause
D[X:0] to be ignored.
Input
Synchronous
W
R
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read
operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is
allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock.
Input
Synchronous
Each read access consists of a burst of two sequential transfer.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be
Input Clock used together to deskew the flight times of various devices on the board back to the controller. See application example
for further details.
C
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can
Input Clock
C
be used together to deskew the flight times of various devices on the board back to the controller. See application
example for further details.
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out
data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs
Output Clock and can be used as a data valid indication. These signals are free running and do not stop when the output data is tri-
stated.
CQ, CQ
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance.
ZQ
Input
Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this
pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected
directly to GND or left unconnected.
6109 tbl 02a
6.42
3
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be
different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C
to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
Input
Doff
TDO
TCK
TDI
Output
Input
Input
Input
TDO pin for JTAG
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected.
TMS
NC
No Connect No connects inside the package. Can be tied to any voltage level
Input Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC
V
REF
Reference measurement points.
Power
V
DD
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Supply
VSS
Ground
Ground for the device. Should be connected to ground of the system.
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the
desired output voltage.
VDDQ
6109 tbl 02b
6.442
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Configuration IDT71P72804 (1M x 18)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
W
5
6
K
7
8
R
9
10
11
V
SS/
NC/
SA (1)
VSS/
SA (2)
NC
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
BW
1
SA (3)
Q9
D9
SA
NC
SA
K
SA
NC
Q8
BW
0
NC
D10
VSS
SA
SA
VSS
Q7
D8
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
D7
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
D6
Q6
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
D5
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
ZQ
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
Q4
D4
Q14
VDDQ
VDD
VSS
VDD
VDDQ
D3
Q3
K
L
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
Q2
NC
D16
VSS
VSS
VSS
VSS
VSS
Q1
D2
M
N
P
R
D17
Q16
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
D1
NC
Q17
SA
SA
SA
SA
D0
Q0
TCK
SA
TMS
TDI
C
6109 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.
6.42
5
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Configuration IDT71P72604 (512K x 36)
1
2
3
4
W
5
BW
BW
6
K
7
8
R
9
10
11
V
SS/
NC/
SA (2)
NC/
SA (1)
V
SS/
CQ
A
B
C
D
E
F
CQ
2
3
BW
1
SA (4)
SA (3)
Q27
Q18
D18
SA
K
SA
D17
Q17
Q8
BW
0
D
27
Q
28
D
19
V
SS
SA
SA
SA
V
SS
D
16
Q
7
D8
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
D
30
D
22
Q
22
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
13
D
13
D5
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
Doff
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q
4
D4
Q
32
D
32
Q
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
12
D
3
Q3
K
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D
33
Q
34
D
25
V
SS
V
SS
V
SS
V
SS
V
SS
D
10
Q
1
D2
M
N
P
R
D34
D26
Q25
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
Q10
D9
D1
Q35
D35
Q26
SA
SA
SA
SA
Q
9
D0
Q0
TDO
TCK
SA
SA
TMS
TDI
C
6109 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604)
devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604)
devices.
6.642
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Absolute Maximum Ratings(1) (2)
Capacitance (TA = +25°C, f = 1.0MHz)
(1)
Symbol
Rating
Value
Unit
Symbol
Parameter
Input Capacitance
Conditions
Max.
Unit
pF
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
CIN
5
6
7
VDD = 1.8V
CCLK
Clock Input Capacitance
Output Capacitance
pF
VDDQ = 1.5V
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD +0.3
–0.5 to VDD +0.3
-0.5 to VDDQ +0.3
V
V
V
CO
pF
6109 tbl 06
NOTE:
VTERM
Voltage on Input terminals with
respect to GND.
1. Tested at characterization and retested after any design or process
change that may affect these parameters.
VTERM
Voltage on Output and I/O
terminals with respect to GND.
Recommended DC Operating and
Temperature Conditions
T
BIAS
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
TSTG
Symbol
VDD
Parameter
Power Supply Voltage
I/O Supply Voltage
Ground
Min.
1.7
1.4
0
Typ.
1.8
1.5
0
Max. Unit
IOUT
Continuous Current into Outputs
mA
1.9
VDD
0
V
V
V
V
6109 tbl 05
NOTES:
VDDQ
VSS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGSmaycausepermanentdamagetothedevice. Thisisastress
ratingonlyandfunctionaloperationofthedeviceattheseoranyother
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
VREF
Input Reference Voltage
0.68 VDDQ/2 0.95
0 to +70
o
c
Commercial
Industrial
Ambient
Temperature
TA
(1)
o
c
-40 to +85
2. VDDQ must not exceed VDD during normal operation.
6109 tbl 04
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
Write Descriptions(1,2,3)
Signal
BW
0
BW
1
BW
X
2
BW
X
3
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
L
X
X
L
X
X
X
X
L
X
X
X
X
L
6109 tbl 09
NOTES:
1) All byte write (BWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the
data bus in the designated byte will be latched into the input if
the corresponding BWx is held low. The rising edge of K will
sample the first byte of the two word burst and the rising edge
of K will sample the second byte of the two word burst.
2) The availability of the BWx on designated devices is de
scribed in the pin description table.
3) The QDRII Burst of two SRAM has data forwarding. Aread request
that is initiated on the same cycle as a write request to the same
address will produce the newly written data in response to the read
request.
6.42
7
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Application Example
SRAM #1
SRAM #4
ZQ
Q
ZQ
Q
250
Ω
250
Ω
D
D
V
T
K
K
R
C
K
K
R W BW
0
BW
1
C
C
SA
W BW
0
BW
1
C
SA
R
Data In
Data Out
Address
R
R
R
R
R
R
V
T
W
BW x
V
T
VT
MEMORY
CONTROLLER
R
R
Return CLK
Source CLK
Return CLK
Source CLK
VT = VREF
R = 50Ω
6109 drw 20
6.842
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
µA
Input Leakage Current
Output Leakage Current
I
IL
V
DD = Max VIN = VSS to VDDQ
-2
-2
+2
+2
Output Disabled
µA
IOL
Com'l
Ind
V
I
DD = Max,
OUT = 0mA (outputs open),
Cycle Time > tKHKH Min
200MH
Z
-
-
950
1000
Operating Current
(x36): DDR
I
DD
mA
mA
1
167MH
Z
850
850
750
650
375
335
300
900
-
250MH
200MH
167MH
250MH
200MH
167MH
Z
-
-
-
-
-
-
VDD = Max,
Operating Current
(x18): DDR
IDD
IOUT = 0mA (outputs open),
Z
800
700
-
1,8
Cycle Time > tKHKH Min
Z
Device Deselected (in NOP state),
Iout = 0mA (outputs open),
f=Max,
Z
Standby Current: NOP
ISB1
Z
385
350
mA
2,8
All Inputs <0.2V or > VDD -0.2V
Z
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
RQ = 250Ω, IOH = -15mA
RQ = 250Ω, IOL = 15mA
V
OH1
OL1
OH2
OL2
V
DDQ/2-0.12
DDQ/2-0.12
DDQ-0.2
SS
V
DDQ/2+0.12
DDQ/2+0.12
DDQ
V
V
V
V
3,7
4,7
5
V
V
V
IOH = -0.1mA
V
V
V
IOL = 0.1mA
V
V
0.2
6
6109 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω< RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω< RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
8. Industrial temperature range is not available for the 250MHz speed grade.
6.42
9
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Input Electrical Characteristics Over
the Operating Temperature and
Undershoot Timing
Supply Voltage Range
VIH
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Min
Max
DDQ +0.3
Unit Notes
V
SS
Input High Voltage, DC
Input Low Voltage, DC
Input High Voltage, AC
Input Low Voltage, AC
NOTES:
V
IH (DC
IL (DC)
IH (AC)
IL (AC)
)
V
REF +0.1
V
V
V
V
V
1,2
1,3
4,5
4,5
V
SS-0.25V
V
-0.3
VREF -0.1
V
SS-0.5V
V
V
REF +0.2
-
6109 drw 22
20% tKHKH (MIN)
V
-
VREF -0.2
6109 tbl 10d
Overshoot Timing
1.These are DC test criteria. DC design criteria is VREF +50mV. The
AC VIH/VILlevels are defined separately for measuring timing param
eters.
20% tKHKH (MIN)
V
DD +0.5
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse
width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20%
tKHKH (min))
VDD +0.25
VDD
4. This conditon is forAC function test only, not forAC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the currentAC level through the
target AC level, VIL(AC) or VIH(AC)
VIL
6109 drw 21
b) Reach at least the targetAC level.
c)After theAC target level is reached, continue to maintain at least the
target DC level, VIL(DC) or VIH(DC)
61.402
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
AC Test Conditions(1)
Parameter
Core Power Supply Voltage
I/O Power Supply Voltage
Input High Level
Symbol
Value
Unit
V
V
DD
DDQ
IH
IL
1.7 to 1.9
V
1.4 to VDD
(VDDQ/2)+ 0.5
(VDDQ/2)- 0.5
V
V
V
Input Low Level
V
V
Input Reference Level
Input Rise/Fall Time
VREF
TR/TF
V
DDQ/2
0.3/0.3
DDQ/2
V
ns
Output Timing Reference Level
V
V
6109tbl 11a
NOTE:
1. Parameters are tested with RQ=250Ω
Input Waveform
(VDDQ/2) + 0.5V
Test points
VDDQ/2
V
DDQ/2
(VDDQ/2) - 0.5V
6109 drw 06
Output Waveform
Test points
VDDQ/2
VDDQ/2
6109 drw 06a
AC Test Load
VDDQ
/2
DDQ/2
V
Ω
RL = 50
REF
V
OUTPUT
Ω
=50
Z0
Device
Under
Test
Ω
Q = 250
R
ZQ
6109 drw 04
6.42
11
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
AC Electrical Characteristics
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges) (3,7)
250MHz(10,11)
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Symbol
Parameter
Unit
Notes
Clock Parameters
t
KHKH
KC var
KHKL
KLKH
KHKH
KHKH
KHCH
KC lock
Clock Cycle Time (K,K,C,C)
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K,C→C)
Clock to clock (K→K,C→C)
4.00
-
6.30
5.00
-
7.88
6.00
-
8.40
ns
ns
t
0.20
0.20
0.20
1,5
8
t
1.60
1.60
1.80
1.80
0.00
1024
30
-
2.00
2.00
2.20
2.20
0.00
1024
30
-
2.40
2.40
2.70
2.70
0.00
1024
30
-
ns
t
-
-
-
ns
8
t
-
-
-
ns
9
t
-
-
-
ns
9
t
Clock to data clock (K→C,K→C)
1.80
2.30
2.80
ns
t
DLL lock time (K, C)
-
-
-
-
-
-
cycles
ns
2
t
KC reset K static to DLL reset
Output Parameters
t
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
C,C HIGH to output valid
C,C HIGH to output hold
-
0.45
-
0.45
-
-0.50
-
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
t
-0.45
-
-
0.45
-
-0.45
-
-
0.45
-
-
0.50
-
t
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
t
-0.45
-
-0.45
-
-0.50
-
t
0.30
-
0.35
-
0.40
-
t
-0.30
-
-0.35
-
-0.40
-
t
0.45
-
0.45
-
0.50
-
3,4,5
3,4,5
t
-0.45
-0.45
-0.50
Set-Up Times
t
AVKH
IVKH
DVKH
Address valid to K,K rising edge
0.35
0.35
0.35
-
-
-
0.40
0.40
0.40
-
-
-
0.50
0.50
0.50
-
-
-
ns
ns
ns
6
R, W inputs valid to K,K rising edge
Data-in and BWx valid to K, K rising edge
t
t
Hold Times
t
KHAX
KHIX
KHDX
K,K rising edge to address hold
0.35
0.35
0.35
-
-
-
0.40
0.40
0.40
-
-
-
0.50
0.50
0.50
-
-
-
ns
ns
ns
6
t
K,K rising edge to R, W inputs hold
K, K rising edge to data-in and BWx hold
t
6109 tbl 11
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
10. The 250MHz speed grade is not available in the 512K x 36-bit option.
11. Industrial temperature range is not available for the 250MHz speed grade.
61.422
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Timing Waveform of Combined Read and Write Cycles
Read A0
1
Write A1
Read A2
Write A3
4
Read A4
Write A5
Write A6
8
NOP
9
NOP
10
NOP
7
3
6
2
5
K
tKHKL
tKLKH
tKHKH
tKHKH
K
R
tIVKH
tKHIX
W
A0
A6
A4
A5
SA
D
A2
A3
A1
tKHAX
tAVKH
tAVKH tKHAX
D11
D30
D31
D51
D10
D50
D60
D61
tDVKH tKHDX
tDVKH tKHDX
Q00
Q40
Q01
Q20
Q21
Q41
Q
tCHQX1
tCHQV
tCHQZ
tCHQX
tCHQX
tCQHQV
tCQHQX
tKHCH
tKLKH
tCHQV
C
tKHKL
tKHKH
tKHKH
tKHCH
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6109 drw 09a
6.42
13
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
required. It is possible to use this device without utilizing the TAP. To
This part contains an IEEE standard 1149.1 Compatible TestAc-
cess Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturingandsystemdiagnostics. InconformancewithIEEE1149.1,
the SRAM contains aTAPcontroller, Instruction register, Bypass Regis-
ter and ID register. TheTAPcontroller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
disable theTAPcontroller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Instruction Coding
JTAG Block Diagram
IR2 IR1 IR0
Instruction
TDO Output
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
IDCODE
2
1
5
4
5
5
SAMPLE-Z
RESERVED
S
A,D
K,K
C,C
SRAM
CORE
SAMPLE/PRELOAD Boundary Scan register
Q
CQ
CQ
RESERVED
RESERVED
BYPASS
Do Not Use
Do Not Use
TDI
Bypass Register
3
BYPASS Reg.
TDO
Identification Reg.
6109tbl 13
NOTES:
Instruction Reg
Control Signal
TAP Controller
.
1. Places Qs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
s
TMS
TCK
3. Bypass register is initialized to Vss when BYPASS instruction is in
voked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.
6109 drw 18
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
1
0
1
1
1
Select IR
0
Run Test Idle
Select DR
0
0
1
1
1
Capture IR
0
Capture DR
0
Shift DR
1
Shift IR
1
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause IR
1
Pause DR
1
0
0
0
0
Exit 2 IR
1
Exit 2 DR
1
1
0
Update DR
0
Update IR
1
6109 drw 17
61.442
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Scan Register Definition
Part
Instruction Register
Bypass Register
ID Register
32 bits
Boundary Scan
107 bits
512Kx36
1Mx18
3 bits
3 bits
1 bit
1 bit
32 bits
107 bits
6109 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
DESCRIPTION
PART NUMBER
Revision Number (31:29)
0x0
Revision Number
0x0284
0x0285
512Kx36
1Mx18
QDRII Burst of 2
71P72604S
71P72804S
Device ID (28:12)
IDT JEDEC ID CODE (11:1)
Allows unique identification of SRAM
vendor.
0x033
1
ID Register Presence
Indicator (0)
Indicates the presence of an ID register.
6109 tbl 15
6.42
15
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Boundary Scan Exit Order
ORDER
PIN ID
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
2
6P
74
3
6N
10C
11D
9C
75
4
7P
76
5
7N
77
6
7R
9D
78
7
8R
11B
11C
9B
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
82
3G
2G
1J
83
84
85
2J
10M
11N
9M
9N
8B
86
3K
3J
7C
87
6C
88
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
8A
89
11L
11M
9L
7A
90
7B
91
6B
92
10L
11K
10K
9J
6A
93
5B
94
5A
95
4A
96
9K
5C
97
10J
11J
11H
10G
9G
4B
98
3A
99
2N
2P
1H
100
101
102
103
104
105
106
107
1A
1P
2B
11F
11G
9F
3R
4R
4P
3B
1C
1B
10F
11E
10E
5P
3D
3C
5N
5R
1D
6109 tbl 16
6109 tbl 17
6109 tbl 18
61.462
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
JTAG DC Operating Conditions
Parameter
Symbol
Min
1.4
1.7
1.3
-0.3
-5
Typ
Max
Unit Note
I/O Power Supply
V
DDQ
DD
IH
IL
IL
IL
0L
OH
OL
-
1.8
-
VDD
V
V
Power Supply Voltage
Input High Level
V
1.9
V
V
DD+0.3
V
Input Low Level
V
-
0.5
V
TCK Input Leakage Current
TMS, TDI Input Leakage Current
TDO Output Leakage Current
Output High Voltage (IOH = -1mA)
Output Low Voltage (IOL = 1mA)
NOTE:
I
-
+5
µA
µA
µA
I
-15
-5
-
+15
+5
I
-
V
V
DDQ - 0.2
-
VDDQ
V
V
1
V
VSS
-
0.2
1
6109 tbl 19
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external
resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol
Value
1.8
Unit Note
Input High Level
V
IH
IL
V
V
ns
Input Low Level
V
0
Input Rise/Fall Time
Input and Output Timing Reference Level
NOTE:
TR/TF
1.0/1.0
0.9
V
1
6109 tbl 20
1. For SRAM outputs see AC test load on page 11.
JTAG Input Test WaveForm
JTAG AC Test Load
1.8 V
0.9 V
Test points
0.9 V
0.9 V
0 V
6109 drw 23
50Ω
Z = 50Ω
0
JTAG Output Test WaveForm
TDO
,
6109 drw 24
Test points
0.9 V
0.9 V
6109 drw 23a
6.42
17
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
TCK Cycle Time
t
CHCH
CHCL
CLCH
MVCH
CHMX
DVCH
CHDX
SVCH
CHSX
CLQV
-
-
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
t
t
-
t
-
t
5
-
t
5
-
t
5
-
t
5
-
t
5
-
Clock Low to Output
Valid
t
0
10
6109 tbl.21
JTAG Timing Diagram
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
TMS
tDVCH
tCHDX
TDI/
SRAM
Inputs
tSVCH
tCHSX
SRAM
Outputs
tCLQV
TDO
6109 drw 19
61.482
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42
19
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Ordering Information
S
XXX
BQ
X
71P72XXX
X
Process
Temperature
Range
Device
Type
Power Speed
Package
o
o
o
Commercial (0 C to +70 C)
Blank
I
o
Industrial (-40 C to +85 C)
G
Restricted Hazardous Substance Device
BQ
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
250(1,2)
200
167
IDT71P72804 1M x 18 QDR II SRAM Burst of 2
IDT71P72604 512K x 36 QDR II SRAM Burst of 2
Notes:
6109 drw 15
1) The 250MHz speed grade is not available in the 512K x36-bit option.
2) Industrial temperature range is not available for the 250MHz speed grade.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
408-284-4532
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
62.402
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18 x -Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial Temperature Range
RevisionHistory
REVISION
DATE
PAGES
p.1-22
DESCRIPTION
0
07/20/05
04/21/06
Released Final datasheet
A
p.1-3,7-9
12,15,20
p. 7,11,17
p.1,7,9,12,20
p.20
Removed x8 and x9 information from the datasheet.
Clarified Max VDDQ equals VDD.
Added Industrial temperature to the datasheet.
Added Green to the datasheet “Restricted hazardous substance device”
Removed "IDT" from orderable part number
B
10/13/08
p.20
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