71P74804S333BQ [IDT]
CABGA-165, Tray;
| 型号： | 71P74804S333BQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-165, Tray 时钟 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance
Information
IDT71P74204
IDT71P74104
IDT71P74804
IDT71P74604
18Mb Pipelined
QDR™II SRAM
Burst of 4
Description
Features
TM
The IDT QDRII Burst of four SRAMs are high-speed synchronous
memories with independent, double-data-rate (DDR), read and write
data ports. This scheme allows simultaneous read and write access for
the maximum device throughput, with four data items passed with each
read or write. Four data word transfers occur per clock cycle, providing
quad-data-rate(QDR)performance. ComparingthiswithstandardSRAM
common I/O (CIO), single data rate (SDR) devices, a four to one in-
crease in data access is achieved at equivalent clock speeds. Consider-
ing that QDRII allows clock speeds in excess of standard SRAM de-
vices, the throughput can be increased well beyond four to one in most
applications.
◆
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
Supports concurrent transactions
-
◆
◆
◆
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
Multiplexed Address Bus One Read or One Write request
per clock cycle
◆
DDR (Double Data Rate) Data Bus
-
Four word burst data per two clock cycles on
each port
Four word transfers per clock cycle
-
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
◆
◆
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
◆
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
The QDRII has a single SDR address bus with read addresses and
write addresses multiplexed. The read and write addresses interleave
with each occurring a maximum of every other cycle. In the event that no
operation takes place on a cycle, the subsequest cycle may begin with
either a read or write. During write operations, the writing of individual
bytes may be blocked through the use of byte or nibble write control
signals.
-
Output Impedance adjustable from 35 ohms to 70
ohms
◆
◆
◆
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package
JTAG Interface
The QDRII has echo clocks, which provide the user with a clock
Functional Block Diagram
(Note1)
DATA
D
REG
WRITE DRIVER
(Note2)
(Note2)
ADD
SA
REG
(Note1)
Q
18M
MEMORY
ARRAY
R
CTRL
LOGIC
W
(Note3)
BWx
K
CLK
CQ
GEN
K
CQ
C
SELECT OUTPUT CONTROL
C
6111 drw16
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36.
BW
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the
and there are 2 signal lines.
is a “nibble write”
MARCH 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
DSC-6111/00
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
that is precisely timed to the data output, and tuned with matching imped- edge of CQ, and the falling edge of CQ. The rising edge of C generates
ance and signal quality. The user can use the echo clock for down- the rising edge ofCQ and the falling edge of CQ. This scheme improves
stream clocking of the data. Echo clocks eliminate the need for the user the correlation of the rising and falling edges of the echo clock and will
to produce alternate clocks with precise timing, positioning, and signal
qualities to guarantee data capture. Since the echo clocks are generated
bythesamesourcethatdrivesthedataoutput, therelationshiptothedata
isnotsignificantlyaffectedbyvoltage, temperatureandprocess, aswould
be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond
SRAM devices that use any form of TTL interface. The interface can be
scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if
necessary. The device has a VDDQ and a separate Vref, allowing the
user to designate the interface operational voltage, independent of the
device core voltage of 1.8V VDD. The output impedance control allows
the user to adjust the drive strength to adapt to a wide range of loads and
transmission lines.
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in two word bursts, with
addressing capability to the burst level.
Clocking
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing that
the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the 4 words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte and nibble write signals can be used to prevent writing any indi-
vidual bytes, or combined to prevent writing one word of the burst.
Read and write operations may be interleaved with each occurring
on every other clock cycle. In the event that two reads or two writes are
requested on adjacent clock cycles, the operation in progress will com-
plete and the second request will be ignored. In the event that both a
read and write are requested simultaneously, the read operation will win
and the write operation will be ignored.
Read operations are initiated by holding the read port select (R) low,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
The QDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the QDRII has an output “echo” clock,
CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, W and BWx/NWx), the ad-
dress, first and third words of the data burst during a write operation.
The K clock is used to clock in the control signals (BWx orNWx) and the
second and fourth words of the data burst during a write operation. The
K and K clocks are also used internally by the SRAM. In the event that
the user disables the C and C clocks, the K and K clocks will be used to
clock the data out of the output register and generate the echo clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the QDRII will be closely aligned to the C andC input,
through the use of an internal DLL. When C is presented to the QDRII
SRAM, the DLL will have already internally clocked the data to arrive at
the device output simultaneously with the arrival of the C clock. The C
and second data item of the burst will also correspond. The third and
with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and presenting the designated write address to the address bus. The
QDRII SRAM will receive the address on the rising edge of clock K. On
the following rising edge of K clock, the QDRII SRAM will receive the first
data item of the four word burst on the data bus. Along with the data, the
byte (BW) or nibble write (NW) inputs will be accepted, indicating which
bytes of the data inputs should be written to the SRAM. On the rising
edge of K, the next word of the write burst and BW/NW will be accepted.
The following K and K will receive the last two words of the four word
burst, with their BW/NW enables.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
fourth data items will follow on the next clock cycle.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and C
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
to it’s lowest value, the ZQ pin may be tied to VDDQ.
6.242
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
2M x 8 -- D[7:0]
2M x 9 -- D[8:0]
D[X:0]
Input Synchronous
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K
clocks during write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data.
BW , BW
0
1
Input Synchronous Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
2M x 9 -- controls D[8:0]
BW , BW
2
3
BW
0
1M x 18 -- BW controls D[8:0] and BW controls D[17:9]
0
1
512K x 36 -- BW controls D[8:0], BW controls D[17:9], BW controls D[26:18] and BW controls D[35:27]
0
1
2
3
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the
rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the
Input Synchronous current portion of the write operations. Nibbles no t written remain unaltered. All the nibble writes are sampled on the same
edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not
written in to the device.
NW0, NW1
Address inputs are sampled on the rising edge of K clock during active read or write operations. These address inputs are
Input Synchronous
SA
multiplexed so a read and write can be initiated on alternate clock cycles. These inputs are ignored when the appropriate
port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising
Output Synchronous edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read
port is deselected, Q[X:0] are automatically three-stated.
Q[X:0]
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write
operation in initiated. Deasserting will deselect the Write port, causing D[X:0] to be ignored. If a write operation has
successfully been initiated, it will continue to completion, ignoring the W on the following clock cycle. This allows the user to
continuously hold W low while bursting data into the SRAM.
Input Synchronous
W
R
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read operation is
initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to
complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read
Input Synchronous
access consists of a burst of four sequential transfer. If a read operation has successfully been initiate d, it will continue to
completion, ignoring the R on the following clock cycle. This allows the user to continuously hold R low while bursting data
from the SRAM.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be
C
used together to deskew the flight times of various devices on the board back to the controller. See application example
for further details.
Input Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be
Input Clock
used together to deskew the flight times of various devices on the board back to the controller. See application example
for further details.
C
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
K
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs
CQ, CQ
and can be used as a data valid indication. These signals are free running and do not stop when the output data is three-
stated.
Output Clock
Input
Output Impedance Matching Input. This input is us ed to tune the device outputs to the sys tem data bus impedance. Q[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can
ZQ
be connected directly to V
which enables the minimum impedance mode. This pin cannot be connected directly to
DDQ,
GND or left unconnected.
6111 tbl 02a
6.42
3
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with
the DLL turned off will be different from those listed in this data sheet. There will be an
increased propagation delay from the incidence of C and C to Q, or K and K to Q as
configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
Input
Doff
TDO
TCK
TDI
Output
Input
Input
Input
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected.
TMS
NC
No Connect No connects inside the package. Can be tied to any voltage level
Input
Reference Voltage input. Static input used to set the reference le vel for HSTL inputs and
VREF
Reference Outputs as well as AC measurement points.
Power
Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power
supply.
VDD
VSS
Ground
Ground for the device. Should be connected to ground of the system.
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply
for HSTL or scaled to the desired output voltage.
VDDQ
6111 tbl 02b
6.442
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 2M x 8
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
7
8
9
10
11
VSS/
SA (2)
SA
NC
SA
VSS/
CQ
W
NW1
NC
K
R
A
B
C
D
E
F
SA (1)
NC
NC
NC
NC
SA
K
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
Q
3
NW0
SA
NC
VSS
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
D
3
D
4
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
NC
Q
4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D
2
Q
2
NC
NC
NC
NC
NC
ZQ
D
5
Q
5
G
H
J
VREF
NC
VDDQ
NC
VREF
Q
1
D
1
NC
NC
NC
NC
NC
K
L
Q
6
D
6
Q
0
NC
NC
NC
NC
D
0
M
N
P
R
D
7
VSS
NC
NC
NC
TDI
NC
Q
7
SA
SA
SA
NC
TCK
SA
SA
SA
SA
SA
TMS
C
6111 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 2M x 9
1
2
3
4
5
6
K
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
11
VSS/
SA
NC
NC
NC
NC
NC
VSS/
CQ
CQ
NC
NC
NC
NC
NC
NC
W
R
A
B
C
D
E
F
SA (2)
SA (1)
NC
NC
SA
NC
K
SA
NC
NC
NC
Q
3
BW
SA
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
D
3
D
4
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
NC
Q
4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D
2
Q
2
NC
NC
NC
NC
NC
ZQ
D
5
Q
5
G
H
J
VREF
NC
VDDQ
NC
VREF
Doff
NC
NC
NC
NC
NC
NC
TDO
Q
1
D
1
NC
NC
NC
NC
NC
NC
NC
K
L
Q
6
D
6
Q
0
NC
NC
NC
D
0
M
N
P
R
D
7
VSS
NC
NC
Q
7
SA
SA
D
8
Q
8
TCK
SA
SA
SA
SA
TMS
TDI
C
6111 tb l 12a
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.642
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 1M x 18
1
2
3
4
5
6
K
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
11
VSS/
NC/
NC
VSS/
CQ
CQ
NC
NC
NC
NC
NC
NC
W
BW
R
A
B
C
D
E
F
1
SA (3)
SA (1)
SA (2)
Q
9
D
9
SA
NC
SA
VSS
VSS
K
SA
NC
Q
8
BW
0
NC
D
10
VSS
NC
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
Q
7
D
8
D
11
Q
10
VSS
NC
D
7
NC
Q
11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D
6
Q
6
Q
12
D
12
V
DD
V
SS
NC
NC
Q
5
D
13
Q
13
VDD
VDD
VDD
VDD
VSS
VSS
VSS
D
5
G
H
J
VREF
NC
VDDQ
VREF
ZQ
Doff
NC
NC
NC
NC
NC
NC
TDO
D
14
Q
4
D
4
NC
Q
14
V
SS
D
3
Q
3
K
L
Q
15
D
15
V
SS
V
SS
NC
Q
2
NC
D
16
VSS
SA
SA
SA
VSS
SA
C
Q
1
D
2
M
N
P
R
D
17
Q
16
VSS
NC
D
1
NC
Q
17
SA
SA
D
0
Q
0
TCK
SA
SA
SA
SA
TMS
TDI
C
6111 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
6.42
7
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 512K x 36
1
2
3
4
5
6
7
8
9
10
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
VSS/
SA (4)
NC/
SA (2)
NC/
SA (1)
VSS
SA (3)
CQ
Q27
D27
D28
Q29
Q30
D30
W
BW2
BW3
SA
K
BW1
BW0
SA
R
A
B
C
D
E
F
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
SA
K
SA
D17
D16
Q16
Q15
D14
Q13
Q17
Q7
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
G
H
J
V
REF
V
V
DD
V
DDQ
V
REF
DDQ
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
Q31
D32
Q24
Q34
D26
D35
TCK
D23
Q23
D24
D25
Q25
Q26
SA
VDD
VDD
VSS
VSS
SA
SA
SA
D12
Q12
D11
D10
Q10
Q9
Q4
D3
K
L
Q11
Q1
M
N
P
R
VSS
SA
D9
SA
D0
SA
SA
SA
SA
TMS
C
6111 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
6.842
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Absolute Maximum Ratings(1) (2)
Symbol
Rating
Value
Unit
Symbol
CIN
Parameter
Input Capacitance
Conditions
Max.
Unit
pF
VTE RM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
5
6
7
VDD = 1.8V
VDDQ = 1.5V
CCLK
CO
Clock Input Capacitance
Output Capacitance
pF
VTE RM
VTE RM
VTE RM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD +0.3
–0.5 to VDD +0.3
–0.5 to VDDQ +0.3
V
V
V
pF
Voltage on Input terminals with
respect to GND
6111 tbl 06
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
Voltage on Output and I/O
terminals with respect to GND.
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
Recommended DC Operating and
Temperture Conditions
IOUT
Continuous Current into Outputs
mA
NOTES:
6111 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Power Supply
Voltage
VDD
1.7
1.8
1.9
V
VDDQ
VSS
I/O Supply Voltage
Ground
1.4
0
1.5
0
1.9
0
V
V
2. VDDQ must not exceed VDD during normal operation.
Input Reference
Voltage
VREF
TA
0.68
0
VDDQ/2
25
0.95
+70
V
Ambient
o
c
(1)
Temperature
6111 tbl 04
NOTE:
1. During production testing, the case temperarure equals the ambient
temperature.
Write Descriptions(1,2)
Signal
BW0
L
BW1
X
BW2
X
BW3
X
NW0
X
NW1
X
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write Nibble 0
Write Nibble 1
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
6111 tbl 09
NOTES:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on the
rising edge of K and again on K. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding BWx or
NWx is held low. The rising edge of K will sample the first and third bytes/
nibbles of the four word burst and the rising edge of K will sample the second
and fourth bytes/nibbles of the four word burst.
2) The availability of the BWx or NWx on designated devices is described in
the pin description table.
3) The QDRII Burst of four SRAM has data forwarding. A read request that is
initiated on the cycle following a write request to the same address will produce
the newly written data in response to the read request.
6.42
9
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Application Example
SRAM #1
SRAM #4
ZQ
Q
ZQ
Q
250
Ω
250
Ω
D
D
VT
K
K
SA
1
W B W0 B W
K
SA
R
C
K
R W BW0 BW1
C
C
C
R
Data In
Data Out
Address
R
R
R
R
R
R
T
V
W
BWx/NWx
MEMORY
VT VT
CONTROLLER
R
R
Return CLK
Source CLK
Return CLK
Source CLK
T
REF
V = V
R = 50Ω
6111 drw 20
61.402
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
µ
A
A
Input Le akage Curre nt
Output Le akage Curre nt
I
IL
V
DD = Max VIN = VSS to VDDQ
-10
-10
+10
+10
Output Disable d
µ
I
OL
333MH
300MH
250MH
Z
-
-
-
-
-
-
-
-
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Z
I
DD
OUT = 0mA (outputs ope n),
Cycle Time > tKHKH Min
Ope rating Curre nt
(x36,x18,x9,x8): DDR
DD
I
Z
mA
1
300MHz
167MHz
333MH
300MH
250MH
Z
Z
De vice De s e le cte d (in NOP state )
I
OUT = 0mA (outputs ope n),
f=Max,
Standby Curre nt: NOP
I
S B1
Z
mA
2
All Inputs <0.2V or > VDD -0.2V
167MHz
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
NOTES:
RQ = 250Ω,
RQ = 250Ω,
I
OH = -15mA
V
DDQ/2-0.12
V
DDQ /2+0.12
V
V
V
V
3,7
4,7
5
V
OH1
I
OL = 15mA
V
DDQ/2-0.12
V
DDQ /2+0.12
V
OL1
I
OH = -0.1mA
V
DDQ -0.2
V
DDQ
V
OH2
I
OL = 0.1mA
V
SS
0.2
6
V
OL2
6111 tb l 10 c
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
6.42
11
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER
SYMBOL
VIH (DC)
VIL (DC)
VIH (AC)
VIL (AC)
MIN
VREF +0.1
-0.3
MAX
VDDQ +0.3
VREF -0.1
-
UNIT
V
NOTES
1,2
Input High Voltage, DC
Input Low Voltage, DC
Input High Voltage, AC
Input Low Voltage, AC
V
1,3
VREF +0.2
-
V
4,5
VREF -0.2
V
4,5
6111 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Undershoot Timing
Overshoot Timing
20% tKHKH (MIN)
VIH
V
DD
+0.5
VDD +0.25
VDD
VSS
VSS-0.25V
VSS-0.5V
VIL
6111 drw 22
6111 drw 21
20% tKHKH (MIN)
AC Test Load
AC Test Conditions
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
Input Reference Level
Input Rise/Fall Time
Symbol
Value
1.7-1.9
1.4-1.9
1.25/0.25
0.75
Unit
V
DD
V
DDQ
V
V
0.75V
V
R EF
IH IL
V /V
V
OUTPUT
VREF
TR/TF
V
=50
Ω
Z0
0.6/0.6
ns
V
Device
Under
Test
Ω
RL = 50
DDQ
V /2
Output Timing Reference Level
Ω
Q
= 250
R
6111tbl 11a
NOTE:
ZQ
DDQ/2
V
1. Parameters are tested with RQ=250Ω
6111 drw 04
1.25V
0.75V
0.25V
6111 drw 06
61.422
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
(3,8)
AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V,TA = 0 TO 70°C)
333MHz
300MHz
250MHz
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Symbol
Parameter
Unit
Notes
Clock Parameters
tKHKH
tKC var
tKHKL
tKLKH
Average clock cycle time (K,K,C,C)
3.00
-
3.47
3.30
-
5.25
4.00
-
6.30
5.00
-
7.88
6.00
-
8.40
ns
ns
Cycle to Cycle Period Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K,C→C)
Cl oc k to clock (K→K,C→C)
Clock to data clock (K→C,K→C)
DLL lock time (K, C)
0.20
0.20
0.20
0.20
0.20
1,5
9
1.20
1.20
1.35
1.35
0.00
1024
30
-
1.32
1.32
1.49
1.49
0.00
1024
30
-
1.60
1.60
1.80
1.80
0.00
1024
30
-
2.00
2.00
2.20
2.20
0.00
1024
30
-
2.40
2.40
2.70
2.70
0.00
1024
30
-
ns
-
-
-
-
-
ns
9
K
tKH H
-
-
-
-
-
ns
10
10
K
t HKH
-
-
-
-
-
ns
tKHCH
1.30
1.45
1.80
2.30
2.80
ns
tKC lock
-
-
-
-
-
-
-
-
-
-
cycles
ns
2
tKC reset K static to DLL reset
Output Parameters
tCHQV
C,C HIGH to output valid
C,C HIGH to output hold
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
-
-0.45
-
0.45
-
0.45
-
0.45
-
-0.45
-
0.45
-
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
tCHQX
-
0.45
-
-0.45
-
-
0.45
-
-0.45
-
-
0.45
-
-
0.45
-
-0.50
-
-
0.50
-
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.50
-
0.25
-
0.27
-
0.30
-
0.35
-
0.40
-
-0.25
-
-0.27
-
-0.30
-
-0.35
-
-0.40
-
0.45
-
0.45
-
0.45
-
0.45
-
0.50
-
3,4,5
3,4,5
tCHQX1
-0.45
-0.45
-0.45
-0.45
-0.50
Set-Up Times
tAVKH
tIV KH
Address valid to K,K rising edge
0.40
0.40
0.30
-
-
-
0.40
0.40
0.30
-
-
-
0.50
0.50
0.35
-
-
-
0.60
0.60
0.40
-
-
-
0.70
0.70
0.50
-
-
-
ns
ns
ns
6
7
Control inputs valid to K,K rising edge
Date-in valid to K, K rising edge
tDVKH
Hold Times
tKHAX
K,K rising edge to address hold
K,Krising edge to control inputs hold
K, K rising edge to data-in hold
0.40
0.40
0.30
-
-
-
0.40
0.40
0.30
-
-
-
0.50
0.50
0.35
-
-
-
0.60
0.60
0.40
-
-
-
0.70
0.70
0.50
-
-
-
ns
ns
ns
6
7
tKHIX
tKHDX
6111 tbl 11
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36)
8. During production testing, the case temperature equals TA.
9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
10. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
6.42
13
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
NOP
7
Write A1
Read A2
4
Write A3
NOP
6
NOP
1
Read A0
3
2
5
K
tKHKL
tKH H
K
tKLKH
tKHKH
K
R
tIVKH
tKHIX
tIVKH
tKHIX
W
A3
A1
A2
SA
D
A0
tKHDX
tDVKH
tKHDX
tDVKH
tAVKH tKHAX
D10
D12
Q02
D13
D32 D33
D11
Q01
D30 D31
Qx2
Q03
Q20
Q21
Q22
Q23
Qx3
Q00
Q
tCHQX
tCHQV
tCHQZ
tCQHQV
tKHCH
tCQHQX
tCHQX1
tCHQX
tCHQV
C
tKHKH
tKH H
K
tKHCH
tKLKH
tKHKL
.
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6111 drw09
61.442
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry
when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the
SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that
resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable
the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI
are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a register. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0
Instruction
EXTEST
TDO Output
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
IDCODE
2
1
5
4
5
5
A,D
S
SAMPLE-Z
RESERVED
K,
K
C,C
SRAM
CO RE
Q
SAMPLE/PRELOAD Boundary Scan register
CQ
CQ
RESERVED
RESERVED
BYPASS
Do Not Use
Do Not Use
TDI
BYPASS R eg.
Identification R eg.
Instruction Reg.
TDO
Bypass Register
3
6111tbl 13
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the
serial shift of the external TDI data.
Control Signal
s
TMS
TCK
TAP Controller
6111 drw 18
3. Bypass register is initialized to Vss when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when
existing the Shift DR states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause DR
1
Pause IR
1
0
0
0
0
Exit 2 DR
1
Exit 2 IR
1
0
1
Update DR
0
Update IR
1
6111 drw 17
6.42
15
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Scan Register Definition
Part
Instrustion Register
Bypass Register
ID Register
32 bits
Boundry Scan
107 bits
512Kx36
1Mx18
3 bits
3 bits
3 bits
1 bit
1 bit
1 bit
32 bits
107 bits
2Mx8/x9
32 bits
107 bits
6111 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
Revision Number (31:29)
Device ID (28:12)
ALL DEVICES
DESCRIPTION
PART NUMBER
000
Revision Number
0 0000 0010 0100 0000 512Kx36
0 0000 0010 0100 0001 1Mx18
0 0000 0010 0100 0010 2Mx9
0 0000 0010 0100 0011 2Mx8
QDRII BURSTOF 4
71P74604S
71P74804S
71P74104S
71P74204S
IDT JEDEC ID CODE (11:1)
000 0011 0011
1
Allows unique identification of SRAM
vendor.
ID Register Presence
Indicator (0)
Indicates the presence of an ID register.
6111 tbl 15
61.462
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit)
ORDER
73
PIN ID
3E
2C
1D
2E
1E
2F
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
PIN ID
1
6R
74
2
6P
75
10C
11D
9C
3
6N
76
4
7P
77
5
7N
78
6
7R
9D
79
3F
7
8R
11B
11C
9B
80
2G
3G
1F
8
8P
81
9
9R
82
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
83
1G
1J
84
85
2J
86
3K
3J
10M
11N
9M
9N
8B
87
7C
88
3L
2L
1K
2K
1M
1L
3N
3M
2N
3P
6C
89
8A
90
11L
11M
9L
7A
91
7B
92
6B
93
10L
11K
10K
9J
6A
94
5B
95
5A
96
4A
97
9K
5C
98
2M
1N
2P
10J
11J
11H
10G
9G
4B
99
3A
100
101
102
103
104
105
106
107
2A
1P
1A
3R
4R
4P
2B
11F
11G
9F
3B
1C
5P
1B
5N
5R
10F
11E
10E
3D
3C
6111 tbl 18a
2D
6111 tbl 16a
6111 tbl 17a
6.42
17
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Boundary Scan Exit Order (1M x 18-Bit, 512K x 36-Bit)
ORDER
PIN ID
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
2
6P
74
3
6N
10C
11D
9C
75
4
7P
76
5
7N
77
6
7R
9D
78
7
8R
11B
11C
9B
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
82
3G
2G
1J
83
84
85
2J
10M
11N
9M
9N
8B
86
3K
3J
7C
87
6C
88
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
89
8A
11L
11M
9L
90
7A
91
7B
92
6B
10L
11K
10K
9J
93
6A
94
5B
95
5A
96
4A
97
9K
5C
98
10J
11J
4B
99
2N
2P
3A
100
101
102
103
104
105
106
107
11H
10G
9G
1H
1P
1A
3R
4R
4P
2B
11F
11G
9F
3B
1C
5P
1B
5N
5R
10F
11E
10E
3D
3C
6111 tbl 18
1D
6111 tbl 16
6111 tbl 17
61.482
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
JTAG DC Operating Conditions
Parame te r
Symbol
DDQ
DD
IH
Min
1.4
Ty p
Max
1.9
Unit
V
Note
Output Powe r S upply
V
-
Powe r Supply Voltage
Inp ut High Le v e l
V
1.7
1.8
1.9
V
V
1.3
-
-
-
-
V
DD+0.3
V
Inp ut Lo w Le v e l
V
IL
-0.3
0.5
V
1
Output High Voltage (IOH = -1mA)
Output Low Voltage (IOL = 1mA)
NOTE:
V
OH
OL
V
DDQ - 0.2
V
DDQ
V
1
V
V
SS
0.2
V
6111 tbl 1 9
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
1
Input High/Low Level
1.3/0.5
1.0/1.0
VDDQ/2
Input Rise/Fall Time
ns
Input and Output Timing Reference Level
V
6111 tbl 20
NOTE:
1. See AC test load on page 12.
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
CHCH
t
TCK Cycle Time
-
-
CHCL
t
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
CLCH
t
-
MVCH
t
-
CHMX
t
5
-
DVCH
t
5
-
CHDX
t
5
-
SVCH
t
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
CHSX
t
5
-
CLQV
t
0
10
6111 tbl.21
JTAG Timing Diagram
TCK
CHCH
t
t
CHCL
t
CLCH
MVCH
DVCH
t
t
CHMX
t
TMS
t
CHDX
TDI/
SRAM
Inputs
t
SVCH
t
CHSX
SRAM
Outputs
CLQV
t
TDO
61 11 drw 19
6.42
19
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
62.402
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Ordering Information
IDT
71P74XXX
S
XXX
BQ
X
Device
Type
Power
Speed
Package
Process
Temperature
Range
Blank
BQ
Commercial (0 C to +70 C)
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
333
300
250
200
167
IDT71P74204 2M x 8 QDR II SRAM Burst of 4
IDT71P74104 2M x 9 QDR II SRAM Burst of 4
IDT71P74804 1M x 18 QDR II SRAM Burst of 4
IDT71P74604 512K x 36 QDR II SRAM Burst of 4
6111 drw 15
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
sramhelp@idt.com
800-544-7726
www.idt.com
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
6.42
21
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18 x -Bit) 71P74604 (512K x 36-Bit)
Advance Information
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Revision History
REVISION DATE
PAGES
DESCRIPTION
O
03/30/04 1-21
Initial Advance Information Data Sheet Release
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