71T75602150PFG [IDT]
Synchronous ZBT SRAMs;型号: | 71T75602150PFG |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Synchronous ZBT SRAMs 静态存储器 |
文件: | 总23页 (文件大小:1292K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
512K x 36, 1M x 18
IDT71T75602
IDT71T75802
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Description
Features
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead
bus cycles when turning the bus around between reads and writes, or
writesandreads. Thus, theyhavebeengiventhenameZBTTM, orZero
Bus Turnaround.
•
•
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
•
•
ZBTTM Feature - No dead cycles between write and read
cycles
Address and control signals are applied to the SRAM during one
clockcycle, andtwocycleslatertheassociateddatacycleoccurs, beit
read or write.
Internally synchronized output buffer enable eliminates the
need to control OE
•
•
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
TheIDT71T75602/802containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
•
•
•
•
•
•
•
•
A Clock Enable CEN pin allows operation of the IDT71T75602/802
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
2.5V I/O Supply (VDDQ)
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Pin Description Summary
A
0-A19
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
TMS
TDI
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
N/A
N/A
TCK
Test Clock
N/A
TDO
TRST
ZZ
Test Data Input
N/A
JTAG Reset (Optional)
Sleep Mode
Asynchronous
Synchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5313 tbl 01
APRIL 2012
1
©2012IntegratedDeviceTechnology,Inc.
DSC-5313/10
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description (cont.)
used to load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
Thedatabuswilltri-statetwocyclesafterthechipisdeselectedorawrite
isinitiated.
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm
100pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA).
The IDT71T75602/802 have an on-chip burst counter. In the burst
mode, the IDT71T75602/802 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
Pin Definitions(1)
Symbol
-A19
Pin Function
I/O
Active
Description
A
0
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,
any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.
R/
W
Read / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
BW1-BW4
(when R/
W
and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-
BW
4
) must be valid. The byte
is sampled
can all be tied low if
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/
high. The appropriate byte(s) of data are written into the device two cycles later. BW BW
always doing write to the entire 36-bit word.
W
1-
4
Chip Enables
Synchronous active low chip enable. CE and CE2 are used with CE2 to enable the IDT71T75602/802 (CE1 or CE2
sampled high or CE sampled low) and1ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
CE1, CE2
ZBTTM has a two cyc2le deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
CE
2
Chip Enable
Clock
I
HIGH Synchronous active high chip enable. CE
but otherwise identical to CE and CE
2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity
1
2.
CLK
I
I/O
I
N/A
This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O -I/O31
I/OP01-I/OP4
Data Input/Output
Linear Burst Order
Output Enable
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered and triggered
by the rising edge of CLK.
LOW
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the
Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
LBO
OE
I
Asynchronous output enable. OE must be low to read data from the 71T75602/802. When OE is high the I/O pins
are in a high-impedance state.OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Test Data Output
O
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs
automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left
floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
HIGH
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
2.5V core power supply.
2.5V I/O Supply.
V
V
Ground.
5313 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.242
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
512Kx36 BIT
MEMORY ARRAY
Address
Address A [0:18]
D
Q
Q
CE1, CE2, CE2
R/W
CEN
D
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5313 drw 01
TMS
TDI
TCK
Data I/O [0:31],
I/O P[1:4]
TDO
JTAG
TRST
(optional)
LBO
1Mx18 BIT
MEMORY ARRAY
Address
Address A [0:19]
D
Q
Q
CE1, CE2, CE2
R/W
CEN
D
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5313 drw 01b
TMS
TDI
TCK
Data I/O [0:15],
I/O P[1:2]
TDO
JTAG
TRST
(optional)
6.42
3
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
2.375
2.375
0
Typ.
Max.
2.625
2.625
0
Unit
V
Ambient
Grade
V
SS
V
DD
VDDQ
Temperature(1)
0° C to +70° C
-40° C to +85° C
V
DD
DDQ
SS
2.5
Commercial
Industrial
OV
OV
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
V
2.5
V
V
0
V
2.5V ± 5%
____
5313 tbl 05
V
IH
IH
IL
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
1.7
V
DD +0.3
V
NOTE:
____
____
1. During production testing, the case temperature equals the ambient temperature.
V
1.7
V
DDQ+0.3
0.7
V
V
-0.3(1)
V
5313 tbl 03
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
Pin Configuration — 512K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O22
I/O
I/O
9
8
I/O23
(1)
VDD
V
SS
(1)
V
DD
DD
VDD
(1)
V
VDD
VSS
ZZ
I/O
I/O
I/O24
I/O25
7
6
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O5
I/O4
I/O3
I/O2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
1
0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5313 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with
normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left
unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG
circuit will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
6.42
4
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 1Mx 18
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
Industrial
Unit
(2)
V
V
V
V
TERM
Terminal Voltage with
Respect to GND
V
-0.5 to +3.6
-0.5 to +3.6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
(3,6)
NC
NC
NC
DDQ
1
80
79
78
77
TERM
Terminal Voltage with
Respect to GND
V
V
V
A
NC
NC
10
-0.5 to VDD
-0.5 to VDD
2
3
V
4
(4,6)
VDDQ
TERM
Terminal Voltage with
Respect to GND
5
VSS
-0.5 to VDD +0.5
-0.5 to VDD +0.5
76
75
74
73
VSS
NC
NC
6
NC
I/OP1
I/O
7
(5,6)
TERM
Terminal Voltage with
Respect to GND
I/O8
8
7
-0.5 to VDDQ +0.5 -0.5 to VDDQ +0.5
I/O9
9
72
71
70
I/O
6
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VDDQ
VDDQ
Operating Ambient
Temperature
(7)
TA
0 to +70
-40 to +85
oC
I/O10
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
I/O
5
4
I/O11
(1)
V
DD
VSS
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
2.0
-55 to +125
-55 to +125
2.0
oC
oC
W
(1)
V
DD
DD
(1)
VDD
V
VDD
TSTG
VSS
ZZ
I/O
I/O
I/O12
I/O13
3
P
T
2
VDDQ
V
V
DDQ
SS
IOUT
DC Output Current
50
50
mA
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
5313 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
VSS
VSS
,
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5313 drw 02a
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary; however,
the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp
up.
Top View
100 TQFP
NOTES:
7. During production testing, the case temperature equals TA.
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the
input voltage is ≥ VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42
should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38,
39 and 43 could be left unconnected “NC” and the JTAG circuit will remain
disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
165 fBGA Capacitance
100-Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
CIN
V
7
7
pF
CIN
V
5
7
pF
CI/O
V
pF
CI/O
V
pF
5313 tbl 07b
5313 tbl 07
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
5313 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
5
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 512K X 36, 119 BG5A(1,2)
1
2
3
4
6
7
Top View
A
B
C
D
E
F
V
DDQ
A6
A4
A3
A2
A18
A8
A16
V
DDQ
NC
NC
CE2
A7
ADV/LD
A9
NC
NC
CE2
A15
V
DD
A12
I/O16
I/O17
I/OP3
I/O18
I/O19
I/O21
I/O23
V
SS
SS
SS
NC
CE1
OE
V
SS
SS
SS
I/OP2
I/O13
I/O12
I/O11
I/O9
I/O15
I/O14
V
V
V
V
V
DDQ
I/O20
I/O22
V
DDQ
I/O10
I/O8
G
H
J
A17
BW3
BW2
V
SS
DD(1)
SS
R/W
V
SS
DD(1)
SS
V
DDQ
I/O24
I/O25
V
DD
V
V
DD
V
V
DD
V
DDQ
I/O7
I/O5
K
L
I/O26
I/O27
V
CLK
NC
V
I/O6
I/O4
I/O3
BW4
BW1
M
N
P
R
T
V
DDQ
I/O29
I/O31
NC
V
V
V
SS
V
V
V
SS
V
DDQ
I/O1
I/O0
NC
I/O28
I/O30
CEN
A1
SS
SS
SS
SS
I/O2
I/OP1
I/OP4
A5
A0
V
DD
V
DD(1)
A13
LBO
NC
NC
A10
A11
A14
NC(3)
ZZ
NC/TRST(2, 4)
NC/TMS (2)
NC/TCK(2) NC/TDO(2)
U
V
DDQ
NC/TDI(2)
V
DDQ
5313 tbl 25
Pin Configuration — 1M X 18, 119 BGA(1,2)
1
2
3
4
5
6
7
Top View
A
B
C
D
E
F
V
DDQ
A6
A4
A3
A2
A19
A8
A9
A13
A16
VDDQ
NC
NC
I/O8
NC
CE2
A7
ADV/LD
NC
NC
NC
I/O7
CE2
A17
V
DD
NC
I/O9
NC
I/O10
NC
V
SS
SS
SS
NC
CE1
OE
V
SS
SS
SS
SS
SS
I/OP1
NC
I/O6
NC
I/O4
V
V
V
V
V
V
V
DDQ
V
DDQ
I/O5
NC
G
H
J
NC
A18
BW2
I/O11
V
SS
R/W
V
DDQ
V
DD
V
DD(1)
V
DD
V
DD(1)
V
DD
V
DDQ
I/O3
NC
K
L
NC
I/O12
NC
V
SS
SS
SS
SS
SS
CLK
NC
V
SS
NC
I/O13
V
I/O2
BW
1
M
N
P
R
T
V
DDQ
I/O15
NC
I/O14
NC
V
V
V
V
V
V
SS
NC
I/O1
V
DDQ
NC
I/O0
NC
ZZ
CEN
A1
SS
SS
I/OP2
A5
A0
NC
NC
V
DD
V
DD(1)
A12
LBO
NC
A10
NC/TMS(2)
A15
NC/TDI(2)
NC(3)
NC/TCK(2) NC/TDO(2)
A14
A11
NC/TRST(2, 4)
U
V
DDQ
V
DDQ
5313 tb l 25a
NOTES:
1. J3, R5, and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are
possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3, U4 and U6
could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
3. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.642
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
Chip(5)
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
R/W
Enable
(2 cycles later)
L
L
L
L
H
X
Select
Select
X
L
L
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D(7)
Q(7)
D(7)
H
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q(7)
(Advance burst counter)(2)
L
L
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
HiZ
HiZ
X
X
DESELECT / NOOP
X
NOOP
SUSPEND(4)
H
Previous Value
5313 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst
cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state
two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
BW
1
BW
2
BW
3
BW4
OPERATION
R/W
H
L
READ
X
X
X
L
X
L
WRITE ALL BYTES
L
L
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1
)
L
L
H
L
H
H
L
H
H
H
L
(2)
WRITE BYTE 2 (I/O[8:15], I/OP2
)
L
H
H
H
H
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3
)
L
H
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4
)
L
H
H
NO WRITE
L
H
5313 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
7
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5313 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5313 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A
0 - A18)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O[0:31], I/O P[1:4]
5313drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay
from the rising edge of clock.
6.42
8
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
(1)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
H
X
X
H
X
X
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
n+2
A
1
Q0
n+3
X
X
L
H
X
L
L
Q0+1 Deselect or STOP
n+4
H
L
L
Q1
NOOP
n+5
A
2
X
X
L
Z
Z
Load read
n+6
X
X
H
L
X
H
L
Burst read
n+7
Q2
Deselect or STOP
n+8
A
3
L
L
Q2+1 Load write
n+9
X
X
L
H
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
Deselect or STOP
NOOP
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A
4
L
D3
X
X
X
X
L
L
H
X
L
X
X
L
D3+1
H
L
D4
A
5
6
7
Z
Z
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
A
A
H
L
L
L
X
L
L
L
D5
X
X
H
X
L
H
L
X
L
L
Q6
A
8
X
X
L
X
X
L
D7
X
H
L
X
L
D7+1
A
9
Q8
5313 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Read Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
X
L
X
X
L
L
L
X
X
X
X
X
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
X
Q0
Contents of Address A Read Out
0
5313 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
9
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
X
X
X
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
H
H
H
H
L
X
X
X
X
L
Clock Setup Valid, Advance Counter
X
X
X
Q0
Address A Read Out, Inc. Count
0
Q0+1
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
Q0+2
A
X
X
1
Q0+3
Address A0+3 Read Out, Load A
1
H
H
L
X
X
L
Q0
Address A
Address A
0
Read Out, Inc. Count
Read Out, Inc. Count
Q1
1
A
2
Q1+1
Address A1+1 Read Out, Load A
2
5313 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
X
L
X
X
L
L
L
L
L
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
D0
Write to Address A
0
5313 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
H
H
H
H
L
X
X
X
X
L
X
X
X
D0
Address A Write, Inc. Count
0
D0+1
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
D
0+2
0+3
A
X
X
1
D
Address A0+3 Write, Load A
1
X
X
L
H
H
L
X
X
L
D0
Address A
Address A
0
Write, Inc. Count
Write, Inc. Count
D1
1
A
2
D1+1
Address A1+1 Write, Load A
2
5313 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
61.402
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A
1
Clock Valid
X
X
X
X
L
H
H
L
Q0
Q0
Q0
Clock Ignored. Data Q
0
0
is on the bus.
is on the bus.
Clock Ignored. Data Q
A
2
3
4
Address A
Address A
Address A
0
1
2
Read out (bus trans.)
Read out (bus trans.)
Read out (bus trans.)
A
A
L
L
Q1
L
L
Q2
5313 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
H
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A
1
X
X
X
X
L
H
H
L
Clock Ignored.
Clock Ignored.
A
2
3
4
D0
Write Data D
Write Data D
Write Data D
0
A
A
L
L
D1
1
L
L
D2
2
5313 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(2)
I/O(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE
H
H
L
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
?
Z
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Deselected.
A
0
Address and Control meet setup.
Deselected or STOP.
X
H
L
A
1
Q0
Address A
Deselected or STOP.
Address A Read out. Deselected.
0
Read out. Load A
1.
X
X
H
H
L
X
L
Z
Q
Z
Z
1
1
A
2
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
Q2
Address A Read out. Deselected.
2
5313 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
H
H
L
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
?
Z
Z
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
A
0
Address and Control meet setup.
Deselected or STOP.
X
X
L
H
L
X
L
A
1
D0
Address D
Deselected or STOP.
Address D Write in. Deselected.
0
Write in. Load A
1.
X
X
X
X
L
H
H
L
X
X
L
Z
D
Z
Z
1
1
A
2
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
D2
Address D Write in. Deselected.
2
5313 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
61.422
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
V
DD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
LBO, JTAG and ZZ Input Leakage Current
Output Leakage Current
|ILI
|
V
V
DD = Max., VIN = 0V to VDD
30
5
µA
µA
V
|ILO
|
OUT = 0V to VDDQ, Device Deselected
V
OL
OH
Output Low Voltage
IOL = +6mA, VDD = Min.
0.4
___
V
Output High Voltage
IOH = -6mA, VDD = Min.
2.0
V
5313 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD, and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
200MHz
166MHz
150MHz
133MHz
100MHz
Symbol
Parameter
Test Conditions
Unit
Com'l
Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind
Device Selected, Outputs Open,
Operating Power
Supply Current
IDD
ADV/LD = X, VDD = Max.,
275
295
60
245 265
215
40
60
60
40
235
60
80
80
60
195 215
175
40
45
60
40
195
60
65
80
60
mA
(2)
V
IN > VIH or < VIL, f = fMAX
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
CMOS Standby Power
Supply Current
ISB1
V
,
40
80
60
40
40
70
60
40
60
90
80
60
40
50
60
40
60
70
80
60
mA
mA
mA
Device Deselected, Outputs Open,
Clock Running Power
Supply Current
ISB2
V
DD = Max., VIN > VHD or < VLD,
100
80
(2.3)
f = fMAX
Device Selected, Outputs Open,
Idle Power
Supply Current
ISB3
CEN > VIH, VDD = Max.,
(2,3)
V
IN > VHD or < VLD, f = fMAX
Device Selected, Outputs Open,
Full Sleep Mode
Supply Current
IZZ
CEN < VIH, VDD = Max.,
60
mA
V
IN > VHD or < VLD, f = fMAX(2,3),ZZ > VHD
5313 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ/2
AC Test Load
AC Test Conditions
Input Pulse Levels
50Ω
0 to 2.5V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
5313 drw 04
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
Figure 1. AC Test Load
6
5
4
See Figure 1
•
5313 tbl 23
ΔtCD
(Ty pical , ns)
3
2
•
•
1
•
•
20 30 50
80 100
Capacit ance(pF )
200
5313 dr 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
13
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 2.5V +/-5%, Commercial and Industrial
Temperature Ranges)
200MHz
166MHz
150MHz
133MHz
100MHz
Symbol
Parameter
Min. Max. Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
____
____
____
____
____
t
CYC
Clock Cycle Time
5
6
6.7
7.5
10
ns
MHz
ns
____
____
____
____
____
(1)
Clock Frequency
200
166
150
133
100
tF
(2)
CH
____
____
____
____
____
Clock High Pulse Width
Clock Low Pulse Width
1.8
1.8
1.8
1.8
2.0
2.0
2.2
2.2
3.2
3.2
t
(2)
CL
____
____
____
____
____
ns
t
Output Parameters
____
____
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.2
____
3.5
____
3.8
____
4.2
____
5
____
ns
ns
ns
tCDC
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
1.5
1.5
____
____
____
____
____
(3,4,5)
(3,4,5)
tCLZ
Clock High to Data High-Z
1.0
3
1.0
3
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
ns
tCHZ
____
____
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
3.2
3.5
3.8
4.2
5
____
____
____
____
____
(3,4)
0
0
0
0
0
tOLZ
(3,4)
OHZ
____
____
____
____
____
3.2
3.5
3.8
4.2
5
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
Address Setup Time
1.4
1.4
1.5
1.5
1.5
1.5
1.7
1.7
2.0
2.0
ns
ns
t
____
____
____
____
____
t
Data In Setup Time
1.4
1.5
1.5
1.7
2.0
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Read/Write (R/W) Setup Time
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
ns
ns
ns
ns
t
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
5313 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is faster than tCLZ (device turn-on) at a given temperature and voltage. The specs
as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ, which is a Max.
parameter (worse case at 70 deg. C, 2.375V).
61.442
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
6.42
15
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
6.42
16
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
6.42
17
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
6.42
18
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
6.42
19
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification
t
JCYC
t
JR
tJF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
t
JH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M5313 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
Scan Register Sizes
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
t
5(1)
ns
____
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
t
5(1)
ns
____
Note (1)
____
t
50
ns
I5313 tbl 03
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I5313 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
20
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field
Revision Number (31:28)
Value
Description
0x2
0x220, 0x222
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71T75602 and 71T75802, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I5313 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5313 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
21
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
5313 drw 11
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
X
X
XXXX
S
XX
XX
Device
Type
Power Speed Package
Blank Tube or Tray
Tape and Reel
8
Blank Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
I
PF
PFG
BG
100-Pin Plastic Thin Quad Flatpack (TQFP)
TQFP - Green
119 Ball Grid Array (BGA)
BGA - Green
BGG
*200
166
150
133
100
Clock Frequency in Megahertz
71T75602
71T75802
512Kx36 Pipelined ZBT SRAM
1Mx18 Pipelined ZBT SRAM
5313 drw 12
* 200MHz available Only for IDT71T75802
6.42
22
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev
0
Date
Pages
Description
04/20/00
05/25/00
Created New Datasheet
1
Pg.1,14,15,25
Pg. 1,2,14
Pg. 23
Added 166MHz speed grade offering
Corrected error in ZZ Sleep Mode
AddBQ165 Package Diagram Outline
Pg. 24
Corrected 119BGA Package Diagram Outline.
Corrected topmark on ordering information
Removed reference of BQ165 Package
Pg. 25
2
08/23/01
Pg. 1,2,24
Pg. 7
Removed page of the 165 BGA pin configuration
Removed page of the 165 BGA package diagram outline
Corrected 3.3V to 2.5V in Note 2
Pg. 23
3
4
5
10/16/01
10/29/01
12/21/01
Pg. 6
Pg. 13
Improved DC Electrical characteristics-parameters improved: Icc, ISB2, ISB3, IZZ.
Added clarification to JTAG pins, allow for NC. Added 36M address pin locations.
Revised 166MHz tCDC(min), tCLZ(min) and tCHZ(min) to 1.0ns
Pg. 4-6
Pg. 14
06/07/02
Pg. 1-3,6,13,20,21 Added complete JTAG functionality.
Pg. 2,13
Added notes for ZZ pin internal pulldown and ZZ leakage current.
Pg. 13,14,24
Added 200MHz and 225MHz to DC and AC Electrical Characteristics. Updated supply current for
Idd, ISB1, ISB3 and Izz.
6
7
8
11/19/02
05/23/03
04/01/04
Pg.1-24
Pg.13
ChangeddatasheetfromAdvancedInformationtofinalrelease.
Updated DC Electrical characteristics temperature and voltage range table.
Pg.4,5,13,14,24 Added I-temp to the datasheet.
Pg.5
Updated 165 BGA Capacitance table.
Pg. 1
Updated logo with new design.
Pg. 4,5
Pg. 6
Clarified ambient and case operating temperatures.
Updated pin I/O number order for the 119 BGA.
Pg. 23
Updated 119BGA Package Diagram Drawing.
9
10/01/08
04/04/12
Pg. 1,13,14,24
Deleted 225MHz part, added 200MHz Industrial grade and added green packages. Updated the
orderinginformationbyremovingthe“IDT”notation.
Updated text on Page 2 last paragraph. Added Note to ordering information and updated to include
tube or tray and tape & reel.
10
.
Pg. 2,22
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
sramhelp@idt.com
408-284-4532
6024 Silver Creek Valley Rd
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax:408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc. All brands or products are the trademarks or registered trademarks of their respective owners.
ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
6.42
1
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