71V016SA12BFG38 [IDT]
Standard SRAM, 64KX16, 12ns, CMOS, PBGA48;
| 型号： | 71V016SA12BFG38 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 64KX16, 12ns, CMOS, PBGA48 静态存储器 |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS Static RAM
for Automotive Applications
1 Meg (64K x 16-Bit)
IDT71V016SA
Features
Description
◆
64K x 16 advanced high-speed CMOS Static RAM
TheIDT71V016isa1,048,576-bithigh-speedStaticRAMorganized
as64Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneedsandautomotiveapplications.
◆
Equal access and cycle times
— Automotive:12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
◆
◆
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputsandoutputsoftheIDT71V016areLVTTL-compatibleandoperation
isfromasingle3.3Vsupply.Fullystaticasynchronouscircuitryisused,
requiringnoclocks orrefreshforoperation.
◆
◆
◆
◆
Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Functional Block Diagram
Output
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
OE
Enable
Buffer
Address
Buffers
Row / Column
Decoders
A0 – A15
I/O15
High
Byte
I/O
8
8
Chip
Enable
Buffer
CS
Buffer
8
I/O
Sense
Amps
and
Write
Drivers
16
64K x 16
Memory
Array
Write
Enable
Buffer
WE
I/O7
I/O0
Low
Byte
I/O
8
8
Buffer
BHE
BLE
Byte
Enable
Buffers
6818 drw 01
DECEMBER 2004
1
©2004 IntegratedDeviceTechnology,Inc.
DSC-6818/00
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
1
2
3
4
5
6
A
B
C
D
E
A0
A1
A2
NC
BLE
OE
A4
A3
A2
A1
A0
1
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
A6
3
I/O8
I/O9
VSS
VDD
I/O14
I/O15
NC
A3
A5
A4
A6
I/O0
I/O2
VDD
VSS
I/O6
I/O7
BHE
I/O10
I/O11
I/O12
I/O13
NC
CS
A7
4
OE
5
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VDD
I/O11
I/O10
I/O9
I/O8
NC
I/O1
I/O3
I/O4
I/O5
WE
A11
C
6
S
I/O0
7
NC
NC
A14
A12
A9
A7
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
8
9
NC
A15
A13
A10
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
F
G
H
A8
NC
A8
6818 tbl 02a
FBGA (BF48-1)
Top View
A14
A9
A13
A10
A12
A11
Pin Description
NC
NC
A0 – A15
Address Inputs
Input
6818 drw 02
Chip Select
Input
Input
Input
Input
Input
I/O
CS
SOJ/TSOP
Top View
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
WE
OE
BHE
BLE
I/O0 – I/O15
VDD
Power
Gnd
VSS
Ground
6818 tbl 01
Truth Table(1)
I/O0-I/O7
I/O8-I/O15
Function
CS
H
L
OE
X
L
WE
X
H
H
H
L
BLE
BHE
X
H
L
X
L
High-Z
DATAOUT
High-Z
High-Z
High-Z
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
L
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
L
DATAOUT
DATAIN
DATAIN
High-Z
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
L
L
H
X
H
DATAIN
High-Z
L
H
X
X
H
High-Z
L
High-Z
High-Z
6818 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.422
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage
Symbol
Rating
Value
Unit
VDD
Supply Voltage Relative to
VSS
–0.5 to +4.6
V
Grade
Temperature
-40°C to +125°C
-40°C to +105°C
-40°C to +85°C
0°C to +70°C
VSS
0V
0V
0V
0V
VDD
Automotive Grade 1
Automotive Grade 2
Automotive Grade 3
Automotive Grade 4
See Below
See Below
See Below
Terminal Voltage Relative
to VSS
–0.5 to VDD+0.5
V
VIN, VOUT
TBIAS
TJ
Temperature Under Bias
Junction Temperature Page
Storage Temperature
Power Dissipation
–55 to +125
–40 to +150
–65 to +150
1.25
oC
oC
oC
W
See Below
6818 tbl 04
TSTG
PT
Recommended DC Operating
Conditions
IOUT
NOTE:
DC Output Current
50
mA
Symbol
VDD
Vss
Parameter
Min.
Typ.
Max.
Unit
V
6818 tbl 03
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
Supply Voltage
3.0
3.3
3.6
Ground
0
0
0
V
____
VIH
Input High Voltage
Input Low Voltage
2.0
VDD+0.3(1)
0.8
V
–0.3(1)
V
____
VIL
Capacitance
6818 tbl 05
NOTE:
(TA = +25°C, f = 1.0MHz, SOJ/TSOP package)
1. Refer to maximum overshoot/undershoot diagram below. The measured
voltage at device pin should not exceed half sinusoidal wave with 2V peak and
half period of 2ns.
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
6
7
pF
CI/O
pF
MaximumOvershoot/Undershoot
6818 tbl 06
NOTE:
+2V
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
V
IH
2ns
2 ns
V
IL
-2V
6818 drw 12
DC Electrical Characteristics
(VDD = Min. to Max., Automotive Temperature Ranges)
Automotive
Temperature
Grade
IDT71V016SA
Symbol
Parameter
Input Leakage Current
Test Conditions
Min.
Max.
Unit
___
___
___
___
___
1 and 2
3 and 4
1 and 2
3 and 4
5
1
5
1
|ILI|
VDD = Max., VIN = VSS to VDD
µA
|ILO|
Output Leakage Current
VDD = Max., CS = VIH, VOUT = VSS to VDD
µA
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 8mA, VDD = Min.
IOH = -4mA, VDD = Min.
0.4
___
2.4
V
6818 tbl 07
6.42
3
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V, Automotive Temperature Ranges)
71V016SA12
71V016SA15
71V016SA20
Parameter
Automotive Grade
Automotive Grade
Automotive Grade
Unit
Symbol
1
2
100
75
3 and 4
1
80
70
2
80
70
3 and 4
1
80
70
2
80
70
3 and 4
Max.
110
75
90
75
80
70
80
70
Dynamic Operating Current
ICC
mA
mA
(3)
CS < VLC, Outputs Open, VDD = Max., f = fMAX
Typ.(4)
Dynamic Standby Power Supply Current
CS > VHC, Outputs Open, VDD = Max., f = fMAX
ISB
45
5
45
5
35
2
35
5
35
5
30
2
30
5
30
5
30
2
(3)
Full Standby Power Supply Current (static)
1
ISB
mA
CS > VHC, Outputs Open, VDD = Max., f = 0(3)
6818 tbl 8
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are measured at 3.3V, 25°C and with equal read and write cycles. These parameter is guaranteed by device characterization but is not production
tested.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
6818 tbl 09
3.3V
320
AC Test Loads
W
OUT
DATA
+1.5V
350
W
5pF*
50
W
0
Z =
I/O
6818 drw 04
50W
*Including jig and scope capacitance.
30pF
6818 drw 03
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
7
6
DtAA,
5
4
3
tACS
(Typical, ns)
2
1
•
180
8 20 40 60 80 100 120 140 160
200
6818 drw 05
CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
6.442
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = Min. to Max., Automotive Temperature Ranges)
71V016SA12
71V016SA15
71V016SA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
12
15
20
ns
ns
ns
ns
____
____
____
tAA
tACS
Address Access Time
12
15
20
____
____
____
Chip Select Access Time
Chip Select Low to Output in Low-Z
12
15
20
____
____
____
(1,2)
4
5
5
tCLZ
____
____
____
(1,2)
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
6
6
8
ns
ns
ns
tCHZ
____
____
____
tOE
6
6
8
____
____
____
(1,2)
1
1
1
tOLZ
____
____
____
(1,2)
Output Enable High to Output in High-Z
6
6
8
ns
tOHZ
tOH
tBE
Output Hold from Address Change
Byte Enable Low to Output Valid
4
—
4
—
4
—
ns
ns
____
—
6
—
6
8
____
____
____
(1,2)
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
Chip Select Low toPower Up
1
1
1
ns
ns
ns
ns
tBLZ
____
____
____
(1,2)
6
6
8
tBHZ
____
____
____
(3)
0
0
0
tPU
____
____
____
(3)
Chip Select High toPower Down
12
15
20
tPD
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tAW
tCW
tBW
tAS
Write Cycle Time
12
8
8
9
0
0
8
6
0
15
10
10
10
0
20
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
tWR
tWP
tDW
tDH
Address Hold from End of Write
Write Pulse Width
0
0
10
8
12
9
Data Valid to End of Write
Data Hold Time
0
0
____
____
____
(1,2)
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
3
3
3
ns
tOW
____
____
____
(1,2)
6
6
8
ns
tWHZ
6818 tbl 10
NOTES:
1. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ, and tWHZ is less than tOW for any given device.
2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
3. This parameter is guaranteed by design and not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
t
OH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
6818 drw 06
2. Deviceiscontinuouslyselected,CSisLOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
t
RC
ADDRESS
OE
t
AA
t
OH
(3)
t
OHZ
t
OE
(3)
tOLZ
CS
(2)
t
ACS
(3)
(3)
(3)
t
CHZ
t
CLZ
BLE
BHE,
(2)
t
BE
(3)
t
BHZ
t
BLZ
DATAOUT
DATAOUT VALID
t
PD
t
PU
ICC
V
DD
Supply
Current
I
SB
6818 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. AddressmustbevalidpriortoorcoincidentwiththelaterofCS,BHE,or BLE transitionLOW;otherwisetAA isthelimitingparameter.
3. Transitionismeasured±200mVfromsteadystate.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
t
WC
ADDRESS
t
AW
C
S
(2)
(5)
(5)
t
CW
t
CHZ
t
BW
,
BHE BLE
t
WR
t
BHZ
t
WP
WE
t
AS
(5)
t
WHZ
(5)
t
OW
(3)
DATAOUT
DATAIN
PREVIOUS DATA VALID
DATA VALID
t
DH
t
DW
DATAIN VALID
6818 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuouslyHIGH. Ifduringa WEcontrolledwrite cycle OEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOEis HIGHduringaWE controlledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. Ifthe CSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.462
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
t
WC
ADDRESS
t
AW
C
S
(2)
t
AS
t
CW
t
BW
BHE, BLE
t
WP
t
WR
WE
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
6818 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
t
WC
ADDRESS
t
AW
C
S
(2)
t
CW
t
AS
t
BW
BHE, BLE
t
WP
t
WR
WE
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
6818 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuouslyHIGH. Ifduringa WEcontrolledwrite cycle OEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOEis HIGHduringaWE controlledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. Ifthe CSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
7
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
X
IDT 71V016
SA
XX
XXX
X
X
Process/
Device
Type
Power Speed Package
Tape & Reel
Temperature
Range
8
Automotive Grade 1 (-40°C to +125°C)
Automotive Grade 2 (-40°C to +105°C)
Automotive Grade 3 (-40°C to +85°C)
Automotive Grade 4 (0°C to +70°C)
1
2
3
4
Restricted hazardous substance device
G
Y
400-mil SOJ (SO44-1)
PH
BF
400-mil TSOP Type II (SO44-2)
7.0 x 7.0 mm FBGA (BF48-1)
12
15
20
Speed in nanoseconds
6818 drw 11
6.482
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev
0
Date
12/17/04
Page
p. 1-8
Description
ReleasedAutomotivedatasheet
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for SALES:
for Tech Support:
800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com
800-544-7726
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9
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