71V124HSA10PHGI [IDT]
Standard SRAM, 128KX8, 10ns, CMOS, PDSO32;
| 型号： | 71V124HSA10PHGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 128KX8, 10ns, CMOS, PDSO32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
IDT71V124SA/HSA
Ground Pinout
Features
Description
◆
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
TheIDT71V124isa1,048,576-bithigh-speedstaticRAMorganized
as128Kx8.ItisfabricatedusingIDT’shigh-performance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds. The JEDECcenterpower/GNDpinoutreduces
noisegenerationandimprovessystemperformance.
◆
◆
Equal access and cycle times
– Commercial:10/12/15/20ns
– Industrial:10/12/15/20ns
◆
◆
◆
◆
◆
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
TheIDT71V124has anoutputenablepinwhichoperates as fastas
5ns, with address access times as fast as 9ns available. All bidirec-
tionalinputs andoutputs oftheIDT71V124areLVTTL-compatibleand
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
FunctionalBlockDiagram
A0
•
•
•
•
•
•
1,048,576-BIT
MEMORY ARRAY
ADDRESS
DECODER
A16
8
8
I/O0 - I/O7
I/O CONTROL
.
8
WE
OE
CS
CONTROL
LOGIC
3873 drw 01
OCTOBER 2008
1
DSC-3873/09
©2007-IntegratedDeviceTechnology,Inc.
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
PinConfiguration
Symbol
Rating
Value
Unit
A
16
A
A
A
A
0
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Supply Voltage Relative
to GND
-0.5 to +4.6
V
VDD
1
2
3
A15
A14
A13
Terminal Voltage Relative
to GND
-0.5 to VDD+0.5
V
VIN, VOUT
CS
I/O
I/O1
5
6
7
8
OE
I/O
I/O
0
7
SO32-2
SO32-3
SO32-4
Commercial
Operating Temperature
6
-0 to +70
VDD
GND
TA
oC
VDD
GND
I/O
I/O
WE
9
Industrial
-40 to +85
2
10
11
12
13
14
15
16
I/O
I/O
5
Operating Temperature
4
3
.
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
1.25
oC
oC
W
A
A
A
A
A
12
A4
A5
A6
A7
11
10
9
TSTG
P
T
8
IOUT
DC Output Current
50
mA
3873 drw 02
3873 tbl 02
NOTE:
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliabilty.
SOJ and TSOP
Top View
Truth Table(1)
RecommendedOperatingTempera-
ture and Supply Voltage
I/O
Function
CS
OE
WE
L
L
H
DATAOUT Read Data
DATAIN Write Data
Grade
Temperature
0°C to +70°C
-40°C to +85°C
GND
VDD
L
X
H
X
L
Commercial
Industrial
0V
See Below
L
H
High-Z Output Disabled
0V
See Below
H
X
High-Z Deselected – Standby
3873 tbl 02a
3873 tbl 01
NOTE:
RecommendedDCOperating
Conditions
1. H = VIH, L = VIL, X = Don't care.
Symbol
Parameter
Min. Typ.
Max.
Unit
V
Capacitance
(1)
V
DD
Supply Voltage
3.15
3.0
3.3
3.3
3.6
3.6
0
(TA = +25°C, f = 1.0MHz, SOJ package)
(2)
DD
V
Supply Voltage
Ground
V
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
V
SS
IH
IL
0
0
V
CIN
V
6
7
pF
V
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(3)
V
____
CI/O
V
pF
____
V
–0.5(1)
0.8
V
3873 tbl 03
NOTE:
3873 tbl 04
1. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
NOTES:
1. For 71V124SA10 only.
2. For all speed grades except 71V124SA10.
3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
DD = Max., VIN = GND to VDD
DD = Max.,CS IH, VOUT = GND to VDD
OL = 8mA, VDD = Min.
OH = –4mA, VDD = Min.
Min.
Max.
Unit
µA
µA
V
___
|
V
5
5
___
___
|
V
= V
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
3873 tbl 05
2
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics(1, 2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V124SA10
71V124SA12
71V124SA15
71V124SA20
Symbol
Parameter
Dynamic Operating Current
Com'l
Ind
Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
mA
ICC
145
150
130
140
100
120
95
115
(3)
CS < VLC, Outputs Open, VDD = Max., f = fMAX
mA
I
SB
Dynamic Standby Power Supply Current
45
10
50
10
40
10
40
10
35
10
40
10
30
10
35
10
(3)
CS > VHC, Outputs Open, VDD = Max., f = fMAX
mA
ISB1
Full Standby Power Supply Current (static)
CS > VHC, Outputs Open, VDD = Max., f = 0(3)
3873 tbl 06
NOTES:
1. Allvaluesaremaximumguaranteedvalues.
2. All inputs switch between 0.2V (Low) and VDD–0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
3ns
1.5V
1.5V
See Figure 1 and 2
3873 tbl 07
3.3V
320Ω
350Ω
+1.5V
DATAOUT
50Ω
5pF*
I/O
Z0 = 50Ω
30pF
3873 drw 03
3873 drw 04
.
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
3
6.42
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V124SA10
71V124SA12
71V124SA15
71V124SA20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
10
12
15
20
____
____
____
____
t
Chip Select Access Time
10
12
15
20
(1)
CLZ
____
____
____
____
t
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
OutputDisable to Output in High-Z
Output Hold from Address Change
4
4
4
4
(1)
tCHZ
0
5
0
6
0
7
0
8
____
____
____
____
tOE
5
6
7
8
(1)
(1)
____
____
____
____
tOLZ
0
0
4
0
0
4
0
0
4
0
0
4
tOHZ
5
5
5
7
____
____
____
____
tOH
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
10
7
7
0
7
0
5
0
3
0
12
8
8
0
8
0
6
0
3
0
15
10
10
0
20
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
10
0
12
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Data Hold Time
7
9
t
0
0
(2)
OW
t
Output Active from End-of-Write
Write Enable to Output in High-Z
3
4
(2)
WHZ
t
5
5
0
5
0
8
ns
3873 tbl 08
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
4
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
t
RC
ADDRESS
OE
t
AA
tOE
(5)
t
OLZ
(5)
CS
(3)
tACS
(5)
OHZ
t
t
CLZ
(5)
CHZ
t
HIGH IMPEDANCE
.
DATAOUT
DATAOUT VALID
3873 drw 05
Timing Waveform of Read Cycle No. 2(1, 2, 4)
tRC
ADDRESS
tAA
t
OH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
DATAOUT
.
3873 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
5
6.42
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
t
AW
CS
(2)
tWR
tWP
t
AS
WE
(5)
(5)
t
CHZ
(5)
tOW
tWHZ
HIGH IMPEDANCE
(3)
(3)
DATAOUT
DATAIN
t
DW
tDH
.
DATAIN VALID
3873 drw 07
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC
ADDRESS
t
AW
CS
(3)
WR
t
tAS
tCW
WE
t
DW
tDH
DATAIN
DATAIN VALID
.
3873 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OELOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be
placedonthe bus forthe requiredtDW. IfOEis HIGHduringa WE controlledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCSLOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahighimpedancestate.CSmustbeactiveduringthetCW writeperiod.
5. Transitionismeasured±200mVfromsteadystate.
6
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
OrderingInformation
71V124
SA
XX
X
X
X
H
Process/
Temperature
Range
Device
Type
Power Speed
Package
Blank Commercial (0°C to +70°C)
I
Industrial (-40°C to +85°C)
G
Restricted hazardous substance device
TY
Y
PH
300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)
TSOP Type II (SO32-4)
10
12
15
20
.
Speed in nanoseconds
Blank
H
First generation or current die step
Current generation die step optional
3873 drw 09
7
6.42
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Center Power & Ground Pinout
Commercial and IndustrialTemperature Ranges
DatasheetDocumentHistory
11/22/99
Updatedtonewformat
Pg. 1–4, 7 AddedIndustrialTemperaturerangeofferings
Pg. 2
Pg. 6
Pg. 8
Pg. 3
Pg. 4
Pg. 7
Pg. 1,3,7
Pg. 7
Pg. 7
Pg.7
AddedRecommendedOperatingTemperatureandSupplyVoltagetable
RevisedfootnotesonWriteCycleNo. 1diagram
AddedDatasheetDocumentHistory
08/30/00
Tighten ICC and ISB
TightenACCharacteristicstOHZ,tOWandtWHZ
Removed footnote "400-mil SOJ package only offered in 10ns and 12ns speed grade"
AddedIndustrialtemperatureoffering10nsspeedgrade
Added"Restrictedhazardoussubstancedevice"toorderinginformation.
AddedHgenerationdiesteptodatasheetorderinginformation.
removed"IDT"formtheorderablepartnumber
08/22/01
11/30/03
01/30/04
2/14/07
10/13/08
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
相关型号：
©2020 ICPDF网 联系我们和版权申明