71V2546XS133PFG8 [IDT]
3.3V Synchronous ZBT SRAM;
| 型号： | 71V2546XS133PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V Synchronous ZBT SRAM 静态存储器 |
| 文件： | 总21页 (文件大小：733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V2546S/XS
128K x 36
3.3V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Pipelined Outputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread
or write.
Features
◆
128K x 36 memory configurations
◆
Supports high performance system speed - 150 MHz
The IDT71V2546 contains data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
(3.8 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
◆
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546tobe
suspended as long as necessary. All synchronous inputs are ignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Internally synchronized output buffer enable eliminates the
need to control OE
◆
Single R/W (READ/WRITE) control pin
◆
Positive clock-edge triggered address, data, and control
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis
initiated.
signal registers for fully pipelined applications
◆
4-word burst capability (interleaved or linear)
◆
Individual byte write (BW1 - BW4) control (May tie active)
◆
Three chip enables for simple depth expansion
◆
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
TheIDT71V2546hasanon-chipburstcounter.Intheburstmode,the
IDT71V2546 can provide four cycles of data for a single address
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
flatpack (TQFP) and 119 ball grid array (BGA)
Description
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, theyhavebeengiventhenameZBTTM, orZeroBusTurnaround.
TheIDT71V2546SRAMutilizeIDT's latesthigh-performanceCMOS
process and is packaged in a JEDEC standard 14mm x 20mm 100-pin
thinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA).
PinDescriptionSummary
A0-A16
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE , CE
1
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
ZZ
Synchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
Static
5294 tbl 01
APRIL 2011
1
©2011IntegratedDeviceTechnology,Inc.
DSC-5294/07
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A16
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled
high.
R/W
Read / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the
low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of
clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
BW
1
-BW
4
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW4) must be valid. The
byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW
tied low if always doing write to the entire 36-bit word.
1-BW4 can all be
Chip Enables
LOW Synchronous active low chip enable. CE
sampled high or CE sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
1
and CE
2
are used with CE
2
to enable the IDT71V2546. (CE
1
or CE
2
CE
1
, CE
2
2
CE
2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE is used with CE and CE to enable the chip. CE has inverted
2
1
2
2
polarity but otherwise identical to CE and CE2.
1
CLK
N/A
N/A
This is the clock input to the IDT71V2546. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31
Data Input/Output
Linear Burst Order
Output Enable
I/O
I
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
I/OP1-I/OP4
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
LBO
I
LOW Asynchronous output enable. OE must be low to read data from the IDT71V2546. When OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
OE
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V2546 to its
HIGH lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
ZZ
Sleep Mode
I
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
Ground.
V
V
5294 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
128Kx36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
D
Q
Q
Address
CE1, CE2, C E2
R/W
C EN
Control
ADV/LD
BW x
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
O E
5294 drw 01a
Data I/O [0:31],
I/O P[1:4]
RecommendedDCOperating
Conditions
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
3.3
Max.
Unit
V
V
DD
DDQ
SS
IH
IH
IL
3.465
2.625
0
V
2.5
V
V
0
V
____
V
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
1.7
V
DD +0.3
V
DDQ +0.3(2)
V
____
____
V
1.7
V
V
-0.3(1)
0.7
V
5294 tbl 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
6.42
3
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
V
DD
VDDQ
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
2.5V±5%
5294 tbl 05
NOTE:
1. TA is the "instant on" case temperature.
Pin Configuration — 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O22
I/O
I/O
9
8
I/O23
(1)
VDD
V
SS
(1)
V
DD
DD
V
V
V
DD
(1)
V
DD
(3)
SS/ZZ
VSS
I/O24
I/O25
I/O
I/O
7
6
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
1
0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
5294 drw 02
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.442
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100TQFPCapacitance(1)
AbsoluteMaximumRatings(1)
(TA = +25° C, f = 1.0MHz)
Commercial &
Symbol
Rating
Unit
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Industrial Values
Symbol
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
CIN
V
5
7
pF
CI/O
V
pF
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
V
V
5294 tbl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
VTERM
Terminal Voltage with
Respect to GND
119BGACapacitance(1)
Commercial
Operating Temperature
-0 to +70
oC
(TA = +25° C, f = 1.0MHz)
(7)
T
A
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Industrial
Operating Temperature
-40 to +85
oC
oC
CIN
V
7
7
pF
Temperature
Under Bias
-55 to +125
T
BIAS
CI/O
V
pF
5294 tbl 07a
Storage
-55 to +125
oC
TSTG
NOTE:
Temperature
1. This parameter is guaranteed by device characterization, but not production
tested.
P
T
Power Dissipation
DC Output Current
2.0
50
W
IOUT
mA
5294 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
6.42
5
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
ADV/LD
2
3
2
9
NC
CE
NC
NC
2
CE
7
A
DD
V
12
15
A
NC
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
V
19
I/O
12
I/O
DDQ
V
O E
20
21
11
10
I/O
I/O
I/O
NC(2)
I/O
G
H
J
2
BW
3
BW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
V
V
R/W
DDQ
DD
DD
V
DD
DDQ
V
DD(1)
DD(1)
V
V
V
24
26
SS
SS
6
7
I/O
I/O
I/O
V
CLK
NC
V
I/O
K
L
25
I/O
27
I/O
4
I/O
5
I/O
4
1
BW
BW
DDQ
28
SS
SS
3
DDQ
V
V
I/O
V
V
V
V
V
V
I/O
M
N
P
R
T
CEN
29
I/O
30
I/O
SS
SS
1
A
0
A
SS
SS
DD(1)
14
2
I/O
1
I/O
0
31
P4
I/O
P1
I/O
NC
NC
I/O
I/O
NC
,
5
DD
V
13
A
V
A
A
LBO
(3)
10
A
11
NC/ZZ
NC
NC
A
NC
NC
NC
NC
NC
DDQ
V
DDQ
V
U
5294 drw 13a
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.462
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
(6)
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
R/W
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5294 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
BW
X
L
1
BW
X
L
2
BW
X
L
3
BW
X
L
4
OPERATION
R/W
H
L
READ
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1
)
L
L
H
L
H
H
L
H
H
H
L
(2)
WRITE BYTE 2 (I/O[8:15], I/OP2
)
L
H
H
H
H
(2)
WRITE BYTE 3 (I/O[16:23], I/OP3
)
L
H
H
H
(2)
WRITE BYTE 4 (I/O[24:31], I/OP4
)
L
H
H
NO WRITE
L
H
5294 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
6.42
7
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
0
1
0
0
1
1
0
1
Fourth Address(1)
1
1
0
1
0
5294 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst SequenceTable (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5294 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A16)
(2)
CONTROL
(R/W , ADV/LD , BW x)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
,
5294 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.482
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
CE(1)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
n+2
A1
Q0
n+3
X
X
H
X
L
L
Q0+1 Deselect or STOP
n+4
L
Q1
NOOP
n+5
A2
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
n+6
X
X
X
H
L
n+7
Q2
n+8
A3
L
Q2+1 Load write
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
Deselect or STOP
NOOP
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
L
D3
X
X
X
X
L
H
X
L
X
X
L
D3+1
D4
A5
Z
Z
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
A6
H
L
L
X
L
A7
L
D5
X
X
H
X
L
X
L
L
Q6
A8
X
X
L
X
X
L
D7
X
X
L
D7+1
A9
Q8
5294 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
X
L
X
X
L
L
X
X
X
X
X
X
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
Q0
Contents of Address A0 Read Out
5294 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
9
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
Clock Setup Valid, Advance Counter
X
Q0
Address A0 Read Out, Inc. Count
X
Q
0+1
0+2
0+3
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
X
Q
A1
L
Q
Address A0+3 Read Out, Load A
Address A Read Out, Inc. Count
Address A Read Out, Inc. Count
Address A1+1 Read Out, Load A
1
X
X
H
H
L
X
Q0
0
X
Q1
1
A2
L
Q1+1
2
5294 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
L
X
X
L
X
X
L
L
L
L
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
D0
Write to Address A0
5294 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
L
X
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
A1
X
X
X
X
D0
Address A0 Write, Inc. Count
X
D
0+1
0+2
0+3
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
X
D
L
D
Address A0+3 Write, Load A
Address A Write, Inc. Count
Address A Write, Inc. Count
Address A1+1 Write, Load A
1
X
X
L
H
H
L
X
D0
0
X
D1
1
A2
L
D1+1
2
5294 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1402
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
H
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A1
Clock Valid
X
X
X
X
L
Q0
Clock Ignored. Data Q is on the bus.
0
Q0
Clock Ignored. Data Q0 is on the bus.
A2
Q0
Address A
Address A
Address A
0
Read out (bus trans.)
Read out (bus trans.)
2 Read out (bus trans.)
A3
L
Q1
1
A4
L
Q2
5294 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
H
L
H
H
L
L
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A1
X
X
X
X
L
Clock Ignored.
Clock Ignored.
A2
D0
Write Data D0
A3
L
D1
Write Data D
1
A4
L
D2
Write Data D2
5294 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
CE(2)
H
H
L
(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
A
0
Z
Z
Address and Control meet setup
Deselected or STOP.
X
H
L
A1
Q0
Address A
Deselected or STOP.
Address A Read out. Deselected.
0 Read out. Load A1.
X
X
H
H
L
X
L
Z
Q
Z
Z
1
1
A2
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
Q2
Address A2 Read out. Deselected.
5294 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
CE(2)
H
H
L
(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
A
0
Z
Z
Address and Control meet setup
Deselected or STOP.
X
X
L
H
L
X
L
A1
D0
Address D
Deselected or STOP.
Address D Write in. Deselected.
0 Write in. Load A1.
X
X
X
X
L
H
H
L
X
X
L
Z
D
Z
Z
1
1
A2
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
D2
Address D2 Write in. Deselected.
5294 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
6.1422
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 3.3V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
LBO, JTAG and ZZ Input Leakage Current
|ILI
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +6mA, VDD = Min.
OH = -6mA, VDD = Min.
30
5
µA
µA
V
|ILO
|
Output Leakage Current
V
VOL
Output Low Voltage
I
0.4
___
VOH
Output High Voltage
I
2.0
V
5294 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(1) (VDD = 3.3V±5%)
150MHz
133MHz
100MHz
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind'l
Com'l
Ind'l
Ind'l
I
DD
Device Selected, Outputs Open,
Operating Power
Supply Current
325
40
335
300
40
310
250
260
mA
ADV/LD = X, VDD = Max.,
(2)
VIN > VIH or < VIL, f = fMAX
ISB1
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
CMOS Standby Power
Supply Current
45
130
45
45
120
45
40
45
110
45
mA
mA
V
,
ISB2
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
Clock Running Power
Supply Current
120
40
110
40
100
40
V
,
(2.3)
f = fMAX
ISB3
Device Selected, Outputs Open,
Idle Power
Supply Current
mA
CEN > VIH, VDD = Max.,
(2,3)
VIN > VHD or < VLD, f = fMAX
5294 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
VDDQ/2
AC Test Loads
AC Test Conditions
(VDDQ = 2.5V)
50Ω
Input Pulse Levels
0 to 2.5V
2ns
I/O
Z0 = 50Ω
,
Input Rise/Fall Times
5294 drw 04
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
Figure 1. AC Test Load
6
5
4
See Figure 1
5294 tbl 23
3
2
1
∆tCD
(Ty pical ,
ns)
20 30 50
80 100
Capacit ance(pF )
200
5294 dr w05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
13
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
150MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
CYC
Clock Cycle Time
6.7
7.5
10
ns
MHz
ns
____
____
____
t (1)
F
Clock Frequence
150
133
100
____
____
____
(2)
CH
Clock High Pulse Width
Clock Low Pulse Width
2.0
2.0
2.2
2.2
3.2
3.2
t
____
____
____
(2)
CL
ns
t
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.8
4.2
5
ns
ns
ns
____
____
____
tCDC
1.5
1.5
1.5
1.5
1.5
1.5
____
____
____
(3,4,5)
CLZ
t
(3,4,5)
Clock High to Data High-Z
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
3.8
4.2
5
____
____
____
(3,4)
(3,4)
0
0
0
t
OLZ
____
____
____
3.8
4.2
5
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data In Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
5294 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.1442
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
15
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
6.1462
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
6.42
17
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
6.1482
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
19
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
O E
tOE
tOHZ
tOLZ
DATAOUT
Valid
5294 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
XX
XXXX
XX
XX
X
X
X
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Green
G
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
PF
BG
150
133
100
Clock Frequency in Megahertz
Standard Power
S
First generation or current die step
Current generation die step optional
Blank
X
128Kx36 Pipelined ZBT SRAM with 2.5V I/O
71V2546
5294 drw 12
6.2402
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
03/04/00
05/02/00
Createdpreliminarydatasheetfrom71V2556and71V2558datasheets. ChangedtCDC, tCLZ,
andtCHZminimumsfrom1.0nsto1.5ns.
Pg. 1,14,15,22
Add 150 MHz speed grade offering
Pg. 5,6
Pg. 5,6,7
Pg. 6
InsertclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxRatingstables
ClarifynoteonTQFPandBGApinconfigurations;correctedtypoinpinout
Add BGAcapacitancetable
Pg. 21
Pg. 23
Add 100 pin TQFP Package Diagram Outline
05/26/00
07/26/00
Add new package offering, 13 x 15mm 165 fBGA
Correct119BGAPackageDiagramOutline
Pg. 5-8
Pg. 8
Add ZZ, sleep mode reference note to BG119, PK100 and BQ165 pinouts
UpdateBQ165pinout
Pg. 23
UpdateBG119PackageDiagramOutlinedimensions
RemovePreliminarystatusfromdatasheet
10/25/00
Pg. 8
Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST
05/20/02
09/30/04
Pg. 1-8,15,22,23,27 AddedJTAG"SA"versionfunctionalityandupdatedZZpindescriptionsandnotes
Pg. 7
Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
02/23/07
05/27/10
04/11/11
Pg. 27
Pg. 24
Pg. 1-21
Pg. 13
Pg. 20
AddedXstepdiegenerationtodatasheetorderinginformation.
Added"Restrictedhazardoussubstancedevice"totheorderinginformation.
Removed71V2548(EOL), fBGA165pin, andJTAGinformation.
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CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
408-284-4532
800-345-7015or408-284-8200
fax:408-284-2775
www.idt.com
IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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