71V2548S133BGGI [IDT]
ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119;型号: | 71V2548S133BGGI |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119 静态存储器 |
文件: | 总25页 (文件大小:220K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT71V2546S/XS
IDT71V2548S/XS
IDT71V2546SA/XSA
IDT71V2548SA/XSA
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Features
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycles latertheassociateddatacycleoccurs,beitread
or write.
◆
128K x 36, 256K x 18 memory configurations
◆
Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
The IDT71V2546/48 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546/48to
besuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
◆
ZBTTM Feature - No dead cycles between write and read
cycles
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
◆
◆
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
Optional Boundary Scan JTAG Interface (IEEE1149.1
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis
initiated.
◆
◆
◆
◆
◆
complaint)
TheIDT71V2546/48hasanon-chipburstcounter.Intheburstmode,
theIDT71V2546/48canprovidefourcyclesofdataforasingleaddress
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and 165 fine pitch ball grid array (fBGA).
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
Description
TheIDT71V2546/48 are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles
when turning the bus around between reads and writes, or writes and
TM
reads. Thus, they have been given the name ZBT , or Zero Bus
Turnaround.
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE , CE
1
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
TMS
TDI
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
Synchronous
Synchronous
N/A
TCK
TDO
TRST
ZZ
Test Clock
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
Static
5294 tbl 01
MAY 2010
1
©2010IntegratedDeviceTechnology,Inc.
DSC-5294/06
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled
high.
R/W
Read / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the
low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of
clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
BW
1
-BW
4
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW4) must be valid. The
byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW
tied low if always doing write to the entire 36-bit word.
1-BW4 can all be
Chip Enables
LOW Synchronous active low chip enable. CE
CE sampled high or CE sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
1
and CE
2
are used with CE
2
to enable the IDT71V2546/48. (CE
1 or
CE
1
, CE
2
2
2
CE
2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE is used with CE and CE to enable the chip. CE has inverted
2
1
2
2
polarity but otherwise identical to CE and CE2.
1
CLK
N/A
N/A
This is the clock input to the IDT71V2546/48. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31
Data Input/Output
Linear Burst Order
Output Enable
I/O
I
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
I/OP1-I/OP4
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
LBO
I
LOW Asynchronous output enable. OE must be low to read data from the 71V2546/48. When OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
OE
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test Data Output
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
JTAG Reset
(Optional)
I
I
LOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
TRST
be left floating. This pin has an internal pullup.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V2546/2548 to
HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
Ground.
V
V
5294 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.42
2
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
128Kx36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
D
Q
Address
CE1, CE2, CE2
R/W
CEN
Q
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
,
5294 drw 01a
Data I/O [0:31],
I/O P[1:4]
TMS
TDI
TCK
JTAG
(SA Version)
TDO
TRST
(optional)
6.42
3
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
256x18 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
Q
Q
Address
CE1, CE2, CE2
R/W
D
Control
CEN
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5294 drw 01b
Data I/O [0:15],
I/O P[1:2]
TMS
TDI
TCK
JTAG
(SA Version)
TDO
TRST
(optional)
RecommendedDCOperating
Conditions
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
0
Unit
V
V
DD
DDQ
SS
IH
IH
IL
3.3
V
2.5
V
V
0
V
____
V
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
1.7
VDD +0.3
V
DDQ +0.3(2)
V
____
____
V
1.7
V
V
-0.3(1)
0.7
V
5294 tbl 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
6.42
4
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
V
DD
VDDQ
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
2.5V±5%
5294 tbl 05
NOTE:
1. TA is the "instant on" case temperature.
Pin Configuration — 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O22
I/O
I/O
9
8
I/O23
(1)
VDD
V
SS
(1)
V
DD
DD
V
V
V
DD
(1)
V
DD
(3)
SS/ZZ
VSS
I/O24
I/O25
I/O
I/O
7
6
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
1
0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
5294 drw 02
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.42
5
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 256K x 18
AbsoluteMaximumRatings(1)
Commercial &
Symbol
Rating
Unit
Industrial Values
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
DDQ
A
NC
NC
10
2
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
V
V
3
4
V
VDDQ
5
VSS
76
75
74
73
VSS
6
NC
NC
NC
I/OP1
I/O
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
7
8
I/O8
7
9
I/O9
72
71
70
I/O
6
V
TERM
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Terminal Voltage with
Respect to GND
V
DDQ
SS
VSS
V
VDDQ
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O10
I/O11
I/O
I/O
5
4
Commercial
Operating Temperature
(1)
oC
V
DD
VSS
-0 to +70
(1)
VDD
V
V
V
DD
(1)
(7)
V
DD
DD
TA
(3)
SS/ZZ
VSS
Industrial
Operating Temperature
I/O12
I/O13
I/O
I/O
3
2
-40 to +85
oC
oC
V
DDQ
V
V
DDQ
SS
VSS
Temperature
Under Bias
-55 to +125
TBIAS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
Storage
Temperature
-55 to +125
oC
TSTG
VSS
VSS
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
,
P
T
Power Dissipation
DC Output Current
2.0
50
W
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IOUT
mA
5294 drw 02a
5294 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
Top View
100TQFP
NOTES:
3. VDDQ terminals only.
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long
as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
100TQFPCapacitance(1)
(TA = +25° C, f = 1.0MHz)
119BGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
165fBGACapacitance(1)
5294 tbl 07a
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
TBD pF
CI/O
V
TBD pF
5294 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
NC(2)
ADV/LD
A
A
A
2
3
2
9
NC
CE
NC
NC
2
CE
7
A
DD
V
12
15
A
NC
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
V
19
I/O
12
I/O
DDQ
V
OE
20
21
11
10
I/O
G
H
J
I/O
I/O
NC(2)
I/O
2
BW
3
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
V
R/W
DDQ
V
DD
DD
V
DD
DDQ
V
DD(1)
SS
DD(1)
V
V
V
24
I/O
26
I/O
SS
6
I/O
7
I/O
K
L
V
CLK
NC
V
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
1
BW
DDQ
V
28
SS
V
SS
SS
SS
3
DDQ
1
M
N
P
R
T
I/O
V
V
V
I/O
V
CEN
29
I/O
30
I/O
SS
V
1
A
2
I/O
I/O
0
I/O
31
I/O
P4
I/O
SS
V
0
A
P1
I/O
,
5
DD
VDD(1)
13
NC
NC
A
V
A
A
LBO
NC
(5)
10
A
11
14
A
NC/ZZ
NC
NC
(3)
(3)
(3)
(3)
(3,4)
DDQ
V
DDQ
V
NC/TMS
NC/TDI
NC/TCK
U
NC/TDO
NC/TRST
5294 drw 13a
Top View
Pin Configuration — 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
NC(2)
ADV/LD
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
7
I/O
NC
DDQ
1
CE
NC
6
I/O
DDQ
V
V
NC
OE
10
5
I/O
G
H
J
NC
I/O
NC
NC(2)
NC
BW
2
11
I/O
SS
V
SS
4
I/O
V
NC
R/W
DD(1)
DD(1)
DDQ
V
DD
12
DD
V
DD
V
DDQ
V
V
V
V
SS
SS
3
I/O
K
L
NC
I/O
V
CLK
NC
V
NC
13
I/O
SS
SS
2
I/O
NC
V
NC
1
BW
DDQ
V
14
SS
SS
SS
DDQ
V
M
N
P
R
T
I/O
NC
V
V
V
V
V
V
NC
CEN
15
SS
SS
1
A
1
I/O
I/O
NC
NC
NC
NC
P2
I/O
0
A
0
I/O
NC
5
A
DD
V
12
A
NC
V
DD(1)
LBO
(5)
10
15
A
14
11
A
A
NC
A
NC/ZZ
(3)
(3)
(3)
(3)
(3,4)
DDQ
V
DDQ
V
5294 drw 13b
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
NC/TRST
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
7
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(2)
(2)
A
B
C
D
E
F
NC
A
7
ADV/LD
OE
NC
A
8
NC
CE1
BW
BW
3
4
BW
2
CE
2
CEN
R/W
(2)
(2)
NC
A6
CE2
CLK
NC
A9
NC
BW
1
I/OP3
I/O17
I/O19
I/O21
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
10
11
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/OP2
I/O14
I/O12
I/O10
I/O16
I/O18
I/O20
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
I/O23
I/O22
V
V
V
V
V
V
V
I/O
NC
I/O
I/O
I/O
I/O
NC
9
I/O8
(1)
(1)
(5)
V
DD
VDD
NC
V
V
V
V
V
NC
NC/ZZ
I/O
I/O
I/O
I/O
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
13
12
7
6
K
L
M
N
P
V
V
V
V
V
V
V
5
4
V
V
V
V
V
V
V
3
2
V
V
V
V
V
V
V
1
0
(1)
V
V
NC/TRST(3,4)
NC
V
DD
V
V
I/OP1
NC
(2)
(3)
(3)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A14
(2)
(3)
R
NC
A4
A3
NC/TMS(3)
A0
NC/TCK
A
A
A15
A16
LBO
5294 tbl 25
Pin Configuration - 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(2)
(2)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
7
NC
ADV/LD
NC
A
8
A10
CE
1
BW
2
CE
2
CEN
R/W
(2)
(2)
A6
CE2
NC
CLK
NC
A9
NC
BW
1
OE
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
11
12
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/OP1
I/O
8
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
7
I/O
9
V
V
V
V
V
V
V
6
I/O10
V
V
V
V
V
V
V
5
G
H
J
I/O11
V
V
V
V
V
V
V
4
(1)
(1)
(5)
V
DD
VDD
NC
V
V
V
V
V
NC
NC/ZZ
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
NC
NC
NC
NC
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
14
13
I/O
I/O
I/O
I/O
NC
3
NC
K
L
M
N
P
V
V
V
V
V
V
V
2
NC
V
V
V
V
V
V
V
1
NC
V
V
V
V
V
V
V
0
NC
(1)
V
V
NC/TRST(3,4)
NC
V
DD
V
V
NC
(2)
(3)
(3)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A15
NC
(2)
(3)
R
NC
A4
A3
NC/TMS(3)
A0
NC/TCK
A
A
A16
A17
LBO
5294 tbl 25a
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 supports ZZ (sleep mode) on the latest die revision.
6.42
8
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
R/W
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5294 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
BW
X
L
1
BW
X
L
2
BW
3
BW4
OPERATION
R/W
H
L
READ
X
X
WRITE ALL BYTES
L
H
H
L
L
H
H
H
L
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1
)
L
L
H
L
(2)
WRITE BYTE 2 (I/O[8:15], I/OP2
)
L
H
H
H
H
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3
)
L
H
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4
)
L
H
H
NO WRITE
L
H
5294 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
0
1
0
0
1
1
0
1
Fourth Address(1)
1
1
0
1
0
5294 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5294 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A16)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
,
5294 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
10
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showint Mixed Load, Burst,
DeselectandNOOPCycles(2)
CE(1)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
n+2
A1
Q0
n+3
X
X
H
X
L
L
Q0+1 Deselect or STOP
n+4
L
Q1
NOOP
n+5
A2
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
n+6
X
X
X
H
L
n+7
Q2
n+8
A3
L
Q2+1 Load write
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
Deselect or STOP
NOOP
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
L
D3
X
X
X
X
L
H
X
L
X
X
L
D3+1
D4
A5
Z
Z
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
A6
H
L
L
X
L
A7
L
D5
X
X
H
X
L
X
L
L
Q6
A8
X
X
L
X
X
L
D7
X
X
L
D7+1
A9
Q8
5294 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
X
L
X
X
L
L
X
X
X
X
X
X
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
Q0
Contents of Address A0 Read Out
5294 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
Clock Setup Valid, Advance Counter
X
Q0
Address A0 Read Out, Inc. Count
X
Q
0+1
0+2
0+3
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
X
Q
A1
L
Q
Address A0+3 Read Out, Load A
Address A Read Out, Inc. Count
Address A Read Out, Inc. Count
Address A1+1 Read Out, Load A
1
X
X
H
H
L
X
Q0
0
X
Q1
1
A2
L
Q1+1
2
5294 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
L
X
X
L
X
X
L
L
L
L
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
D0
Write to Address A0
5294 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
L
X
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
A1
X
X
X
X
D0
Address A0 Write, Inc. Count
X
D
0+1
0+2
0+3
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
X
D
L
D
Address A0+3 Write, Load A
Address A Write, Inc. Count
Address A Write, Inc. Count
Address A1+1 Write, Load A
1
X
X
L
H
H
L
X
D0
0
X
D1
1
A2
L
D1+1
2
5294 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
12
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A1
Clock Valid
X
X
X
X
L
Q0
Clock Ignored. Data Q is on the bus.
0
Q0
Clock Ignored. Data Q0 is on the bus.
A2
Q0
Address A
Address A
Address A
0
Read out (bus trans.)
Read out (bus trans.)
2 Read out (bus trans.)
A3
L
Q1
1
A4
L
Q2
5294 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2)
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
H
L
H
H
L
L
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A1
X
X
X
X
L
Clock Ignored.
Clock Ignored.
A2
D0
Write Data D0
A3
L
D1
Write Data D
1
A4
L
D2
Write Data D2
5294 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
CE(2)
H
H
L
(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
A
0
Z
Z
Address and Control meet setup
Deselected or STOP.
X
H
L
A1
Q0
Address A
Deselected or STOP.
Address A Read out. Deselected.
0 Read out. Load A1.
X
X
H
H
L
X
L
Z
Q
Z
Z
1
1
A2
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
Q2
Address A2 Read out. Deselected.
5294 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
CE(2)
H
H
L
(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
A
0
Z
Z
Address and Control meet setup
Deselected or STOP.
X
X
L
H
L
X
L
A1
D0
Address D
Deselected or STOP.
Address D Write in. Deselected.
0 Write in. Load A1.
X
X
X
X
L
H
H
L
X
X
L
Z
D
Z
Z
1
1
A2
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
D2
Address D2 Write in. Deselected.
5294 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
14
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 3.3V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
LBO, JTAG and ZZ Input Leakage Current
|ILI
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +6mA, VDD = Min.
OH = -6mA, VDD = Min.
30
5
µA
µA
V
|ILO
|
Output Leakage Current
V
VOL
Output Low Voltage
I
0.4
___
VOH
Output High Voltage
I
2.0
V
5294 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(1) (VDD = 3.3V±5%)
150MHz
133MHz
Com'l
100MHz
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l Only
Ind
Ind
I
DD
Device Selected, Outputs Open,
Operating Power
Supply Current
325
40
300
40
310
250
260
mA
ADV/LD = X, VDD = Max.,
(2)
VIN > VIH or < VIL, f = fMAX
ISB1
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
CMOS Standby Power
Supply Current
45
120
45
40
45
110
45
mA
mA
V
,
ISB2
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
Clock Running Power
Supply Current
120
40
110
40
100
40
V
,
(2.3)
f = fMAX
ISB3
Device Selected, Outputs Open,
Idle Power
Supply Current
mA
CEN > VIH, VDD = Max.,
(2,3)
VIN > VHD or < VLD, f = fMAX
5294 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
VDDQ/2
AC Test Loads
AC Test Conditions
50Ω
(VDDQ = 2.5V)
I/O
Z0 = 50Ω
,
Input Pulse Levels
0 to 2.5V
2ns
5294 drw 04
Input Rise/Fall Times
Figure 1. AC Test Load
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
6
5
4
See Figure 1
5294 tbl 23
3
2
1
ΔtCD
(Ty pical ,
ns)
20 30 50
80 100
Capacit ance(pF )
200
5294 dr w 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
150MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
CYC
Clock Cycle Time
6.7
7.5
10
ns
MHz
ns
____
____
____
t (1)
F
Clock Frequence
150
133
100
____
____
____
(2)
CH
Clock High Pulse Width
Clock Low Pulse Width
2.0
2.0
2.2
2.2
3.2
3.2
t
____
____
____
(2)
CL
ns
t
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.8
4.2
5
ns
ns
ns
____
____
____
tCDC
1.5
1.5
1.5
1.5
1.5
1.5
____
____
____
(3,4,5)
CLZ
t
(3,4,5)
Clock High to Data High-Z
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
3.8
4.2
5
____
____
____
(3,4)
(3,4)
0
0
0
t
OLZ
____
____
____
3.8
4.2
5
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data In Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
5294 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.42
16
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
17
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
,
6.42
18
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
,
6.42
19
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
6.42
20
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
21
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
t
5(1)
ns
____
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
t
5(1)
ns
____
Note (1)
____
t
50
ns
I5294 tbl 03
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I5294 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
22
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Revision Number (31:28)
Value
Description
0x2
0x210, 0x212
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71V2546SA and 71V2548SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I5294 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5294 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
23
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
NOTE:
5294 drw 11
1. A read operation is assumed to be in progress.
OrderingInformation
XXXX
XX
XX
XX
X
X
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Restricted hazardous substance device
G
PF**
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
150*
133
100
Clock Frequency in Megahertz
,
Standard Power
Standard Power with JTAG Interface
S
SA
Blank
X
First generation or current die step
Current generation die step optional
128Kx36 Pipelined ZBT SRAM with 2.5V I/O
IDT71V2546
IDT71V2548 256Kx18 Pipelined ZBT SRAM with 2.5V I/O
5294 drw 12
*Available in commercial range only
** JTAG (SA version) is not available with 100-pin TQFP package
6.42
24
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
03/04/00
05/02/00
Createdpreliminarydatasheetfrom71V2556and71V2558datasheets.ChangedtCDC,t
tCLZ, andtCHZ minimumsfrom1.0nsto1.5ns.
Add 150 MHz speed grade offering
Pg. 1,14,
15,22
Pg. 5,6
InsertclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxRatings
tables
Pg. 5,6,7
Pg. 6
ClarifynoteonTQFPandBGApinconfigurations;correctedtypoinpinout
Add BGAcapacitancetable
Pg. 21
Add100pinTQFPPackage DiagramOutline
05/26/00
07/26/00
Addnewpackage offering, 13x15mm165fBGA
Correct119BGAPackageDiagramOutline
AddZZ, sleepmode refernce note toBG119, PK100andBQ165pinouts
UpdateBQ165pinout
Pg. 23
Pg. 5-8
Pg. 8
Pg. 23
UpdateBG119PackageDiagramOutlinedimensions
RemovePreliminarystatusfromdatasheet
10/25/00
05/20/02
09/30/04
Pg. 8
Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST
Pg. 1-8,15,22,23, AddedJTAG"SA"versionfunctionalityandupdatedZZpindescriptions andnotes
27
Pg. 7
Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
02/23/07
05/27/10
Pg. 27
Pg. 24
AddedXstepdiegenerationtodatasheetorderinginformation.
Added"Restrictedhazardoussubstancedevice"totheorderinginformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
800-345-7015 or
408/284-4555
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
6.42
25
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