71V2558XSA133BQGI8 [IDT]
ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA165;
| 型号： | 71V2558XSA133BQGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA165 静态存储器 |
| 文件： | 总28页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 36, 256K x 18
IDT71V2556S/XS
IDT71V2558S/XS
IDT71V2556SA/XSA
IDT71V2558SA/XSA
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Features
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread
or write.
The IDT71V2556/58 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
AClockEnable(CEN)pinallowsoperationoftheIDT71V2556/58to
besuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis
initiated.
TheIDT71V2556/58hasanon-chipburstcounter.Intheburstmode,
theIDT71V2556/58canprovidefourcyclesofdataforasingleaddress
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LDsignal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
◆
128K x 36, 256K x 18 memory configurations
◆
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
◆
◆
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
◆
◆
◆
◆
◆
complaint)
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
TheIDT71V2556/58 are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles
when turning the bus around between reads and writes, or writes and
TM
reads. Thus, they have been given the name ZBT , or Zero Bus
Turnaround.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1
, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
Test Clock
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
Static
4875 tbl 01
MAY 2010
1
©2010IntegratedDeviceTechnology,Inc.
DSC-4875/11
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the
chip deselected, any burstin progress is terminated. When ADV/LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored
when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place two clock
cycles later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load
BW
1
-BW
4
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the
device two cycles later. BW -BW can all be tied low if always doing write to the entire 36-bit word.
1-BW4)
1
4
Chip Enables
LOW Synchronous active low chip enable. CE and CE are used with CE to enable the IDT71V2556/58.
1
2
2
CE1
, CE
2
(CE
1
or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a
deselect cycle. The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles
after deselect is initiated.
CE
2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE
2
is used with CE
1
and CE2 to enable the chip. CE2 has
inverted polarity but otherwise identical to CE
1
and CE
2.
CLK
N/A
N/A
This is the clock input to the IDT71V2556/58. Except for OE, all timing references for the device are
made with respect to the rising edge of CLK.
I/O0-I/O31
Data Input/Output
Linear Burst Order
I/O
I
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
I/OP1-I/OP4
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO
is low the Linear burst sequence is selected. LBO is a static input and it must not change during
device operation.
LBO
Output Enable
I
LOW Asynchronous output enable. OE must be low to read data from the 71V2556/58. When OE is high the
I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write
cycles. In normal operation, OE can be tied low.
OE
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal
pullup.
TMS
TDI
Test Mode Select
Test Data Input
Test Clock
I
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has
an internal pullup.
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
I
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of
the TAP controller.
Test Data Output
O
N/A
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
LOW reset occurs automatically at power up and also resets using TMS and TCK p er IEEE 1149.1. If not
used TRST can be left floating. This pin has an internal pullup.
JTAG Reset
(Optional)
I
I
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
HIGH IDT71V2556/2558 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
This pin has an internal pulldown
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
Ground.
V
V
4875 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
128Kx36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
,
4875 drw 01a
TMS
TDI
TCK
Data I/O [0:31],
I/O P[1:4]
JTAG
(SA Version)
TDO
TRST
(optional)
6.42
3
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
256x18 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
4875 drw 01b
TMS
TDI
TCK
Data I/O [0:15],
I/O P[1:2]
JTAG
(SA Version)
TDO
TRST
(optional)
RecommendedDCOperating
Conditions
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
0
Unit
V
V
DD
DDQ
SS
IH
IH
IL
3.3
V
2.5
V
V
0
V
____
V
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
1.7
V
DD +0.3
V
(2)
____
____
V
1.7
VDDQ +0.3
V
V
-0.3(1)
0.7
V
4875 tbl 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
6.442
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
V
DD
VDDQ
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
2.5V±5%
4875 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
Pin Configuration — 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
V
DDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
V
V
SS
VDDQ
DDQ
69
68
67
66
65
64
I/O22
I/O9
I/O8
I/O23
(1)
VDD
V
VDD
SS
(1)
V
DD
DD
(1)
V
VDD
(3)
VSS
VSS/ZZ
63
62
I/O24
I/O25
I/O7
I/O6
61
60
59
VDDQ
VDDQ
VSS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
58
57
56
55
4
3
2
VSS
V
V
SS
54
53
VDDQ
DDQ
I/O30
I/O31
I/OP4
I/O
I/O
I/OP1
1
52
51
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
4875 drw 02
Top View
TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.42
5
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 256K x 18
AbsoluteMaximumRatings(1)
Commercial &
Symbol
Rating
Unit
Industrial Values
(2)
V
TERM
Te rm inal Vo ltag e with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
NC
DDQ
A
NC
NC
10
(3,6)
(4,6)
(5,6)
V
TERM
2
Te rm inal Vo ltag e with
Respect to GND
-0.5 to VDD
V
V
V
79
78
77
3
4
V
VDDQ
5
V
SS
76
75
74
73
V
SS
VTERM
Te rm inal Vo ltag e with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
6
NC
NC
I/O8
NC
I/OP1
I/O
I/O
7
8
7
9
I/O9
72
71
6
VTERM
Te rm inal Vo ltag e with
Respect to GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
VSS
70
V
DDQ
VDDQ
69
68
67
66
65
64
I/O10
I/O
I/O
5
Commerical
Operating Temperature
I/O11
4
-0 to +70
oC
(1)
V
DD
VSS
(1)
V
DD
DD
V
V
V
DD
T (7)
A
(1)
V
DD
(3)
SS/ZZ
Industrial
Operating Temperature
-40 to +85
oC
oC
V
SS
63
62
61
60
59
58
57
56
55
54
53
I/O12
I/O13
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
TBIAS
Temperature
Under Bias
-55 to +125
V
SS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
Storage
-55 to +125
oC
TSTG
Temperature
V
SS
VSS
V
DDQ
NC
NC
NC
VDDQ
P
T
Power Dissipation
DC Output Current
2.0
50
W
NC
NC
NC
,
52
51
IOUT
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4875 tbl 06
4875 drw 02a
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
Top View
TQFP
NOTES:
3. VDDQ terminals only.
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long
as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
100TQFPCapacitance(1)
(TA = +25° C, f = 1.0MHz)
119 BGA Capacitance(1)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
(TA = +25° C, f = 1.0MHz)
CIN
V
5
7
pF
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CI/O
V
pF
CIN
V
7
7
pF
4875 tbl 07
165 fBGA Capacitance(1)
CI/O
V
pF
(TA = +25° C, f = 1.0MHz)
4875 tbl 07a
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
Max. Unit
CIN
V
TBD pF
CI/O
VOUT = 3dV
TBD pF
4875 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.462
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
ADV/LD
2
3
2
9
NC
NC
CE
NC
NC
2
CE
7
A
DD
V
12
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
NC(2)
I/O
2
BW
3
BW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
V
V
V
V
R/W
DDQ
24
DD
DD
V
DD
DDQ
V
DD(1)
SS
DD(1)
SS
V
V
26
I/O
6
I/O
7
I/O
K
L
I/O
CLK
NC
25
I/O
27
28
4
I/O
5
I/O
I/O
4
BW
BW1
DDQ
29
SS
V
SS
SS
SS
3
I/O
DDQ
1
M
N
P
R
T
I/O
I/O
I/O
V
V
V
V
CEN
30
SS
V
1
A
2
I/O
I/O
I/O
I/O
31
I/O
P4
SS
0
A
0
V
I/OP1
,
5
A
DD
11
VDD(1)
13
A
NC
NC
DDQ
V
NC
LBO
(5)
10
A
14
NC
A
A
NC
NC/ZZ
(3)
(3)
(3)
(3)
(3,4)
DDQ
V
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
V
NC/TRST
4875 drw 13a
Top View
Pin Configuration — 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
ADV/LD
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
7
DD
V
13
17
A
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
7
I/O
NC
1
CE
NC
DDQ
6
I/O
DDQ
5
V
NC
V
OE
10
I/O
G
H
J
NC
I/O
NC
I/O
NC(2)
BW
2
11
SS
SS
4
I/O
NC
V
V
V
V
V
V
NC
DDQ
R/W
DD(1)
SS
DD(1)
SS
DDQ
DD
12
DD
V
DD
V
V
V
V
3
I/O
K
L
NC
I/O
I/O
CLK
NC
NC
13
SS
2
NC
V
I/O
NC
NC
BW
1
DDQ
14
I/O
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
V
V
V
V
V
V
CEN
15
I/O
SS
SS
1
A
1
NC
I/O
NC
NC
P2
I/O
0
A
0
I/O
NC
NC
NC
DDQ
,
5
DD
V
12
A
A
V
DD(1)
NC
LBO
(5)
10
15
A
14
11
A
A
NC
A
NC/ZZ
DDQ
(3)
(3)
(3)
(3)
(3,4)
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
V
NC/TRST
V
4875 drw 13b
TopView
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
7
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
ADV/LD
OE
9
10
11
(2)
(2)
A
B
C
D
E
F
NC
A7
NC
A8
NC
CE1
BW
3
BW
2
CE
2
CEN
R/W
(2)
(2)
NC
A6
CE
2
CLK
NC
A9
NC
BW
4
BW
1
I/OP3
I/O17
I/O19
I/O21
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
10
11
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/OP2
I/O14
I/O12
I/O10
I/O16
I/O18
I/O20
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
I/O23
I/O22
V
V
V
V
V
V
V
I/O
NC
I/O
I/O
I/O
9
I/O8
(1)
(1)
(5)
V
DD
V
DD
NC
V
V
V
V
V
NC
NC/ZZ
I/O
I/O
I/O
I/O
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
13
12
7
6
K
L
M
N
P
V
V
V
V
V
V
V
5
4
V
V
V
V
V
V
V
3
2
V
V
V
V
V
V
V
I/O1
0
(3,4)
(3)
(1)
NC/TRST
V
V
NC
VDD
V
V
NC
I/OP1
NC
(2)
(3)
NC
A
5
A
2
NC/TDI
A
1
NC/TDO
A
A
A14
(2)
(3)
R
NC
A
4
A
3
NC/TMS(3)
A
0
NC/TCK
A
A
A15
A16
LBO
4875 tbl 25
Pin Configuration — 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(2)
(2)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
7
NC
ADV/LD
NC
A
8
A10
CE
1
BW
2
CE
2
CEN
R/W
(2)
(2)
A6
CE2
NC
CLK
NC
A9
NC
BW1
OE
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
11
12
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/OP1
I/O
8
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
7
I/O
9
V
V
V
V
V
V
V
6
I/O10
V
V
V
V
V
V
V
5
G
H
J
I/O11
VDDQ
V
V
V
V
V
V
4
(1)
(1)
(5)
V
DD
VDD
NC
V
V
V
V
V
NC
NC/ZZ
NC
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
NC
NC
NC
NC
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
14
13
I/O
I/O
I/O
3
K
L
M
N
P
V
V
V
V
V
V
V
2
NC
V
V
V
V
V
V
V
1
NC
V
V
V
V
V
V
V
I/O
0
NC
(3,4)
(3)
(1)
NC/TRST
V
V
NC
V
DD
V
V
NC
NC
(2)
(3)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A15
NC
(2)
(3)
R
NC
A4
A3
NC/TMS(3)
A0
NC/TCK
A
A
A16
A17
LBO
4875 tbl 25a
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 supports ZZ (sleep mode) on the latest die revision.
6.482
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
R/W
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D
(7)
Q
(7)
Valid
LOADWRITE /
BURST WRITE
BURST WRITE
D
(Advance burst counter)(2)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(Advance burst counter)(2)
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
NOOP
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
4875 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
BW
1
BW
X
L
2
BW
3
BW4
OPERATION
R/W
H
L
READ
X
L
X
X
L
WRITE ALL BYTES
L
H
H
L
(2)
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1
)
L
L
H
L
H
H
H
L
WRITE BYTE 2 (I/O[8:15], I/OP2
)
L
H
H
H
H
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3
)
L
H
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4
)
L
H
H
NO WRITE
L
H
4875 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
4875 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
4875 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A16)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
,
4875 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.1402
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showint Mixed Load, Burst,
DeselectandNOOPCycles(2)
(1)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
n+2
A
X
X
1
Q0
n+3
H
X
L
L
Q0+1 Deselect or STOP
n+4
L
Q1
NOOP
n+5
A2
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
n+6
X
X
X
H
L
n+7
Q2
n+8
A3
L
Q2+1 Load write
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
L
D3
X
X
X
X
L
H
X
L
X
X
L
D3+1 Deselect or STOP
D4
NOOP
A5
Z
Z
Load write
Load read
Load write
Burst write
Load read
A6
H
L
L
X
L
A7
L
D5
X
X
H
X
L
X
L
L
Q6
A8
X
X
L
X
X
L
D7
X
X
L
D7+1 Burst read
A9
Q8
Load write
4875 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
X
L
X
X
L
L
L
X
X
X
X
X
X
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
Q0
Contents of Address A0 Read Out
4875 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
X
Address and Control meet setup
Clock Setup Valid, Advance Counter
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
X
X
X
L
Q0
Address A0 Read Out, Inc. Count
Q
0+1
0+2
0+3
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
Q
A
X
X
1
Q
Address A0+3 Read Out, Load A
Address A Read Out, Inc. Count
Address A Read Out, Inc. Count
1
H
H
L
X
X
L
Q0
0
Q1
1
A2
Q1+1
Address A1+1 Read Out, Load A2
4875 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
X
L
X
X
L
L
L
L
L
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
D0
Write to Address A0
4875 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
CE
n
A
0
L
X
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
A1
X
X
X
X
X
X
L
X
D0
Address A0 Write, Inc. Count
D
0+1
0+2
0+3
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
D
D
Address A0+3 Write, Load A
Address A Write, Inc. Count
Address A Write, Inc. Count
1
X
X
L
H
H
L
X
X
L
D0
0
D1
1
A2
D1+1
Address A1+1 Write, Load A2
4875 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1422
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A
X
X
1
Clock Valid
X
X
L
Q0
Clock Ignored. Data Q is on the bus.
0
Q0
Clock Ignored. Data Q0 is on the bus.
A2
Q0
Address A
Address A
Address A
0
Read out (bus trans.)
Read out (bus trans.)
2 Read out (bus trans.)
A3
L
Q1
1
A4
L
Q2
4875 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A
X
X
1
X
X
L
Clock Ignored.
Clock Ignored.
A2
D0
Write Data D0
A3
L
D1
Write Data D
1
A4
L
D2
Write Data D2
4875 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(2)
(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
H
L
?
Deselected.
A0
Z
Z
Address and Control meet setup
Deselected or STOP.
X
H
L
A
X
X
1
Q0
Address A
Deselected or STOP.
Address A Read out. Deselected.
0 Read out. Load A1.
H
H
L
X
L
Z
Q
Z
Z
1
1
A2
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
Q2
Address A2 Read out. Deselected.
4875 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
(2)
(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
?
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
H
L
A0
Z
Z
Address and Control meet setup
Deselected or STOP.
X
X
L
H
L
X
L
A
X
X
1
D0
Address D
Deselected or STOP.
Address D Write in. Deselected.
0 Write in. Load A1.
X
X
L
H
H
L
X
X
L
Z
D
Z
Z
1
1
A2
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
D2
Address D2 Write in. Deselected.
4875 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1442
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 3.3V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
LBO, JTAG and ZZ Input Leakage Current
|ILI
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +6mA, VDD = Min.
OH = -6mA, VDD = Min.
30
5
µA
µA
V
|ILO
|
Output Leakage Current
V
VOL
Output Low Voltage
I
0.4
___
VOH
Output High Voltage
I
2.0
V
4875 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(1) (VDD = 3.3V±5%)
200MHz
166MHz
133MHz
100MHz
Unit
Symbol
Parameter
Test Conditions
Com'l Only Com'l
Ind
Com'l
Ind
Com'l
Ind
I
DD
Device Selected, Outputs Open,
Operating Power
Supply Current
400
40
350
40
360
300
40
310
250
40
260
mA
ADV/LD = X, VDD = Max.,
(2)
VIN > VIH or < VIL, f = fMAX
ISB1
Device Deselected, Outputs
Open, VDD = Max., VIN > VHD or
< VLD, f = 0(2,3)
CMOS Standby
Power Supply Current
45
45
45
mA
mA
Device Deselected, Outputs
Open, VDD = Max., VIN > VHD or
ISB2
Clock Running Power
Supply Current
130
40
120
40
130
45
110
40
120
45
100
40
110
45
< VLD
,
(2.3)
f = fMAX
ISB3
Device Selected, Outputs Open,
Idle Power
Supply Current
mA
CEN > VIH, VDD = Max.,
(2,3)
VIN > VHD or < VLD, f = fMAX
4875 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ/2
AC Test Loads
AC Test Conditions
(VDDQ = 2.5V)
50Ω
Input Pulse Levels
0 to 2.5V
2ns
I/O
Z0
= 50Ω
,
Input Rise/Fall Times
4875 drw 04
6
5
4
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
Figure 1. AC Test Load
See Figure 1
4875 tbl 23
3
ΔtCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
4875 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
200MHz
166MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
CY C
Clock Cycle Time
5
6
7.5
10
ns
MHz
ns
____
____
____
____
t (1)
F
Clock Frequence
200
166
133
100
____
____
____
____
(2)
CH
Clock High Pulse Width
Clock Low Pulse Width
1.8
1.8
1.8
1.8
2.2
2.2
3.2
3.2
t
____
____
____
____
(2)
CL
ns
t
Output Parameters
____
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.2
3.5
4.2
5
ns
ns
ns
____
____
____
____
tCDC
1
1
1
1
1
1
1
1
____
____
____
____
(3,4,5)
CLZ
t
(3, 4,5)
Clock High to Data High-Z
1
3
1
3
1
3
1
3
ns
ns
ns
t
CHZ
____
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Data Active
3.2
3.5
4.2
5
(3,4)
(3,4)
____
____
____
____
0
0
0
0
t
OLZ
____
____
____
____
Output Enable High to Data High-Z
3.5
3.5
4.2
5
ns
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
Clock Enable Setup Time
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
ns
ns
ns
ns
t
t
Data In Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup
____
____
____
____
____
____
____
____
____
____
____
____
t
SADV
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
2.0
2.0
2.0
ns
ns
ns
Time
tSC
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup
Time
tSB
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
4875 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.1462
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
17
tCYC
CLK
tCH
tCL
tSE
tHE
CEN
tSADV
tHADV
ADV/LD
R/W
t
SW
t
HW
HA
tSA
t
A2
ADDRESS
A1
tSC
tHC
CE1, CE2 (2)
tSB
tHB
BW1 - BW4
OE
(CEN high, eliminates
current L-H clock edge)
(Burst Wraps around
to initial state)
tSD
tHD
tSD
tHD
DATAIN
D(A1)
D(A2)
D(A2+3
)
D(A2)
D(A2+1
)
D(A2+2
)
Pipeline
Write
Burst Pipeline Write
4875 drw 07
Pipeline
Write
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of theLBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/Wis don'tcarewhentheSRAMis bursting(ADV/LDsampledHIGH). Thenatureoftheburstaccess (ReadorWrite)is fixedbythestateoftheR/Wsignalwhennewaddress andcontrolare
loadedintotheSRAM.
5. IndividualByteWritesignals(BWx)mustbevalidonallwriteandburst-writecycles.AwritecycleisinitiatedwhenR/WsignalissampledLOW. Thebytewriteinformationcomesintwocyclesbefore
theactualdataispresentedtotheSRAM.
tCYC
CLK
tCH
tCL
tSE
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
tHA
A2
A5
A4
A8
A9
A3
A1
A6
A7
ADDRESS
tSC
tHC
(2)
CE1, CE2
tSB
tHB
BW1 - BW4
OE
tSD tHD
D(A5)
D(A4)
D(A2)
DATAIN
Write
Write
t
tCLZ
CDC
t
CHZ
tCD
Q(A6)
Q(A3)
Q(A7)
Q(A1)
DATAOUT
Read
Read
Read
4875 drw 08
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
tCYC
CLK
tCH
tCL
tSE
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
tHA
A2
A4
A5
A1
A3
ADDRESS
tSC
tHC
(2)
CE1, CE2
tSB
tHB
B(A2)
BW1 - BW4
OE
tSD tHD
D(A2)
DATAIN
tCHZ
tCDC
tCD
Q(A1)
Q(A3)
Q(A1)
DATAOUT
t
CLZ
4875 drw 09
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to theCE1 andCE2 signals. For example, whenCE1 andCE2 are LOW on this waveform, CE2 is HIGH.
3. CENwhensampledhighontherisingedgeofclockwillblockthatL-HtransitionoftheclockfrompropogatingintotheSRAM. Thepartwillbehaveas iftheL-Hclocktransitiondidnotoccur. All
internalregistersintheSRAMwillretaintheirpreviousstate.
4. IndividualByteWritesignals(BWx)mustbevalidonallwriteandburst-writecycles.AwritecycleisinitiatedwhenR/WsignalissampledLOW. Thebytewriteinformationcomesintwocyclesbefore
theactualdataispresentedtotheSRAM.
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
21
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
t
JCYC
t
JR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M4875 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
(1)
____
t
5
ns
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
(1)
____
t
5
ns
Note (1)
____
____
t
50
ns
I4875 tbl 03
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I4875 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.2422
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Revision Number (31:28)
Value
Description
0x2
0x210, 0x212
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71V2556SA and 71V2558SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I4875 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I4875 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
23
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100 Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.2442
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
25
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.2462
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
4875 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
6.42
27
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
6/30/99
8/23/99
Updatedtonewformat
AddedSmartZBTfunctionality
Pp. 4, 5
Pg. 6
Added Note 4 and changed Pins 38, 42, and 43 to DNU
Changed U2–U6 to DNU
Pg. 14
Pg. 15
AddedSmartZBTACElectricalCharacteristics
ImprovedtCD andtOE(MAX)at166MHz
Revised tCHZ(MIN) for f ≤ 133 MHz
Revised tOHZ (MAX) for f ≤ 133 MHz
ImprovedtCH, tCL forf≤166MHz
Improvedsetuptimesfor100–200MHz
Pg. 22
Pg. 24
Pg. 14
Pg. 15
AddedBGApackagediagrams
AddedDatasheetDocumentHistory
RevisedACElectricalCharacteristicstable
Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz
RemovedSmartfunctionality
AddedIndustrialTemperaturerangeofferings atthe100to166MHzspeedgrades.
AddclarificationnotetoRecommendedTemperatureRatingsandAbsoluteMaxRatings
table;AddnotetoTQFPPinConfigurations
10/4/99
12/31/99
04/30/00
Pg. 5,6
Pg. 6
Pg. 7
Pg. 21
AddBGACapacitancetable
AddnotetoBGAPinConfigurations
InsertTQFPPackageDiagramOutline
05/26/00
07/26/00
Addnewpackageoffering,13x15mm165fBGA
Correct119BGAPackageDiagramOutline
Addzz, sleepmode reference note toTQFP, BG119andBQ165pinouts
UpdateBQ165pinout
Pg. 23
Pg. 5,6,7
Pg. 8
Pg. 23
UpdateBG119packagediagramoutlines
10/25/00
RemovePreliminaryStatus
Pg. 8
Pg. 1-8,15,22,23,27
Pg.7
Add note to pin N5, BQ165 pinout reserved for JTAG TRST
AddedJTAG"SA"versionfunctionality&updatedZZpindescriptions andnotes.
Updated pin configuration for the 119 BGA - reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
AddedX generatondiesteptoorderinginformation.
Removed "IDT" from orderable part number
Added"Restrictedhazardoussubstancedevice"totheorderinginformation
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CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
800-345-7015 or
408/284-4555
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
6.2482
相关型号：
71V2558XSA200BGG
ZBT SRAM, 256KX18, 3.2ns, CMOS, PBGA119, 22 X 14 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119
IDT
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