71V30L55TFGI8 [IDT]
HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM;
| 型号： | 71V30L55TFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM |
| 文件： | 总15页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V30S/L
HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
Features
◆
◆
High-speed access
On-chip port arbitration logic
◆
◆
◆
◆
◆
Interrupt flags for port-to-port communication
– Commercial: 25/35/55ns (max.)
– Industrial 35ns (max.)
Fully asynchronous operation from either port
Battery backup operation, 2V data retention (L Only)
TTL-compatible, single 3.3V ±0.3V power supply
Industrial temperature range (-40OC to +85OC) is available
for selected speeds
◆
Low-power operation
– IDT71V30S
— Active: 375mW (typ.)
— Standby: 5mW (typ.)
– IDT71V30L
— Active: 375mW (typ.)
— Standby: 1mW (typ.)
◆
Green parts available, see ordering information
Functional Block Diagram
OE
R
OEL
CE
R
CE
R/WL
L
R/W
R
I/O0R-I/O7R
I/O0L- I/O7L
I/O
Control
I/O
Control
(1)
(1)
BUSYR
BUSY
L
A
9L
0L
A
9R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
10
10
ARBITRATION
and
INTERRUPT
LOGIC
CE
OE
L
L
CE
OE
R/W
R
R
R
R/W
L
(2)
(2)
INTL
INTR
3741 drw 01
NOTES:
1. IDT71V30: BUSY outputs are non-tristatable push-pulls.
2. INT outputs are non-tristable push-pull output structure.
JULY 2015
1
DSC 3741/12
©2015 Integrated Device Technology, Inc.
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
The IDT71V30 is a high-speed 1K x 8 Dual-Port Static RAM. The
IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 375mW of power. Low-power (L) ver-
sions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
SRAM.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
The IDT71V30 devices are packaged in 64-pin STQFPs.
PinConfigurations(1,2,3)
INDEX
OE
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A
1L
A
A2L
3L
A
4L
A
A
5L
6L
A
N/C
A
7L
A8L
9L
A
N/C
L
0L
48
47
46
0R
A
A
A
A
A
A
A
1R
2R
3R
4R
5R
6R
45
44
43
42
41
40
39
38
37
36
35
34
33
IDT71V30TF
PP64(4)
64-Pin STQFP
Top View(5)
N/C
7R
A
8R
A
9R
A
N/C
N/C
I/O0L
7R
I/O
1L
I/O
I/O6R
2L
I/O
3741 drw 03
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking.
6.42
2
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended
DC Operating Conditions
Symbol
Rating
Com'l & Ind
Unit
(2)
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
Typ.
Max.
3.6
0
Unit
V
V
TERM
Terminal Voltage
-0.5 to +4.60
V
with Respect to GND
V
CC
3.3
Temperature
Under Bias
-55 to +125
-65 to +150
oC
oC
T
BIAS
GND
0
0
V
____
V
IH
Input High Voltage
Input Low Voltage
2.0
V
CC+
0.3V
V
Storage
TSTG
Temperature
-0.3(1)
0.8
V
____
V
IL
(3)
JN
T
Junction Temperature
+150
50
oC
3741 tbl 02
NOTE:
DC Output
Current
mA
I
OUT
1. VIL (min.) = -1.5V for pulse width less than 20ns.
3741 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
MaximumOperating
TemperatureandSupplyVoltage(1,2)
Ambient
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
3. This is the absolute maximum junction temperature for the device. No DC Bias.
3.3V
3.3V
+
+
0.3
0V
0.3
3741 tbl 03
NOTES:
Capacitance(1) (TA = +25OC, f=1.0MHz)
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers,
contact your sales office.
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
9
Unit
CIN
V
IN = 3dV
pF
(3)
C
OUT
V
OUT = 3dV
10
pF
3741 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
71V30S
71V30L
Symbol
|ILI
Parameter
Test Conditions
Min.
___
Max.
Min.
___
Max.
Unit
|
Input Leakage
V
V
= 3.6V,
10
5
µA
Current(1)
ICNC= 0V to VCC
___
___
___
___
10
5
µA
V
|ILO
|
Output Leakage
Current
CE = V ,
V
OUT = I0HV to VCC
V
OL
Output Low Voltage
IOL = 4mA
0.4
0.4
(I/O
0
-I/O )
7
___
___
V
OH
Output High Voltage
IOH = -4mA
2.4
2.4
V
3741 tbl 05
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Supply CurrentVIN > VCC -0.2V or < 0.2V
3
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V)
71V30X25
71V30X35
71V30X55
Com'l Only
Com'l & Ind
Com'l Only
Typ.(2)
Typ.(2)
Symbol
Parameter
Test Condition
Version
COM'L
Max.
Max.
Typ.(2)
Max. Unit
mA
ICC
Dynamic Operating Current CE
L
and CE = V
,
S
L
75
150
75
145
75
135
(Both Ports Active)
Outputs(3D) isRabledIL
75
120
75
115
75
105
f = fMAX
___
___
___
___
___
___
___
___
___
___
IND
S
L
75
145
mA
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE and CE
R= VIL
,
COM'L
IND
S
L
20
20
50
35
20
50
20
20
50
35
f =LfMAX
20
35
(3)
___
___
___
___
___
___
S
L
___
___
___
___
20
50
(5)
mA
ISB2
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE = VIH
COM'L
IND
S
L
30
30
105
75
30
100
30
30
90
60
Active(3P) ort Outputs"BD" isabled,
30
70
f=fMAX
___
___
___
___
___
___
S
L
___
___
___
___
30
100
mA
ISB3
Full Standby Current (Both
Ports - CMOS Level Inputs)
CE and CE > VCC - 0.2V
COM'L
IND
S
L
1.0
0.2
5.0
3.0
1.0
5.0
1.0
0.2
5.0
3.0
V
L> VCC - R0.2V or
0.2
3.0
VIN < 0.2V, f = 0(4)
___
___
___
___
___
___
S
L
___
___
___
___
1.0
5.0
mA
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L
IND
S
L
30
30
___
___
90
75
___
___
30
85
30
30
___
___
75
60
___
___
CE"B" > VCC - 0.2V(5)
30
70
V
IN > VCC - 0.2V or VIN < 0.2V
___
___
S
L
Active(3P) ort Outputs Disabled
f=fMAX
30
85
3741 tbl 06
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to chip enable Truth Table I.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics (L Version Only)
71V30L
Symbol
Parameter
CC for Data Retention
Test Condition
Min.
Typ.(1)
____
Max.
____
Unit
V
V
DR
V
2.0
____
ICCDR
Data Retention Current
Ind.
100
1000
µA
____
V
V
CC = 2V, CE > VCC -0.2V
IN > VCC -0.2V or VIN < 0.2V
Com'l.
100
____
500
____
(3)
CDR
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
____
____
tR
tRC
ns
3741 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
4
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Data Retention Waveform
DATA RETENTION MODE
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CC
V
≥
DR
V
2.0V
3.0V
3.0V
tCDR
tR
DR
V
CE
3741 tbl 08
IH
V
IH
V
,
3741 drw 04
3.3V
3.3V
590Ω
590Ω
DATA OUT
DATA OUT
435Ω
BUSY
435Ω
INT
30pF
5pF
3741 drw 05
Figure 2. Output Test Load
(For tHZ, tLZ, tWZ and tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,4)
71V30X25
71V30X35
Com'l & Ind
71V30X55
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
t
t
t
t
t
t
t
t
RC
Read Cycle Time
25
____
35
____
55
____
ns
ns
ns
ns
ns
ns
ns
ns
AA
Address Access Time
Chip Enable Access Time
Output Enable Access Time
25
25
35
35
55
55
____
____
____
____
____
____
ACE
AOE
OH
LZ
12
____
20
____
25
____
Output Hold from Address Change
Output Low-Z Time(1,2)
Output High-Z Time(1,2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
3
3
3
____
____
____
0
____
0
____
0
____
HZ
12
____
15
____
30
____
PU
PD
0
____
0
____
0
____
50
50
50
ns
3741 tbl 09
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and power contact your sales office.
5
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
3741 drw 06
(2,3)
tBDD
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operations BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
t
ACE
CE
OE
(4)
(2)
tHZ
tAOE
(2)
(1)
t
HZ
t
LZ
VALID DATA
DATAOUT
(1)
(4)
tLZ
tPD
tPU
CC
I
CURRENT
50%
50%
SS
I
3741 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is desserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, and tBDD.
6.42
6
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(4,5)
71V30X25
71V30X35
71V30X55
Com'l Only
Com'l & Ind
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
t
t
t
t
WC
EW
AW
AS
Write Cycle Time
25
20
20
0
35
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
WP
WR
DW
HZ
Write Pulse Width
20
0
30
0
40
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,3)
12
____
20
____
20
____
12
____
15
____
30
____
DH
WZ
OW
0
____
0
____
0
____
15
____
15
____
30
____
0
0
0
ns
3741 tbl 10
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperatures: for specific speeds, packages and powers contact your sales office.
7
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1,(R/W Controlled Timing)(1,5,8)
t
WC
ADDRESS
OE
(7)
tHZ
tAW
CE
(2)
(7)
(6)
(3)
t
AS
tWR
tWP
tHZ
R/W
(7)
tOW
t
WZ
(4)
(4)
OUT
DATA
tDW
tDH
IN
DATA
3741 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
CE
tAW
(3)
(6)
(2)
tAS
tWR
tEW
R/W
tDW
tDH
IN
DATA
3741 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
6.42
8
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
71V30X25
71V30X35
Com'l & Ind
71V30X55
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
t
t
BAA
BDA
BAC
BDC
WH
20
20
20
20
20
20
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(5)
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time(2)
20
____
20
____
30
____
20
____
30
____
40
____
WDD
DDD
APS
BDD
50
60
80
____
____
____
35
____
45
____
65
____
5
____
5
____
5
____
BUSY Disable to Valid Data(3)
30
30
45
ns
3741 tbl 11
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”.
5. To ensure that the Write Cycle is completed on Port “B” after contention on Port “A”.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Write with Port-to-Port Read with BUSY(1,2,3,4)
tWC
ADDR"A"
MATCH
t
WP
R/W"A"
tDW
t
DH
DATAIN"A"
VALID
(1)
APS
t
ADDR"B"
BUSY"B"
MATCH
tBDD
BDA
t
tWDD
DATAOUT"B"
VALID
t
DDD
3741 drw 10
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
9
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(3)
tWP
R/W'A'
tWB
BUSY'B'
(1)
tWH
,
R/W'B'
(2)
NOTES:
3741 drw 11
1. tWH must be met for BUSY.
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
'A' AND 'B'
ADDRESSES MATCH
CE'B'
(2)
tAPS
CE'A'
tBAC
t
BDC
BUSY'A'
3741 drw 12
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
TimingWaveformof BUSY ArbitrationControlledAddressMatchTiming(1)
tRC OR tWC
ADDR'A'
ADDR'B'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
t
APS
tBAA
tBDA
BUSY'B'
3741 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
6.42
10
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
71V30X25
71V30X35
71V30X55
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
t
t
t
AS
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
WR
INS
INR
0
____
0
____
0
____
25
25
25
25
45
45
____
____
____
Interrupt Reset Time
ns
3741 tbl 12
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Interrupt Mode(1)
INT Sets
tWC
INTERRUPT ADDRESS (2)
ADDR'A'
(4)
(3)
t
WR
tAS
R/W'A'
INT'B'
(3)
t
INS
3741 drw 14
INT Clears
tRC
ADDR'B'
INTERRUPT CLEAR ADDRESS
(3)
t
AS
OE'B'
INT'A'
(3)
t
INR
3741 drw 15
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
11
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Table I — Non-Contention Read/Write Control(4)
(1)
Left or Right Port
R/W
X
CE
H
H
L
OE
X
D
0-7
Function
Port Disabled and in Power-Down Mode, ISB2 or ISB4
CER = CEL = Power-Down Mode, ISB1 or ISB3
Data on Port Written Into Memory(2)
Z
X
X
Z
VIH,
L
X
DATAIN
H
L
L
DATAOUT Data in Memory Output on Port(3)
H
L
H
Z
High Impedance Outputs
3741 tbl 13
NOTES:
1. A0L – A9L ≠ A0R – A9R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Table II — Interrupt Flag(1,4)
Left Port
Right Port
OE
R/W
L
A
9L-A0L
3FF
X
R/W
R
A
9R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
L
CE
R
R
INT
R
L
X
X
X
L
X
X
L
X
X
X
L
X
X
X
X
L
L
X
X
L
X
L(2)
H(3
X
R
)
X
3FF
3FE
X
R
X
L(3)
H(2)
L
X
X
L
3FE
X
X
L
3741 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Table III — Address BUSY Arbitration
Inputs
Outputs
A
-A
AOORL-A99RL
Function
Normal
(1)
(1)
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
Normal
MATCH
H
H
Normal
Write Inhibit(3)
MATCH
(2)
(2)
3741 tbl 15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V30. BUSYX outputs on the
IDT71V30 are non-tristatable push-pull.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result.
BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
6.42
12
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
FunctionalDescription
The IDT71V30 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT71V30 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
at3FEor3FFisuser-defined,sinceitisanaddressableSRAMlocation.
Iftheinterruptfunctionisnotused,addresslocations3FEand3FFarenot
used as mail boxes, and are part of the random access memory. Refer
toTableIIfortheinterruptoperation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “Busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FE (HEX), where a write is defined as the CE = R/W = VIL per Truth
TableII.Theleftportclearstheinterruptbyaccessingaddresslocation
3FE access with CER = OER = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
right port must access the memory location 3FF. The message (8 bits)
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
eventofanillegalorillogicaloperation.
13
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
A
A
XXXXX
99
A
A
A
Device
Type
Power
Speed Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
)
I(1
)
G(2
Green
TF
64-pin STQFP (PP64)
25
35
55
Commercial Only
Commercial & Industrial
Commercial Only
Speed in nanoseconds
S
L
Standard Power
Low Power
8K (1K x 8-Bit) Synchronous Dual-Port RAM
71V30
3741 drw 20
NOTES:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
12/9/98:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/15/99:
8/3/99:
Page 2 Fixed typographical error
9/1/99:
RemovedPreliminary
11/12/99:
1/17/01:
Replaced IDT logo
Pages 1 and 2 Moved all of "Description" to page 2 and adjusted page layouts
Page 3 Increasedstoragetemperatureparameters
ClarifiedTA parameter
Page 4 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
3/14/05:
7/16/07:
Page 1 Addedgreenavailabilitytofeatures
Page 17 Addedgreenindicatortoorderinginformation
Page 1 & 17 Replaced old TM logo with new TM logo
Page 3 AddedJunctionTemperaturespecvaluestotheAbsoluteMaximumRatingtable
Addedfootnote3foradditionalclarificationofJunctionTemperature
6.42
14
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(con't)
10/23/08:
11/25/09:
Page 14 Removed "IDT" from orderable part number
Page 4 InordertocorrecttheDCCharstableforthe71V30L35speedgradeandtotheDataRetentionCharstable,ITemp
valueshavebeenaddedtoeachtablerespectively.Inaddition,alloftheACtablesandtheorderinginformation also
nowreflect thisItempcorrection
06/22/15:
07/23/15:
Page 2
RemovedIDTinreferencetofabrication
Page 2 & 14
Page 14
The package code PP64-1 changed to PP64 to match standard package codes
AddedTapeandReelindicatortoOrderingInformation
Entiredatasheet
Removedthe55nsIndustrialspeedoffering. 55nsspeedonlyofferedincommercialgrade
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
408-284-2794
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
15
6.42
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