71V632ZS5PFG8 [IDT]
Standard SRAM, 64KX32, 5ns, CMOS, PQFP100;
| 型号： | 71V632ZS5PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 64KX32, 5ns, CMOS, PQFP100 静态存储器 |
| 文件： | 总19页 (文件大小：1342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64K x 32
IDT71V632/Z
3.3VSynchronousSRAM
PipelinedOutputs
BurstCounter,SingleCycleDeselect
Features
withfullsupportofthePentium™andPowerPC™processorinterfaces.
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-
arycache performance forprocessors upto117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers.Internallogicallows theSRAMtogenerateaself-timedwrite
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite
cycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner, as the IDT71V632canprovide fourcycles ofdata for
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore
it is available on the next rising clock edge. If burst mode operation is
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe
availabletotheuseronthenextthreerisingclockedges.Theorderofthese
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO
inputpin.
◆
64K x 32 memory configuration
◆
Supports high system speed:
Commercial:
– A4 4.5ns clockaccess time (117MHz)
CommercialandIndustrial:
– 5 5ns clockaccess time (100MHz)
– 6 6ns clockaccess time (83MHz)
– 7 7ns clockaccess time (66MHz)
◆
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
◆
◆
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
◆
◆
◆
thin quad flatpack (TQFP).
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity
inbothdesktopandnotebookapplications.
Description
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32
PinDescriptionSummary
A0–A15
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0
, CS
1
Chips Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW1, BW2, BW3, BW
4
CLK
ADV
ADSC
ADSP
LBO
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ZZ
Asynchronous
Synchronous
N/A
I/O
0
–I/O31
DD, VDDQ
SS, VSSQ
Data Input/Output
V
3.3V
Power
Power
V
Array Ground, I/O Ground
N/A
3619 tbl 01
PentiumprocessorisatrademarkofIntelCorp.
PowerPCisatrademarkofInternationalBusinessMachines,Inc.
OCTOBER 2008
1
©2007IntegratedDeviceTechnology,Inc.
DSC-3619/05
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination
A0–A15
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller.ADSC is an active LOW
input that is used to load the address registers with new addresses. ADSC is
NOT GATED by CE.
ADSC
Synchronous Address Status from Processor. ADSP is an active LOW input that
Address Status
(Processor)
I
I
LOW
LOW
ADSP
ADV
is used to load the address registers with new addresses. ADSP is gated by
CE.
Burst Address Advance
Synchronous Address Advance. ADV is an active LOW input that is used to
advance the internal burst counter, controlling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no address advance.
Byte Write Enable
I
I
LOW
LOW
Synchronous byte write enable gates the byte write inputs BW
LOW at the rising edge of CLK then BW inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
is LOW at the rising edge of CLK then data will
1
–BW
4
. If BWE is
BWE
X
CLK. If ADSP is HIGH and BW
X
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
Individual Byte
Write Enables
Synchronous byte write enables. BW
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW –BW must meet specified setup and hold times
with respect to CLK.
1
controls I/O(7:0), BW2 controls I/O(15:8),
BW
1
–BW
4
1
4
Chip Enable
Clock
I
I
I
I
LOW
N/A
Synchronous chip enable. CE is used with CS
IDT71V632. CE also gates ADSP.
0
and CS1 to enable the
CE
CLK
This is the clock input. All timing references for the device are made with respect
to this input.
Chip Select 0
Chip Select 1
HIGH
LOW
Synchronous active HIGH chip select. CS
the chip.
0
is used with CE and CS
1
to enable
CS
0
Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to enable
CS1
the chip.
Synchronous global write enable. This input will write all four 8-bit data bytes
when LOW on the rising edge of CLK. GW supercedes individual byte write
enables.
Global Write Enable
I
LOW
GW
Data Input/Output
Linear Burst Order
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
I/O0–I/O31
LOW
Asynchronous burst order selection DC input. When LBO is HIGH the Interleaved
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
sequence is selected. LBO is a static DC input and must not change state while
the device is operating.
LBO
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are
enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O
pins are in a high-impedence state.
V
DD
DDQ
SS
SSQ
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
HIGH
3.3V core power supply inputs.
3.3V I/O power supply inputs.
Core ground pins.
V
V
V
Ground
I/O ground pins.
NC
ZZ
No Connect
Sleep Mode
NC pins are not electrically connected to the chip.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V632 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode.
3619 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
INTERNAL
ADDRESS
CE
CLK
2
Burst
Logic
64K x 32
BIT
MEMORY
ARRAY
Binary
Counter
16
ADSC
A0*
Q0
Q1
CLR
.
A1*
ADSP
2
CLK EN
ADDRESS
REGISTER
A0, A1
A2–A15
A
0
–A15
GW
BWE
32
32
16
Byte 1
Write Register
Byte 1
Write Driver
BW
1
8
8
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
8
8
Byte 4
Write Register
Byte 4
Write Driver
BW4
OUTPUT
REGISTER
CE
Q
D
CS0
CS
Enable
DATA INPUT
REGISTER
1
Register
CLK EN
Powerdown
ZZ
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
–I/O31
32
I/O0
3619 drw 01
6.42
3
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Rating
Value
Unit
Grade
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
V
DD
VDDQ
(2)
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
V
TERM
Commercial
Industrial
0V
0V
3.3V+10/-5% 3.3V+10/-5%
(3)
TERM
Terminal Voltage with
Respect to GND
–0.5 to VDD+0.5
V
V
3.3V+10/-5% 3.3V+10/-5%
3619 tbl 03
T
A
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
0 to +70
–55 to +125
–55 to +125
1.0
oC
oC
oC
W
T
BIAS
STG
RecommendedDCOperating
Conditions
T
P
T
I
OUT
DC Output Current
50
mA
Symbol
Parameter
Min.
3.135
3.135
0
Max.
3.63
3.63
0
Unit
V
3619 tbl 05
V
DD
DDQ
SS,
IH
IH
IL
Core Supply Voltage
I/O Supply Voltage
Ground
NOTES:
V
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD, VDDQ and Input terminals only.
V
VSSQ
V
V
Input High Voltage — Inputs
Input High Voltage — I/O
Input Low Voltage
2.0
5.0(1)
V
V
2.0
V
DDQ+0.3(2)
V
3. I/O terminals.
V
–0.3(3)
0.8
V
3619 tbl 04
NOTES:
1. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
6
7
pF
CI/O
V
pF
3619 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
4
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinConfiguration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
I/O15
I/O14
NC
I/O16
I/O17
2
79
3
78
4
77
V
DDQ
VDDQ
5
V
SSQ
I/O18
I/O19
I/O20
I/O21
76
75
74
73
VSSQ
6
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSSQ
VSSQ
V
DDQ
VDDQ
69
68
67
66
65
64
I/O22
I/O23
DD/NC(1)
I/O9
I/O8
VSS
V
NC
VDD
PK100-1
NC
V
DD
ZZ(2)
V
SS
I/O24
I/O25
63
62
I/O7
I/O6
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
V
V
DDQ
SSQ
VSSQ
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSSQ
V
V
SSQ
DDQ
VDDQ
I/O30
I/O31
NC
I/O1
I/O0
NC
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
3619 drw 02
TopViewTQFP
NOTES:
1. Pin 14 can either be directly connected to VDD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,2)
Address
Operation
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
Used
None
CE
H
L
CS
0
CS
1
ADSP ADSC ADV
GW
X
X
X
X
X
X
X
H
H
H
H
L
BWE
X
X
X
X
X
X
X
H
L
BW
X
OE(3 ) CLK
I/O
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
None
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
Hi-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Hi-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
Hi-Z
Next
L
DOUT
Next
L
H
L
Hi-Z
Next
L
DOUT
Next
L
H
L
Hi-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
Hi-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
Hi-Z
DOUT
H
L
Hi-Z
DOUT
H
L
Hi-Z
DOUT
H
X
X
X
X
Hi-Z
D
IN
IN
IN
IN
3619 tbl 07
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
6.42
6
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
Operation
GW
H
H
L
BWE
H
L
BW1
BW
2
BW
3
BW4
Read
Read
X
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
Write all Bytes
Write all Bytes
Write Byte 1(2)
Write Byte 2(2)
Write Byte 3(2)
Write Byte 4(2)
X
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
L
H
3619 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
OE
ZZ
I/O Status
Data Out (I/O - I/O31
High-Z
Power
Active
Active
Active
Read
Read
L
L
0
)
H
X
X
X
L
Write
L
High-Z — Data In (I/O0 - I/O31)
Deselected
Sleep
L
High-Z
Standby
Sleep
H
High-Z
3619 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
Fourth Address(1)
NOTE:
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
3619 tbl 10
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
Fourth Address(1)
NOTE:
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
3619 tbl 11
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
7
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 3.3V +10/-5%)
Unit
µA
µA
µA
V
Symbol
|ILI
|ILZZ
|ILO
Parameter
Test Conditions
DD = Max., VIN = 0V to VDD
DD = Max., VIN = 0V to VDD
Min.
—
Max.
5
|
Input Leakage Current
V
|
ZZ and LBO Input Leakage Current(1)
V
—
30
5
|
Output Leakage Current
—
CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max.
OL = 5mA, VDD = Min.
OH = –5mA, VDD = Min.
V
OL (3.3V) Output Low Voltage
OH (3.3V) Output High Voltage
NOTE:
I
—
0.4
—
V
I
2.4
V
3619 tbl 12
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1) (VHD = VDDQ – 0.2V, VLD = 0.2V)
SA4(3,4)
S5
S6
S7
Symbol
Parameter
Test Conditions
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
220
70
—
200
200
180
180
160
160
mA
V
DD = Max., VIN > VIH or < VIL,
(2)
f = fMAX
ISB
Standby Power
Supply Current
Device Deselected, Outputs Open,
—
—
—
65
15
10
65
15
10
60
15
10
60
15
10
55
15
10
55
15
10
mA
mA
V
DD = Max., VIN > VIH or < VIL,
(2)
f = fMAX
ISB1
Full Standby Power
Supply Current
Device Deselected, Outputs Open,
15
V
DD = Max., VIN > VHD or < VLD,
f = 0(2)
Full Sleep Mode
Power Supply Current
ZZ > VHD, VDD = Max.
10
mA
I
ZZ
3619 tbl 13
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. SA4 speed grade corresponds to a tCD of 4.5 ns.
4. 0°C to +70°C temperature range only.
+3.3V
AC Test Loads
VDDQ/2
317Ω
I/O
50Ω
5pF*
I/O
Z0 = 50Ω
351Ω
3619 drw 03
Figure 1. AC Test Load
3619 drw 04
* Including scope and jig capacitance.
6
Figure 2. High-Impedence Test Load
5
4
3
2
1
(for tOHZ, tCHZ, tOLZ, and tDC1)
∆tCD
(Typical, ns)
AC Test Conditions
Input Pulse Levels
0 to 3.0V
Input Rise/Fall Times
2ns
1.5V
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
20 30 50
80 100
Capacitance (pF)
200
1.5V
3619 drw 05
See Figures 1 and 2
Figure 3. Lumped Capacitive Load, Typical Derating
3619 tbl 14
6.42
8
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD, VDDQ = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V632SA4(5,6)
71V632S5
71V632S6
71V632S7
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
CLOCK PARAMETERS
____
____
____
____
____
____
____
____
____
____
____
____
t
CYC
Clock Cycle Time
8.5
3.5
3.5
10
4
12
4.5
4.5
15
5
ns
ns
ns
(1)
CH
t
Clock High Pulse Width
Clock Low Pulse Width
(1)
CL
t
4
5
OUTPUT PARAMETERS
____
____
____
____
t
CD
Clock High to Valid Data
4.5
5
6
7
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
1.5
0
1.5
0
2
0
2
0
(2)
(2)
____
____
____
____
tCLZ
tCHZ
1.5
4
1.5
5
2
5
2
6
____
____
____
____
tOE
4
5
5
6
(2)
____
____
____
____
tOLZ
0
0
0
0
(2)
OHZ
____
____
____
____
t
4
4
5
6
SETUP TIMES
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
2.2
2.2
2.2
2.2
2.2
2.2
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data in Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
HOLD TIMES
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
SLEEP MODE AND CONFIGURATION PARAMETERS
____
____
____
____
____
____
____
____
____
t
ZZPW
ZZ Pulse Width
100
100
34
100
100
40
—
—
—
100
100
50
100
100
50
ns
ns
(3)
ZZR
t
ZZ Recovery Time
Configuration Set-up Time
(4)
CFG
t
ns
3619 tbl 15
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. The 71V632SA4 speed grade corresponds to a tCD of 4.5ns.
6. 0°C to +70°C temperature range only.
6.42
9
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
6.42
10
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
6.42
11
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
.
6.42
12
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
6.42
13
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
6.42
14
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
3619 drw 11
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
6.42
15
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS
1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
3619 drw 12
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
16
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
17
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
71V632
X
Z
S
PF
X
Process/
Tempera-
ture Range
Device
Type
Power Speed
Package
Blank Commercial (0°C to +70°C)
I
Industrial (–40°C to +85°C)
PF
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
A4*
5
6
Synchronous Access Time in nanoseconds
7
Blank
Z
First or current generation die step.
Current generation die step optional.
* Commercial only.
PART NUMBER
71V632SA4PF
71V632S5PF
71V632S6PF
71V632S7PF
SPEED IN MEGAHERTZ
117 MHz
t
CD PARAMETER
CLOCK CYCLE TIME
4.5 ns
5 ns
8.5 ns
10 ns
12 ns
15 ns
100 MHz
83 MHz
6 ns
66 MHz
7 ns
3619 drw 13
6.42
18
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
9/9/99
Updatedtonewformat
Revisedspeedofferingsto66–117MHz
Pg. 1, 8, 9, 17
Pg. 15, 16
Pg. 18
Addednon-burstreadandwritecycletimingdiagrams
AddedDatasheetDocumentHistory
09/30/99
04/04/00
08/09/00
08/17/01
02/28/07
10/16/08
Pg. 1, 4, 8, 9, 17
Pg. 17
Addedindustrialtemperaturerangeofferings
Added100pinTQFPpackageDiagramOutline
Notrecommendedfornewdesigns
Removed“Notrecommendedfornewdesigns”fromthebackgroundonthedatasheet
AddedZgenerationdiesteptodatasheetorderinginformation.
Removed "IDT" from orderable part number
Pg.18
Pg.18
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
19
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