71V67602S133BGG [IDT]
PBGA-119, Tray;
| 型号： | 71V67602S133BGG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PBGA-119, Tray 时钟 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K X 36, 512K X 18
3.3VSynchronousSRAMs
2.5V I/O, Burst Counter
IDT71V67602
IDT71V67802
PipelinedOutputs,SingleCycleDeselect
Features
Description
◆
256K x 36, 512K x 18 memory configurations
Supports high system speed:
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof
thewritecycle.
◆
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
◆
◆
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
orderofthesethreeaddressesaredefinedbytheinternalburstcounter
andthe LBO inputpin.
◆
◆
◆
◆
TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and 165 fine pitch ball grid array (fBGA).
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS0, CS1
OE
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
GW
BWE
(1 )
BW1, BW2, BW3, BW4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
VDD, VDDQ
VSS
Supply
Supply
N/A
5311 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
FEBRUARY 2009
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5311/07
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
ADSC
ADSP
CE
Low and Low.
rising edge of CLK and
Low or
Address Status
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
ADSC
ADSP
ADV
(Cache Controller)
used to load the address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
inputis HIGH the burst counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BWE
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
BW1-BW4
CE
Chip Enable
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V67602/7802.
CE also gates ADSP.
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
CS0
CS1
GW
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
I/OP1-I/OP4
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data outputdrivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
VDD
VDDQ
VSS
NC
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
I
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
N/A
Ground.
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
ZZ
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67602/7802 to its lowestpower consumption level. Data retention is guaranteed in
Sleep Mode.
5311 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
256K x 36/
CLK
2
Burst
Logic
18/19
Binary
Counter
512K x 18-
ADSC
A0*
BIT
Q0
CLR
MEMORY
A1*
Q1
ADSP
ARRAY
2
CLK EN
A0,A1
A2–A18
A0–A17/18
GW
ADDRESS
REGISTER
36/18
36/18
18/19
Byte 1
Write Register
BW E
Byte 1
Write Driver
BW 1
BW 2
9
Byte 2
Write Register
Byte 2
Write Driver
9
Byte 3
Write Register
Byte 3
Write Driver
BW 3
BW 4
9
Byte 4
Write Register
Byte 4
Write Driver
9
OUTPUT
REGISTER
CE
CS0
CS1
Q
D
Enable
DATA INPUT
REGISTER
Register
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
,
36/18
I/O0–I/O31
I/OP1–I/OP4
5311 drw 01
6.42
3
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Rating
Commercial
Unit
Temperature(1)
0°C to +70°C
-40°C to +85°C
VSS
0V
0V
VDD
VDDQ
(2)
Grade
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
3.3V±5%
3.3V±5%
2.5V±5%
(3,6)
(4,6)
(5,6)
TERM
V
DD
-0.5 to V
Terminal Voltage with
Respect to GND
V
V
V
2.5V±5%
5311 tbl 04
NOTE:
1. TA is the "instant on" case temperature.
TERM
V
DD
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
TERM
V
DDQ
-0.5 to V +0.5
Terminal Voltage with
Respect to GND
RecommendedDCOperating
Conditions
Commercial
Industrial
-0 to +70
oC
oC
oC
(7)
A
T
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min. Typ.
3.135 3.3
2.375 2.5
Max.
Unit
V
-40 to +85
3.465
2.625
0
BIAS
Temperature
Under Bias
-55 to +125
T
V
STG
Storage
-55 to +125
oC
0
0
V
T
Temperature
____
VIH
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
1.7
VDD+0.3
VDDQ+0.3
0.7
V
T
P
Power Dissipation
DC Output Current
2.0
50
W
____
____
VIH
1.7
V
OUT
I
mA
VIL
-0.3(1)
V
5311 tbl 03
5311 tbl 06
NOTES:
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
100-pinTQFPCapacitance
(TA = +25°C, f = 1.0MHz)
165fBGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5
7
pF
7
7
pF
CI/O
pF
CI/O
pF
5311 tbl 07
5311 tbl 07b
119BGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
CI/O
pF
5311 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
2
3
4
5
76
75
74
73
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O22
I/O23
VDDQ
69
68
67
66
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
VDD / NC(1)
VDD
65
64
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
63
62
61
60
59
58
57
56
55
54
53
,
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5311 drw 02
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
A10
NC
NC
2
79
78
77
3
4
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
5
76
75
74
73
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O10
I/O11
VDD / NC(1)
VDD
69
68
67
66
65
64
NC
VSS
63
62
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
61
60
59
58
57
56
55
54
53
NC
VSS
VDDQ
NC
NC
NC
,
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5311 drw 03
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
ADSP
ADSC
(4)
A17
3
A
9
NC
NC
CS
0
NC
NC
7
2
A
DD
V
12
A
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
P2
15
I/O
V
V
V
NC
CE
V
V
V
I/O
I/O
I/O
I/O
17
I/O
18
I/O
SS
SS
13
12
11
14
I/O
DDQ
V
19
I/O
DDQ
V
OE
20
I/O
21
I/O
10
I/O
G
H
J
2
BW
3
BW
ADV
GW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
DDQ
V
DD
DD
DD
DDQ
V
NC
V
NC
V
V
24
26
SS
4
SS
6
7
K
L
I/O
I/O
V
CLK
NC
V
I/O
I/O
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
BW
DDQ
28
SS
SS
SS
SS
3
I/O
DDQ
V
I/O
V
V
V
V
V
V
V
M
N
P
R
T
BWE
29
I/O
30
I/O
SS
SS
1
A
2
I/O
1
I/O
0
31
P4
0
A
P1
I/O
I/O
NC
NC
I/O
I/O
(1)
NC
5
DD
11
13
A
V
V
/ NC
A
DD
LBO
(2)
10
A
14
,
NC
A
A
NC
DNU
ZZ
(3)
(3)
(3)
(3)
(3)
DDQ
V
DDQ
V
U
DNU
DNU
DNU
DNU
5311 drw 04
Top View
Pin Configuration 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
18
17
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
(4)
3
A
9
NC
NC
CS
NC
NC
NC
0
7
2
A
DD
13
A
A
V
8
SS
SS
SS
SS
SS
P1
I/O
I/O
NC
NC
V
V
V
NC
CE
V
V
V
V
V
9
SS
SS
7
I/O
I/O
NC
NC
DDQ
V
6
I/O
DDQ
V
OE
10
I/O
5
G
H
J
NC
NC
I/O
NC
DDQ
BW
2
ADV
GW
11
I/O
SS
SS
4
I/O
NC
DD
V
DDQ
V
DD
DD
V
V
NC
SS
V
V
NC
SS
12
I/O
3
I/O
NC
V
CLK
NC
V
NC
K
L
13
I/O
SS
2
I/O
NC
V
NC
1
BW
DDQ
14
I/O
SS
SS
V
DDQ
V
M
N
P
R
T
V
V
V
V
NC
BWE
15
I/O
SS
SS
1
A
SS
SS
1
I/O
NC
V
V
NC
P2
I/O
0
A
0
I/O
NC
NC
(1)
5
DD
12
A
NC
NC
DDQ
A
V
V
DD / NC
NC
LBO
15
(2)
,
10
14
11
A
A
A
NC
A
ZZ
(3)
DNU
(3)
DNU
(3)
(3)
DNU
(3)
DNU
DDQ
V
5311 drw 05
V
DNU
U
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. Pin U6 will be internally pulled to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, TRST should be tied low
and TCK, TDI, and TMS should be pulled through a resistor to 3.3V. TDO should be left unconnected.
4. On future 18M device CS0 will be removed, B2 will be be used for address expansion.
6.42
7
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
ADSC
OE
9
10
A8
11
(3)
A
B
C
D
E
F
NC
A7
NC
CE
BW3
BW2
CS1
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADV
(3)
NC
A6
CS0
A9
NC
BW
BW
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
4
1
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A10
NC
I/OP2
I/O14
I/O12
I/O10
I/O8
I/O16
I/O18
I/O20
I/O22
NC
I/O15
I/O13
I/O11
I/O9
NC
G
H
J
(1)
(2)
VDD
ZZ
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O7
I/O5
I/O3
I/O1
NC
I/O6
I/O4
I/O2
I/O0
I/OP1
A17
K
L
M
N
P
(3)
NC
(3)
(4)
(4)
NC
DNU
A1
A0
DNU
A14
A15
(3)
(4)
(4)
R
NC
A4
A3
DNU
DNU
A11
A12
A16
LBO
5311 tbl 17a
Pin Configuration 512K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
A8
11
(3)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A7
NC
A10
CE
BW2
NC
CS1
CLK
VSS
VSS
BWE
GW
VSS
VSS
ADSC
OE
ADV
(3)
A6
CS0
VDDQ
VDDQ
A9
NC
BW1
VSS
VSS
ADSP
VDDQ
VDDQ
NC
I/O8
VSS
VDD
VSS
VDD
NC
NC
NC
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
A15
A16
I/OP1
I/O7
6
I/O
9
DDQ
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
V
I/O
V
I/O10
I/O11
NC
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A11
VDDQ
VDDQ
NC
I/O5
I/O4
G
H
J
(1)
(2)
VDD
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
ZZ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A14
NC
NC
NC
NC
NC
A18
K
L
M
N
P
NC
NC
NC
(3)
NC
NC
A1
A0
(3)
(4)
(4)
NC
DNU
DNU
(3)
(4)
(4)
R
NC
A4
A3
DNU
DNU
A12
A13
A17
LBO
5311 tbl 17b
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
6.42
8
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|I |
LI
Input Leakage Current
V
DD = Max., V = 0V to V
5
µA
IN
DD
(1 )
___
___
___
ZZ and LBO Input Leakage Current
Output Leakage Current
Output Low Voltage
|ILZZ|
|ILO|
VOL
VOH
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VDDQ, Device Deselected
IOL = +6mA, VDD = Min.
30
5
µA
µA
V
0.4
___
Output High Voltage
IOH = -6mA, VDD = Min.
2.0
V
5311 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1)
166MHz
150MHz
Com'l
133MHz
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l Only
Ind
Ind
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
IDD
340
50
305
50
325
260
50
280
mA
mA
mA
(2)
Operating Power Supply Current
ISB1
CMOS Standby Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
70
175
70
70
170
70
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
160
50
155
50
150
50
(2,3)
VDDQ = Max., VIN > VHD or < VLD, f = fMAX
ZZ > VHD, VDD = Max.
IZZ
mA
Full Sleep Mode Supply Current
5311 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
AC Test Conditions
(VDDQ = 2.5V)
AC Test Load
Ω
50
Input Pulse Levels
0 to 2.5V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
5311 drw 06
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
VDDQ/2
Figure 1. AC Test Load
6
5
4
VDDQ/2
See Figure 1
5311 tbl 10
3
tCD
∆
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
5311 drw 07
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
CE
CS1 ADSP ADSC ADV
GW
BWE BWx
OE
(2)
Operation
Address
CS0
CLK
I/O
Used
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DOUT
HI-Z
DOUT
DOUT
HI-Z
DIN
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Read Cycle, Begin Burst
L
L
L
H
L
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
Read Cycle, Begin Burst
L
L
L
L
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Write Cycle, Begin Burst
L
L
L
L
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
X
X
X
X
L
Next
L
Next
L
X
L
X
L
DIN
Next
L
H
L
DIN
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
H
L
H
L
H
L
H
X
X
X
X
X
L
X
L
DIN
H
L
DIN
X
X
DIN
5311 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
10
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousWrite Function Truth Table(1, 2)
GW
H
H
L
BWE
H
L
BW1
BW2
X
BW3
X
BW4
X
Operation
Read
X
Read
H
H
H
H
Write all Bytes
Write all Bytes
Write Byte 1(3)
Write Byte 2(3)
Write Byte 3(3)
Write Byte 4(3)
X
L
X
X
X
X
H
H
H
H
H
L
L
L
L
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
5311 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67802.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5311 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
Second Address
Third Address
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)
1
0
0
1
0
5311 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5311 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
166MHz
150MHz
133MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
tCY C
Clock Cycle Time
6
6.7
2.6
2.6
7.5
3
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
2.4
2.4
tCH
____
____
____
(1)
3
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
3.5
3.8
4.2
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
1.5
0
1.5
0
1.5
0
(2)
____
____
____
Clock High to Output Active
Clock High to Data High-Z
tCL Z
(2)
1.5
3.5
1.5
3.8
1.5
4.2
ns
ns
ns
ns
tCHZ
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Output Active
Output Enable High to Output High-Z
3.5
3.8
4.2
____
____
____
(2)
0
0
0
tOLZ
____
____
____
(2)
3.5
3.8
4.2
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSA
tSS
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Status Setup Time
Data In Setup Time
tSD
tSW
tSAV
tSC
Write Setup Time
Address Advance Setup Time
Chip Enable/Select Setup Time
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tHS
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Address Status Hold Time
Data In Hold Time
tHD
tHW
tHAV
tHC
Write Hold Time
Address Advance Hold Time
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
tZZPW
ZZ Pulse Width
100
100
24
100
100
27
100
100
30
ns
ns
(3)
ZZ Recovery Time
Configuration Set-up Time
tZZR
____
____
____
(4)
ns
tCFG
5311 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42
12
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
,
6.42
13
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
,
6.42
14
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 GW Controlled(1,2,3)
,
6.42
15
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 Byte Controlled(1,2,3)
,
6.42
16
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
6.42
17
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
NOTES:
5311 drw 14
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
NOTES:
5311 drw 15
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
18
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42
19
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
20
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
21
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
XXX
S
X
XX
XX
Device
Type
Power Speed
Package
Process/Temp
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine pitch Ball Grid Array
PF
BG
BQ
166*
150
133
Frequency in Megahertz
256K x 36 Pipelined Burst Synchronous SRAM
512K x 18 Pipelined Burst Synchronous SRAM
71V67602
71V67802
,
* Industrial temperature not available on 166MHz devices
5311 drw 13
6.42
22
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
Createddatasheetfrom71V676and71V678datasheets.
I/Ovoltage andspeedgrade offerings have beensplitintoseparate partnumbers.
Seethefollowingdatasheetsfor:
3.3VI/O, 133–166MHz
2.5VI/O, 133–166MHz
3.3VI/O, 183–200MHz
2.5VI/O, 183–200MHz
71V67603
71V67602
71V67613
71V67612
04/26/00
05/24/00
Pg. 4
AddcapacitanceforBGApackage;InsertclarificationnotetoAbsoluteMaxRatingsandRecommended
OperatingTemperaturetables.
Replace PinU6withTRST pininBGApinconfiguration;Addpindescriptionnote inpinout
Inserted100pinTQFPPackageDiagramOutline
Pg. 7
Pg. 18
Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correctnote 2on BGA and TQFP pinconfiguration
Pg. 20
Pg. 5,6,8
Pg. 7
Correctioninthe119BGAPackageDiagramOutline
RemovenotefromTQFPandBQ165pinouts
Remove/AddreferencenotefromBG119pinout
UpdateBG119PackageDiagramOutline
07/12/00
08/27/02
Pg. 20
Pg. 4,9,12 AddedIndustrialinformationtothedatasheet.
22
10/28/02
11/19/02
04/15/03
12/20/03
Pg. 1-23
ChangeddatasheetfromAdvancedInformationtoFinalRelease.
Pg.1,9,12,22Added166MHztodatasheet.
Pg .4
Pg. 7
Updated165fBGAtablefromTBDto7.
Updated 119BGA pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7,
H6, G7, F6,E7, D6 (256K x 18).
Removed "IDT" from the orderable part number.
02/27/09 Pg. 22
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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