71V6770385BQGI8 [IDT]
3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect;
| 型号： | 71V6770385BQGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect 静态存储器 |
| 文件： | 总20页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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◆
◆
◆
◆
256K X 36, 512K X 18
3.3VSynchronousSRAMs
IDT71V67703
IDT71V67903
3.3V I/O, Burst Counter
Flow-ThroughOutputs,SingleCycleDeselect
Features
256K x 36, 512K x 18 memory configurations
Supports fast access times:
◆
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array (fBGA)
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
◆
LBO input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
Green parts available see ordering information
Functional Block Diagram
LBO
ADV
INTERNAL
ADDRESS
CEN
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
18/19
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2 - A18
ADDRESS
REGISTER
A0–A
17/18
36/18
36/18
18/19
GW
BWE
Byte 1
Write Register
Byte 1
Write Driver
BW
1
9
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
9
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
CE
Q
D
CS0
Enable
Register
CLK EN
DATA INPUT
REGISTER
CS
1
ZZ
Powerdown
OE
OUTPUT
BUFFER
OE
,
36/18
I/O0
I/OP1–I/OP4
–I/O31
5309 drw 01
DECEMBER 2014
1
©2014 Integrated Device Technology, Inc.
DSC-5309/06
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Description
initiating the access sequence. The first cycle of output data will flow-
through from the array after a clock-to-data access time delay from the
risingclockedgeofthesamecycle. Ifburstmodeoperationisselected
(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbeavailable
totheuseronthenextthreerisingclockedges. Theorderofthesethree
addressesaredefinedbytheinternalburstcounterandtheLBOinputpin.
TheIDT71V67703/7903SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
TheIDT71V67703/7903arehigh-speedSRAMsorganizedas256K
x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write, data,
addressandcontrolregisters. Therearenoregistersinthedataoutput
path (flow-through architecture). Internal logic allows the SRAM to
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil
theendofthewritecycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V67703/7903canprovidefourcyclesof
data for a single address presented to the SRAM. An internal burst
address counter accepts the first cycle address from the processor,
Pin Description Summary
A
0
-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS
0, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
BWE
BW , BW2, BW3 4
, BW (1)
1
CLK
Clock
Input
Input
Input
Input
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O
0-I/O31, I/OP1-I/OP4
Data Input / Output
V
V
DD, VDDQ
SS
Core Power, I/O Power
Ground
Supply
Supply
N/A
5309 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67903.
6.422
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A
0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSC
ADSP
ADV
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
BWE
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW
Any active byte write causes all outputs to be disabled.
1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
BW1-BW4
Chip Enable
Synchronous chip enable. CE is used with CS
CE also gates ADSP.
0 and CS1 to enable the IDT71V67703/7903.
CE
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
CS
CS
GW
0
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
0
is used with CE and CS
1
to enable the chip.
1
is used with CE and CS
0 to enable the chip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by
the rising edge of CLK. The data output path is flow-through (no output register).
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
1
N/A
N/A
3.3V core power supply.
V
3.3V I/O Supply.
V
N/A
Ground.
NC
ZZ
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down
the IDT71V67703/7903 to its lowest power consump tion level. Data retention is guaranteed
in Sleep Mode.
5309 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature Supply Voltage
Symbol
Rating
Commercial
Unit
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
V
DD
VDDQ
(2 )
Grade
Commercial
Industrial
V
V
V
V
TE RM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
0V
0V
3.3V 5%
3.3V 5%
3.3V 5%
(3,6)
(4,6)
(5,6)
TE RM
TE RM
TE RM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
3.3V 5%
5309 tbl 04
Terminal Voltage with
Respect to GND
V
NOTE:
1. TA is the "instant on" case temperature.
Terminal Voltage with
Respect to GND
V
Recommended DC Operating
Conditions
oC
oC
oC
W
T
A(7)
Operating Temperature
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min. Typ.
3.135 3.3
3.135 3.3
Max.
Unit
Temperature
Under Bias
-55 to +125
TBIAS
V
DD
DDQ
SS
3.465
3.465
0
V
V
V
V
V
V
TSTG
Storage
Temperature
-55 to +125
V
0
0
____
P
T
Power Dissipation
DC Output Current
2.0
50
V
IH
IH
IL
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
V
DD +0.3
____
____
IOUT
mA
V
2.0
V
DDQ +0.3
0.8
5309 tbl 03
V
-0.3(1)
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
5309 tbl 05
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
165 fBGA Capacitance
(TA = +25° C, f = 1.0MHz)
100-Pin TQFP Capacitance
(TA = +25° C, f = 1.0MHz)
Parameter(1 )
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
CIN
V
7
7
pF
CIN
V
5
7
pF
CI/O
V
pF
CI/O
V
pF
5309 tbl 07b
5309 tbl 07
119 BGA Capacitance
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
5309 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP2
I/O15
I/O14
I/OP3
I/O16
I/O17
2
3
4
VDDQ
VDDQ
5
V
SS
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
I/O
I/O
I/O22
9
8
I/O23
(1)
V
SS
VSS
NC
VDD
VDD
NC
ZZ(2)
I/O
I/O
VSS
I/O24
I/O25
7
6
VDDQ
VDDQ
VSS
VSS
,
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
1
0
I/OP1
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5309 drw 02a
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
A
10
NC
2
NC
NC
NC
NC
3
78
77
4
V
DDQ
V
V
DDQ
SS
5
VSS
76
75
74
73
6
NC
NC
NC
I/OP1
7
8
I/O
I/O
8
9
I/O
I/O
7
6
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
V
V
SS
V
DDQ
DDQ
69
68
67
66
I/O10
I/O
I/O
5
4
I/O11
(1)
V
SS
VSS
VDD
NC
V
ZZ(2)
65
64
NC
DD
VSS
63
62
61
60
59
58
57
56
55
54
53
I/O12
I/O13
I/O
3
I/O
2
V
DDQ
V
V
I/O
DDQ
SS
VSS
I/O14
I/O15
I/OP2
NC
1
0
I/O
NC
NC
VSS
V
V
SS
V
DDQ
NC
NC
NC
DDQ
NC
NC
NC
,
52
51
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5309 drw 02b
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
(4)
3
2
9
A17
CS
NC
NC
NC
NC
0
7
DD
V
12
A
15
A
A
16
I/O
P3
18
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
I/O
V
V
V
NC
CE
V
V
V
17
I/O
13
I/O
14
I/O
I/O
DDQ
V
19
I/O
12
I/O
DDQ
V
OE
20
22
21
3
2
11
10
I/O
I/O
I/O
I/O
I/O
G
H
J
BW
ADV
GW
BW
23
I/O
SS
V
SS
V
9
I/O
8
I/O
DDQ
DD
DD
V
DD
6
DDQ
V
NC
V
V
NC
V
24
26
I/O
SS
V
SS
V
7
I/O
K
L
I/O
I/O
CLK
NC
I/O
25
27
I/O
4
1
BW
4
I/O
5
I/O
BW
DDQ
29
28
SS
V
SS
V
3
DDQ
1
M
N
P
R
T
V
I/O
I/O
V
BWE
30
I/O
SS
V
1
A
SS
V
2
I/O
I/O
I/O
I/O
I/O
31
P4
SS
V
0
A
SS
V
0
P1
I/O
I/O
(1)
SS
V
5
DD
11
13
NC
A
V
A
NC
LBO
(2)
10
A
14
A
NC
NC
A
NC
ZZ
DNU(3)
DNU(3)
DNU(3)
U
DNU(3)
DNU(3)
DDQ
V
DDQ
V
5309 drw 02c
Top View
Pin Configuration – 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
ADSP
ADSC
(4)
3
2
9
A18
NC
NC
CS
NC
NC
NC
0
7
DD
V
13
A
17
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
SS
P1
NC
V
V
V
NC
CE
V
V
V
V
V
I/O
NC
9
I/O
7
I/O
NC
DDQ
V
6
I/O
DDQ
V
NC
OE
10
I/O
2
5
I/O
G
H
J
NC
NC
BW
ADV
GW
11
I/O
SS
4
I/O
NC
V
NC
DDQ
V
DD
DD
V
DD
V
DDQ
V
V
NC
SS
NC
12
SS
SS
3
I/O
K
L
NC
I/O
NC
V
V
CLK
NC
V
NC
13
I/O
1
2
I/O
NC
BW
DDQ
14
SS
SS
SS
SS
V
DDQ
V
M
N
P
R
T
V
I/O
NC
V
V
V
NC
BWE
15
I/O
1
A
SS
V
1
I/O
NC
P2
0
A
SS
V
0
I/O
NC
I/O
NC
(1)
5
DD
V
SS
14
12
A
NC
NC
A
V
A
NC
LBO
(2)
10
15
A
11
A
A
NC
ZZ
DNU(3)
DDQ
V
U
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DDQ
V
5309 drw 02d
,
Top View
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M devices CS0 will be removed, B2 will be used for address expansion.
6.42
7
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC(3)
NC
A
7
6
A
A
8
9
NC
CE
BW
3
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
A
CS
0
CLK
NC(3)
I/OP2
I/O14
I/O12
I/O10
BW4
BW
1
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/O16
I/O18
I/O20
I/O22
NC
V
V
V
V
I/O15
I/O13
I/O11
G
H
J
I/O
9
I/O8
(2)
V
SS(1)
NC
NC
NC
ZZ
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
DDQ
DDQ
DDQ
DDQ
DDQ
I/O
7
I/O
I/O
I/O
I/O
6
K
L
V
V
V
V
V
V
V
V
I/O
5
4
I/O
3
2
M
N
P
R
I/O
1
0
NC
NC(3)
NC
NC
I/OP1
NC(3)
NC(3)
A
A
5
4
A
2
3
DNU(4)
DNU(4)
A
1
DNU(4)
DNU(4)
A
10
11
A
13
12
A
14
15
A
A
17
16
A
A
0
A
A
A
LBO
5309tbl 17a
Pin Configuration – 512K x 18, 165 fBGA
1
NC(3)
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
A
7
6
NC
A
A
8
9
A10
CE
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
A
CS
0
NC
CLK
NC(3)
I/OP1
BW1
ADSP
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/O
I/O
8
V
V
V
V
I/O
I/O
I/O
I/O
7
6
5
4
9
I/O10
I/O11
NC
G
H
J
(2)
V
SS(1)
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
NC
NC
ZZ
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
DDQ
DDQ
DDQ
DDQ
DDQ
I/O3
NC
NC
NC
NC
NC
K
L
NC
V
V
V
V
V
V
V
V
I/O2
NC
I/O
1
M
N
P
R
NC
I/O0
NC
NC
NC(3)
NC
NC
NC(3)
NC(3)
A
A
5
4
A
2
3
DNU(4)
DNU(4)
A
1
DNU(4)
DNU(4)
A
11
A
14
13
A
15
16
A
A
18
17
A
A
0
A
12
A
A
LBO
5309 tbl 17b
NOTES:
1. H1 does not have to be directly connected to VSS, as long as the input voltage is < VIL.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
6.482
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
V
DD = Max., VIN = 0V to VDD
5
µA
LBO Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
___
___
___
|ILI
|
V
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VCC
30
5
µA
µA
V
|ILO
|
V
OL
OH
IOL = +8mA, VDD = Min.
0.4
___
V
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
V
5309 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
7.5ns
8ns
Com'l
8.5ns
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind
285
70
Ind
230
70
Ind
210
70
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VIH or < VIL, f = fMAX
mA
IDD
(2)
V
265
50
210
50
190
50
ISB1
CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
mA
mA
V
I
SB2
Clock Running Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
(2,.3)
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
145
50
165
70
140
50
160
70
135
50
155
70
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, DD = Max.
V
mA
5309 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
(VDDQ = 3.3V/2.5V)
AC Test Load
V
DDQ/2
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
5309 drw 03
1.5V
6
5
4
3
See Figure 1
Figure 1. AC Test Load
5309 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
,
5309 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1,3)
CE
CS
1
ADSP ADSC ADV
GW
BWE
BWx OE(2)
Operation
Address
Used
CS
0
CLK
I/O
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
HI-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
D
IN
IN
IN
IN
5309 tbl 11
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
6.1402
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
(1, 2)
Synchronous Write Function Truth Table
Operation
GW
BWE
BW
1
BW
X
2
BW
X
3
BW
X
4
Read
H
H
L
X
L
L
L
L
L
X
Read
H
H
X
H
X
H
X
H
X
Write all Bytes
Write all Bytes
Write Byte 1(3)
Write Byte 2(3)
Write Byte 3(3)
Write Byte 4(3)
L
H
L
L
L
L
H
L
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
5309 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67903.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table (1)
Operation(2)
ZZ
I/O Status
Power
OE
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5309 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5309 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5309 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock Parameter
____
____
____
____
____
____
t
CY C
Clock Cycle Time
8.5
3
10
4
11.5
4.5
ns
ns
ns
(1)
CH
Clock High Pulse Width
Clock Low Pulse Width
t
____
____
____
(1)
CL
3
4
4.5
t
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
2
0
2
0
2
0
(2)
CLZ
____
____
____
t
(2 )
Clock High to Data High-Z
2
3.5
2
3.5
2
3.5
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Output Active
3.5
3.5
3.5
____
____
____
(2)
(2)
0
0
0
t
OL Z
____
____
____
Output Enable High to Output High-Z
3.5
3.5
3.5
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
____
____
____
t
ZZP W
ZZR(3)
CFG (4)
ZZ Pulse Width
100
100
34
100
100
40
100
100
50
ns
ns
t
ZZ Recovery Time
Configuration Set-up Time
t
ns
5309 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured 200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.1422
tCYC
CLK
tCL
tSS
tHS
tCH
ADSP
(1)
ADSC
tSA
tHA
Ay
ADDRESS
Ax
tSW
tHW
GW, BWE, BWx
tSC
tHC
CE, CS
1
(Note 3)
tSAV
tHAV
ADV
OE
tOE
ADV HIGH suspends burst
tCD
tOHZ
tCDC
(Burst wraps around
to its initial state)
tCHZ
tOLZ
O1(Ay)
O2(Ay)
O1(Ay)
O2(Ay)
O1(Ax)
O4(Ay)
DATAOUT
O3(Ay)
Output
Disabled
Burst Flow-through Read
Flow-through
Read
5309 drw 06
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCYC
CLK
t
SS
tHS
t
CH
t
CL
(2)
ADSP
t
SA
tHA
Ax
Az
Ay
ADDRESS
GW
t
SW
t
HW
ADV
OE
tSD
t
HD
t
OE
tCD
t
OLZ
I1(Ay)
DATAIN
t
CLZ
t
OHZ
t
CDC
DATAOUT
O1(Az)
O2(Az)
O4(Az)
O1(Ax)
O3(Az)
t
CD
Flow-through Burst Read
Single Read
Write
5309 drw 07
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
tCYC
CLK
ADSP
t
SS
tCL
tCH
t
HS
(1)
ADSC
tSA
tHA
ADDRESS
Az
Ay
Ax
tHW
SW
GW is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
t
GW
t
SC tHC
CE, CS
1
(Note 3)
tHAV
tSAV
ADV
(ADV suspends burst)
OE
tHD
tSD
I2(Ay)(2)
I3(Ay)
DATAIN
I3(Az)
I2(Az)
I1(Az)
I1(Ay)
I4(Ay)
I1(Ax)
I2(Ay)
tOHZ
DATAOUT
O3(Aw)
O4(Aw)
5309 drw 08
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
t
CYC
CLK
ADSP
t
SS
tCL
tCH
t
HS
ADSC
tSA
tHA
Ay
Ax
Az
t
ADDRESS
BWE
t
HW
SW
BWE is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tHW
SW
BWx is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
t
BWx
tSC
tHC
CE, CS
1
(Note 3)
tSAV
ADV
(ADV HIGH suspends burst)
OE
DATAIN
tHD
t
SD
I3(Ay)
I1(Ay)
I2(Az)
I3(Az)
I2(Ay)
I1(Ax)
I4(Ay)
I2(Ay)
I1(Az)
tOHZ
DATAOUT
O3(Aw)
O4(Aw)
Burst
Read
Extended
Burst Write
Single
Write
Burst Write
5309 drw 09
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address
Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCYC
CLK
tCL
tCH
tSS
tHS
ADSP
ADSC
tSA
tHA
ADDRESS
Az
Ax
GW
tSC
tHC
CE, CS
1
(Note 4)
ADV
tOE
OE
tOLZ
O1(Ax)
DATAOUT
ZZ
tZZR
tZZPW
Snooze Mode
Single Read
5309 drw 13
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5309 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS
1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5309 drw 11
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.1482
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
X
XXXX
S
XX
X
X
X
Process/
Temperature
Range
Device
Type
Power Speed
Package
Blank
8
Tube or Tray
Tape and Reel
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
G
Green
PF
BG
BQ
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine pitch Ball Grid Array (fBGA)
75
80
85
Access Time in Tenths of Nanoseconds
256K x 36 Flow-Through Burst Synchronous SRAM
,
512K x 18 Flow-Through Burst Synchronous SRAM
71V67703
71V67903
5309 drw 12
6.42
19
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
04/26/00
CreatedDatasheetfrom71V677and71V679Datasheets
For 2.5V I/O offering, see 71V67702 AND 71V67902 Datasheets.
AddcapacitanceforBGApackage;InsertclarificationnotetoAbsoluteMaxRatingsandRecommended
OperatingTemperaturetables.
Pg. 4
Pg. 7
Pg. 18
Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout
Inserted100pinTQFPPackageDiagramOutline
05/24/00
07/12/00
Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correct note 2 on BGA and TQFP pin configuration
Pg. 20
Pg. 5,6,8
Pg. 7
Pg. 20
Pg. 9
Correctioninthe119BGAPackageDiagramOutline
RemovenotefromTQFPandBQ165pinouts
Add/RemovenotefromBG119pinout
UpdateBG119pinout
12/18/00
10/29/01
Updated ISB2 levels for 7.5-8.5ns.
Pg. 1,2
Pg. 7
RemoveJTAGpins
Changed U2-U6 pins to DNU.
Pg. 8
Pg. 9
Pg. 1-23
Changed P5,P7,R5 & R7 to DNU pins.
Raised specs by 10mA on 7.5ns, 8ns and 8.5ns.
ChangeddatasheetfromAdvancedtoFinalRelease.
10/22/02
Pg. 4,9,12, AddedItemptodatasheet.
22
04/15/03
12/20/03
Pg. 4
Pg. 7
Updated165fBGAtablefromTBDto7.
Updated 119BGS pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7,
H6, G7, F6, E7, D6 (256K x 18).
02/20/09
11/19/14
Pg.22
Removed "IDT" from the orderable part number
Pg.1 & 20 AddedgreenpartsavailablenotetoFeatures&toOrderingInformation
Pg. 1-3
Moved the FBD, the pin description and pin definition tables to pages 1 - 3 respectively to
alignthedatasheetreadingflowtothatofourotherestablisheddatasheets
Added tape & reel to ordering information
Pg. 20
Pg. 19-21 Removed three Package Diagrm Outlines. from this datasheet. Please see idt.com for Package Diagrm
Outlinesspecifictothesedevices.
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6.2402
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