72210L25TPG [IDT]
FIFO, 512X8, 15ns, Synchronous, CMOS, PDIP28, 0.300 INCH, GREEN, THIN, PLASTIC, DIP-28;
| 型号： | 72210L25TPG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 512X8, 15ns, Synchronous, CMOS, PDIP28, 0.300 INCH, GREEN, THIN, PLASTIC, DIP-28 时钟 先进先出芯片 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
CMOS SyncFIFO™
64 x 8, 256 x 8,
512 x 8, 1,024 x 8,
2,048 x 8 and 4,096 x 8
FEATURES:
DESCRIPTION:
• 64 x 8-bit organization (IDT72420)
TheIDT72420/72200/72210/72220/72230/72240SyncFIFO™arevery
high-speed,low-powerFirst-In,First-Out(FIFO)memorieswithclocked read
andwritecontrols.Thesedeviceshavea64,256,512,1,024,2,048,and4,096
x 8-bit memory array, respectively. These FIFOs are applicable for a wide
varietyofdatabufferingneeds,suchasgraphics,LocalAreaNetworks(LANs),
andinterprocessorcommunication.
• 256 x 8-bit organization (IDT72200)
• 512 x 8-bit organization (IDT72210)
• 1,024 x 8-bit organization (IDT72220)
• 2,048 x 8-bit organization (IDT72230)
• 4,096 x 8-bit organization (IDT72240)
• 10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/
72240)
• Read and Write Clocks can be asynchronous or coincidental
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,
respectively
• Output enable puts output data bus in high-impedance state
• Produced with advanced submicron CMOS technology
• Available in 28-pin 300 mil plastic DIP
• For surface mount product please see the IDT72421/72201/72211/ forimprovedsystemcontrol.Thepartial(AE)flagsaresettoEmpty+7andFull-
72221/72231/72241 data sheet
TheseFIFOshave8-bitinputandoutputports.Theinputportiscontrolled
byafree-runningclock(WCLK),andaWriteEnablepin(WEN). Dataiswritten
intotheSynchronousFIFOoneveryclockwhenWENisasserted.Theoutput
portiscontrolledbyanotherclockpin(RCLK)andaReadEnablepin(REN).
TheReadClockcanbetiedtotheWriteClockforsingleclockoperationorthe
twoclockscanrunasynchronousofoneanotherfordualclockoperation.An
OutputEnablepin(OE)isprovidedonthereadportforthree-statecontrolof
theoutput.
These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full
(FF).Twopartialflags,Almost-Empty(AE)andAlmost-Full(AF),areprovided
7 for AE and AF respectively.
TheseFIFOsarefabricatedusinghigh-speedsubmicronCMOStechnol-
ogy.
• Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
D0 - D7
WCLK
WEN
INPUT REGISTER
EF
AE
AF
FF
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 8, 256 x 8,
512 x 8, 1,024 x 8,
2,048 x 8, 4,096 x 8
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
RS
REN
OE
2680 drw01
Q0 - Q7
CIDTO,IDTMlogMoarEereRgisCtereIdAtraLdemaTrksEofIMntegPratEedDRevAiceTTeUchnRologEy,IncR.ThAeSNyncGFIFEOisatrademarkofIntegratedDeviceTechnology,Inc.
JULY 2013
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2680/6
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
PIN CONFIGURATION
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D4
D3
D5
2
D6
3
D2
D7
4
RS
D1
WEN
WCLK
VCC
Q7
5
D0
AF
6
AE
7
GND
RCLK
REN
OE
8
Q6
9
Q5
10
11
12
13
14
Q4
EF
Q3
FF
Q2
Q0
Q1
2680 drw02
PLASTIC THIN DIP (P28-2, order code: TP)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
Data Inputs
I/O
Description
D0 - D7
I
Data inputs for a 8-bit bus.
RS
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go
HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
Write Clock
I
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written
into the FIFO if the FF is LOW.
WEN
Write Enable
Q0 - Q7
RCLK
REN
Data Outputs
Read Clock
Read Enable
O
I
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from
the FIFO if the EF is LOW.
I
OE
EF
Output Enable
Empty Flag
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO
is not empty. EF is synchronized to RCLK.
AE
AF
FF
Almost-Empty Flag
Almost-Full Flag
Full Flag
O
O
O
When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK.
When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not
full. FF is synchronized to WCLK.
VCC
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
2
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
Symbol
Rating
Com'l & Ind'l
Unit
V
CONDITIONS
VTERM
TerminalVoltagewith
RespecttoGND
–0.5 to +7.0
Symbol
Parameter
Min. Typ. Max.
Unit
VCC
SupplyVoltage
Commercial
4.5
5.0
5.5
V
TSTG
StorageTemperature
–55 to +125
–50 to +50
°C
GND
VIH
SupplyVoltage
InputHighVoltage
Commercial
0
2.0
0
—
0
—
V
V
IOUT
DCOutputCurrent
mA
NOTE:
VIL
TA
InputLowVoltage
Commercial
OperatingTemperature
Commercial
—
0
—
—
0.8
70
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
Commercial
tCLK = 10, 15, 25 ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
ILI(1)
Input Leakage Current (any input)
OutputLeakageCurrent
–1
–10
2.4
—
—
—
—
—
—
—
1
μA
μA
V
ILO(2)
10
—
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
VOL
0.4
40
5
V
ICC1(3,4,5)
—
mA
mA
ICC2(3,6)
—
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 1.7 + 0.7*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
3
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C)
Commercial
IDT72420L10
IDT72420L15
IDT72200L15
IDT72210L15
IDT72220L15
IDT72230L15
IDT72240L15
IDT72420L25
IDT72200L25
IDT72210L25
IDT72220L25
IDT72230L25
IDT72240L25
IDT72200L10
IDT72210L10
IDT72220L10
IDT72230L10
IDT72240L10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
—
2
100
—
2
66.7
—
2
40
MHz
tA
DataAccessTime
6.5
—
—
—
—
—
—
—
—
—
—
10
—
6
10
—
—
—
—
—
—
—
—
—
—
15
—
8
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
25
10
10
6
Clock High Time
Clock Low Time
6
DataSetupTime
4
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tRS
EnableSetupTime
4
6
EnableHoldTime
ResetPulseWidth(1)
0.5
10
8
1
1
15
10
10
—
0
15
15
15
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
OutputEnabletoOutputinLow-Z(2)
OutputEnabletoOutputValid
OutputEnabletoOutputinHigh-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
WriteClocktoAlmost-FullFlag
Read Clock to Almost-Empty Flag
8
—
0
2
3
3
tOHZ
tWFF
tREF
tAF
2
6
3
8
3
—
—
—
—
4
6.5
6.5
6.5
6.5
—
—
—
—
—
6
10
10
10
10
—
—
—
—
—
10
tAE
tSKEW1
Skew time between Read Clock & Write Clock for
Empty Flag & Full Flag
tSKEW2
Skew time between Read Clock & Write Clock for
Almost-Empty Flag & Almost-Full Flag
10
—
15
—
18
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
CAPACITANCE(TA = +25°C, f = 1.0 MHz)
5V
Symbol
Parameter
Conditions
VIN = 0V
Max.
10
Unit
pF
(2)
CIN
Input Capacitance
Output Capacitance
1.1KΩ
(1, 2)
COUT
VOUT = 0V
10
pF
NOTES:
D.U.T.
1. With output deselected. (OE ≥ VIH)
2. Characterized values, not currently tested.
30pF*
680Ω
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
2680 drw03
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
or equivalent circuit
1.5V
Figure 1. Output Load
*Includes jig and scope capacitances.
See Figure 1
4
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid
read can begin. Read Enable (REN) is ignored when the FIFO is empty.
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D0–D7) — Data inputs for 8-bit wide data.
OUTPUT ENABLE (OE) — When Output Enable (OE) is enabled (LOW),
the parallel output buffers receive data from the output register. When
Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-
impedance state.
CONTROLS:
RESET (RS) — Reset is accomplished whenever the Reset (RS) input is
takentoaLOWstate. Duringreset, bothinternalreadandwritepointersare
set to the first location. A reset is required after power up before a write
operation can take place. The Full Flag (FF) and Almost-Full Flag (AF) will
be reset to HIGH after tRSF. The Empty Flag (EF) and Almost-Empty Flag
(AE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros.
OUTPUTS:
FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibiting further write
operation, when the device is full. If no reads are performed after Reset
(RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256
writes for the IDT72200, 512 writes for the IDT72210, 1,024 writes for the
IDT72220,2,048writesfortheIDT72230,and4,096writesfortheIDT72240.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
WRITE CLOCK (WCLK) — A write cycle is initiated on the LOW-to-HIGH
transitionoftheWriteClock(WCLK).Datasetupandholdtimesmustbemet
in respect to the LOW-to-HIGH transition of the Write Clock. The Full Flag
(FF) and Almost-Full Flag (AF) are synchronized with respect to the LOW-
to-HIGH transition of the Write Clock.
The Write and Read Clocks can be asynchronous or coincident.
EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer,
indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
WRITE ENABLE (WEN) — When Write Enable (WEN) is LOW, data can
be loaded into the input register and RAM array on the LOW-to-HIGH
transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
WhenWriteEnable(WEN)isHIGH, theinputregisterholdstheprevious
data and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle, the Full
Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write
Enable (WEN) is ignored when the FIFO is full.
ALMOST-FULLFLAG(AF)—TheAlmost-FullFlag(AF)willgoLOWwhen
the FIFO reaches the almost-full condition. If no reads are performed after
Reset (RS), the Almost-Full Flag (AF) will go LOW after 57 writes for the
IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1,017
writes for the IDT72220, 2,041 writes for the IDT72230 and 4,089 writes for
the IDT72240.
The Almost-Full Flag (AF) is synchronized with respect to the LOW-to-
HIGH transition of the Write Clock (WCLK).
READ CLOCK (RCLK) — Data can be read on the outputs on the LOW-to-
HIGH transition of the Read Clock (RCLK). The Empty Flag (EF) and
Almost-Emptyflag(AE)aresynchronizedwithrespecttotheLOW-to-HIGH
transition of the Read Clock.
ALMOST-EMPTY FLAG (AE) — The Almost-Empty Flag (AE) will go LOW
when the FIFO reaches the almost-empty condition. If no reads are
performed after Reset (RS), the Almost-Empty Flag (AE) will go HIGH after
8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and
IDT72240.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN) — When Read Enable (REN) is LOW, data is read
from the RAM array to the output register on the LOW-to-HIGH transition of
the Read Clock (RCLK).
The Almost-Empty Flag (AE) is synchronized with respect to the LOW-
to-HIGH transition of the Read Clock (RCLK).
When Read Enable (REN) is HIGH, the output register holds the
previous data and no new data is allowed to be loaded into the register.
DATA OUTPUTS (Q0–Q7) — Data outputs for 8-bit wide data.
TABLE 1 — STATUS FLAGS
Number of Words in FIFO
IDT72420
0
IDT72200
0
IDT72210
0
IDT72220
0
IDT72230
0
IDT72240
0
FF
H
H
H
H
L
AF
H
H
H
L
AE
L
EF
L
1 to 7
8 to 56
57 to 63
64
1 to 7
1 to 7
1 to 7
1 to 7
1 to 7
L
H
H
H
H
8 to 248
249 to 255
256
8 to 504
505 to 511
512
8 to 1,016
1,017 to 1,023
1,024
8 to 2,040
2,041 to 2,047
2,048
8 to 4,088
4,089 to 4,095
4,096
H
H
H
L
5
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
tRS
RS
tRSS
tRSR
tRSR
REN
tRSS
WEN
tRSF
EF, AE
tRSF
FF, AF
tRSF
OE = 1(1)
OE = 0
Q0 - Q7
2680 drw 04
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
2. The Clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 - D7
DATA IN VALID
tENH
tENS
NO OPERATION
WEN
FF
t
WFF
tWFF
(1)
tSKEW1
RCLK
2680 drw 05
REN
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
6
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
NO OPERATION
REN
EF
t
REF
t
REF
tA
VALID DATA
Q0 - Q7
tOLZ
tOHZ
tOE
OE
(1)
tSKEW1
WCLK
WEN
2680 drw 06
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
WCLK
tDS
D1
D2
D0 (first valid write)
D3
D0 - D7
tENS
WEN
(1)
FRL
t
tSKEW1
RCLK
t
REF
EF
tENS
REN
tA
tA
D0
D1
Q0 - Q7
tOLZ
tOE
OE
2680 drw 07
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 5. First Data Word Latency Timing
7
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
NO WRITE
WCLK
NO WRITE
NO WRITE
tSKEW1
tSKEW1
tDS
DATA WRITE
D0 - D7
t
WFF
tWFF
t
WFF
FF
tENS
tENS
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
tA
tA
LOW
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q0 - Q7
2680 drw 08
Figure 6. Full Flag Timing
WCLK
tDS
tDS
DATA WRITE 1
DATA WRITE 2
D0 - D7
tENS
tENS
tENH
tENH
WEN
(1)
(1)
tFRL
tFRL
tSKEW1
tSKEW1
RCLK
t
REF
tREF
t
REF
EF
REN
OE
LOW
tA
DATA READ
DATA IN OUTPUT REGISTER
Q0 - Q7
2680 drw 09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 7. Empty Flag Timing
8
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
tCLKH
tCLKL
(2)
WCLK
tENS
tENH
WEN
AF
t
AF
Full - 8 words in FIFO
Full - 7 words in FIFO
(1)
SKEW2
t
t
AF
RCLK
tENH
tENS
2680 drw10
REN
NOTES:
1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the current clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge.
2. If a write is performed on this rising edge of the Write Clock, there will be Full -7 words in the FIFO when AF goes LOW.
Figure 8. Almost Full Flag Timing
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
AE
Empty+8
Empty+7
(1)
tSKEW2
t
AE
t
AE
(2)
RCLK
tENS
tENH
2680 drw 11
REN
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge.
2. If a read is performed on this rising edge of the Read Clock, there will be Empty +7 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
9
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIALTEMPERATURERANGE
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - A single IDT72420/72200/72210/
72220/72230/72240 may be used when the application requirements are
for 64/256/512/1,024/2,048/4,096 words or less. See Figure 10.
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
IDT
72420
72200
72210
72220
72230
72240
DATA IN (D0-
D
7
)
DATA OUT (Q0-Q7)
FULL FLAG (FF)
EMPTY FLAG (EF)
ALMOST-FULL (AF)
ALMOST-EMPTY(AE)
2680 drw 12
Figure 10. Block Diagram of Single 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may be increased any one device. Figure 11 demonstrates a 16-bit word width by using two
simply by connecting the corresponding input control signals of multiple IDT72420/72200/72210/72220/72230/72240s. Any word width can be
devices. A composite flag should be created for each of the endpoint status attainedbyaddingadditional IDT72420/72200/72210/72220/72230/72240s.
flags (EFand FF) Thepartialstatusflags(AEandAF)canbedetectedfrom
RESET (RS)
RESET (RS)
DATA IN (D)
16
8
8
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
ALMOST-EMPTY (AE)
WRITE ENABLE (WEN)
ALMOST-FULL (AF)
IDT
IDT
72420
72200
72210
72220
72230
72240
72420
72200
72210
72220
72230
72240
FULL FLAG (FF) #1
FULL FLAG (FF) #2
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
8
16
8
DATA OUT (Q)
2680 drw13
Figure 11. Block Diagram of 64 x 16, 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, 4,096 x 16
Synchronous FIFO Used in a Width Expansion Configuration
10
DEPTHEXPANSION
Please see the Application Note “DEPTH EXPANSION IDT'S
The IDT72420/72200/72210/72220/72230/72240 can be adapted to SYNCHRONOUSFIFOsUSINGRINGCOUNTERAPPROACH”fordetails
applications when the requirements are for greater than 64/256/512/1,024/ ofthisconfiguration.
2,048/4,096words.Depthexpansionispossiblebyusingexpansionlogicto
direct the flow of data. A typical application would have the expansion logic
alternatedataaccessesfromonedevicetothenextinasequentialmanner.
ORDERING INFORMATION
X
XXXXX
X
XX
XX
X
DeviceType Power Speed Package
Process /
Temperature
Range
BLANK
Commercial (0°C to +70°C)
G
Green
TP
Plastic Thin DIP (300 mil, P28-2)
10
15
25
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commercial
L
Low Power
72420
72200
72210
72220
72230
72240
64x 8 SyncFIFO
256 x 8 SyncFIFO
512 x 8 SyncFIFO
1,024 x 8 SyncFIFO
2,048 x 8 SyncFIFO
4,098 x 8 SyncFIFO
2680 drw14
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEET DOCUMENT HISTORY
10/03/2000
05/01/2001
02/10/2006
01/08/2009
07/25/2013
pgs. 1, 3, 4 and 11.
pgs. 1, 2, 3, 4 and 11.
pgs. 1 and 11.
pg. 11.
pgs. 1, 3, 9 and 10.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
11
相关型号：
©2020 ICPDF网 联系我们和版权申明