723623L12PFG8 [IDT]
CMOS BUS-MATCHING SyncFIFO;
| 型号： | 723623L12PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS BUS-MATCHING SyncFIFO 先进先出芯片 配套器件 |
| 文件： | 总28页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS BUS-MATCHING SyncFIFOTM
256 x 36, 512 x 36, 1,024 x 36
IDT723623
IDT723633
IDT723643
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
FEATURES:
• Memory storage capacity:
IDT723623
IDT723633
IDT723643
–
–
–
256 x 36
512 x 36
1,024 x 36
• Clocked FIFO buffering data from Port A to Port B
• Clock frequencies up to 83 MHz (8 ns access time)
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Green parts available, see ordering information
DESCRIPTION:
TheIDT723623/723633/723643aremonolithic,high-speed,low-power,
CMOSunidirectionalSynchronous(clocked)FIFOmemorieswhichsupport
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
• Big- or Little-Endian format for word and byte bus sizes
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
36
RAM ARRAY
256 x 36
36
36
FIFO1
Mail1,
Mail2,
Reset
Logic
RS1
RS2
PRS
512 x 36
1,024 x 36
36
Write
Pointer
Read
Pointer
A0-A35
B0-B35
Status Flag
Logic
EF/OR
AE
FF/IR
AF
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
Timing
Mode
FWFT
10
CLKB
CSB
W/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
SIZE
Mail 2
Register
3269 drw01
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 2014
1
©
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3269/5
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox
registers.Themailboxregisters'widthmatchestheselectedPortBbuswidth.
Eachmailboxregisterhasaflag(MBF1andMBF2)tosignalwhennewmail
hasbeenstored.
DESCRIPTION(CONTINUED)
The256/512/1,024x36dual-portSRAMFIFObuffersdatafromportAtoport
B.FIFOdataonPortBcanoutputin36-bit,18-bit,or9-bitformatswithachoice
ofBig-orLittle-Endianconfigurations.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
Resetinitializesthereadandwritepointerstothefirstlocationofthememory
arrayandselectsserialflagprogramming,parallelflagprogramming,orone
ofthreepossibledefaultflagoffsetsettings,8,16or64.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
These devices are synchronous (clocked) FIFOs, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
PIN CONFIGURATION
INDEX
1
CLKB
102
W/RA
2
Vcc
101
ENA
3
Vcc
100
CLKA
4
B35
99
GND
5
B34
98
A35
6
B33
97
A34
7
B32
96
A33
8
9
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
B25
B24
BM
A24
A23
BE/FWFT
GND
A22
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
3269 drw02
TQFP (PK128, order code: PF)
TOP VIEW
2
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset remainin theFIFOmemoryachieveapredetermined"almost-emptystate".
is useful since it permits flushing of the FIFO memory without changing any AFindicateswhentheFIFOcontainsmorethanaselectednumberofwords.
configurationsettings.
FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, intoitsarray.EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A readsdatafromitsarray. ProgrammableoffsetsforAEandAFareloaded in
read operation is required to access that word (along with all other words parallelusingPortAorinserialviatheSDinput.TheSerialProgrammingMode
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstword pin(SPM)makesthisselection.Threedefaultoffsetsettingsarealsoprovided.
written to an empty FIFO appears automatically on the outputs, no read TheAEthresholdcanbesetat8,16or64locationsfromtheemptyboundary
operationrequired(Nevertheless,accessingsubsequentwordsdoesneces- andtheAFthresholdcanbesetat8,16or64locationsfromthefullboundary.
sitate a formal read request). The state of the BE/FWFT pin during Reset All these choices are made using the FS0 and FS1 inputs during Reset.
determinesthemodeinuse.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a InFirstWordFallThroughmode,morethanonedevicemaybeconnectedin
combinedFull/InputReadyFlag(FF/IR). TheEFandFFfunctionsareselected seriestocreategreaterworddepths. Theadditionofexternalcomponentsis
in the IDT Standard mode. EF indicates whether or not the FIFO memory is unnecessary.
empty.FFshowswhetherthememoryisfullornot.TheIRandORfunctions
If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill
areselectedintheFirstWordFallThroughmode. IRindicateswhetherornot automatically power down. During the power down state, supply current
theFIFOhasavailablememorylocations.ORshowswhethertheFIFOhasdata consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
availableforreadingornot. Itmarksthepresenceofvaliddataontheoutputs. inputs)willimmediatelytakethedeviceoutofthePowerDownstate.
TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogram-
TheIDT723623/723633/723643arecharacterizedforoperationfrom0°C
mableAlmost-Fullflag(AF). AE indicateswhenaselectednumberofwords to70°C.Theyarefabricatedusinghighspeed,submicronCMOStechnology.
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IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
A0-A35
AE
Name
I/O
I/O
Description
PortAData
36-bitbidirectionaldataportforsideA.
Almost-Empty
Flag (Port B)
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsintheFIFO
islessthanorequaltothevalueintheAlmost-EmptyBoffsetregister,X.
AF
Almost-Full
Flag (Port A)
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsinthe
FIFOislessthanorequaltothevalueintheAlmost-FullAoffsetregister, Y.
B0-B35
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
BE/FWFT Big-Endian/
FirstWord
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case,
depending on the bus size, the most significant byte or word written to Port A is read from Port B first. A
LOWonBEwillselectLittle-Endianoperation. Inthiscase,theleastsignificantbyteorwordwrittentoPortA
isreadfromPortBfirst. AfterMasterReset, thispinselectsthetimingmode. AHIGHon FWFTselectsIDT
Standardmode,aLOWselectsFirstWordFallThroughmode.Oncethetimingmodehasbeenselected,the
levelonFWFTmustbestaticthroughoutdeviceoperation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
arrangementforPortB. ThelevelofBMmustbestaticthroughoutdeviceoperation.
Fall Through
BM(1)
Bus-Match
Select(PortB)
I
CLKA
CLKB
CSA
PortAClock
PortBClock
I
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincidenttoCLKA. EF/ORandAEaresynchronizedtotheLOW-to-HIGHtransitionofCLKB.
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputsareinthehigh-impedancestatewhenCSAisHIGH.
Port A Chip
Select
I
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35
outputsareinthehigh-impedancestatewhenCSBisHIGH.
EF/OR
Empty/Output
Ready Flag
(Port B)
O
This is a dual function pin. In the IDT Standard mode, the EF function is selected. EF indicates whether or
nottheFIFOmemoryisempty. IntheFWFTmode,theORfunctionisselected.ORindicatesthepresenceofvalid
dataontheB0-B35outputs,availableforreading.EF/ORissynchronizedtotheLOW-to-HIGHtransitionofCLKB.
ENA
ENB
FF/IR
Port A Enable
Port B Enable
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
Full/Input
Ready Flag
(Port A)
O
This is a dual function pin. In the IDT Standard mode, the FF function is selected. FF indicates whether or
nottheFIFOmemoryisfull. IntheFWFTmode, theIRfunctionisselected. IRindicateswhetherornotthere
isspaceavailableforwritingtotheFIFOmemory. FF/IRissynchronizedtotheLOW-to-HIGHtransitionof
CLKA.
FS1/SEN FlagOffset
I
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagoffsetregisterprogramming. DuringReset,
FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel
load from Port A, and serial load.
Select1/
SerialEnable,
FS0/SD
FlagOffset
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenablesynchronous
totheLOW-to-HIGHtransitionofCLKA. WhenFS1/SENisLOW, arisingedgeonCLKAloadthebitpresent
on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 16
for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register
MSBandthelastbitwritestorestheX-registerLSB.
Select0/
SerialData
MBA
MBB
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputsareactive, aHIGHlevelonMBBselectsdatafromthemail1registerforoutputandaLOWlevel
selectsFIFOdataforoutput.
MBF1
Mail1Register
Flag
O
MBF1issetLOWbyaLOW-to-HIGH transitionofCLKA that writesdatatothemail1register. Writesto
themail1registerareinhibitedwhileMBF1is LOW. MBF1issetHIGHbyaLOW-to-HIGHtransitionofCLKB
when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Reset (RS1) or Partial
Reset(PRS).
4
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
MBF2
Mail2Register
Flag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.Writestothemail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Reset (RS2) or Partial Reset (PRS).
RS1/RS2 Resets
I
A LOWonbothpins initializestheFIFOreadandwritepointerstothefirstlocationofmemoryandsetsthePortB
outputregistertoallzeroes. ALOW-to-HIGHtransitiononRS1selectstheprogrammingmethod(serialorparallel)
andoneofthreeprogrammableflagdefaultoffsets.ItalsoconfiguresPortBforbussizeandendianarrangement.
FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccurwhileRS1isLOW.
PRS
PartialReset
I
I
ALOWonthispininitializestheFIFOreadandwritepointerstothefirstlocationofmemoryandsetsthePortBoutput
registertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endian arrangement,programming
method(serialorparallel),andprogrammableflagsettingsareallretained.
SIZE(1)
BusSizeSelect
(Port B)
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is
HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement
forPortB. ThelevelofSIZEmustbestaticthroughoutdeviceoperation.
(1)
SPM
SerialProgram-
mingMode
I
I
I
ALOWonthispinselectsserialprogrammingofpartialflagoffsets. AHIGHonthispinselectsparallel
programmingordefaultoffsets(8, 16, or64).
W/RA
W/RB
PortAWrite/
ReadSelect
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition
of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
PortBWrite/
ReadSelect
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition
of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
NOTE:
1. BM, SIZE and SPM are not TTL compatible. These inputs should be tied to VCC or GND.
5
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted) (1)
Symbol
VCC
VI(2)
Rating
Commercial
–0.5to7
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
SupplyVoltageRange
InputVoltageRange
V
VO(2)
OutputVoltageRange
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
mA
mA
mA
mA
°C
IOK
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
ContinuousCurrentThroughVCC or GND
StorageTemperatureRange
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at
these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC
VIH
Parameter
Min.
4.5
2
Typ.
5.0
—
Max.
5.5
—
Unit
V
SupplyVoltage(Commercial)
High-LevelInputVoltage(Commercial)
Low-LevelInputVoltage(Commercial)
High-LevelOutputCurrent(Commercial)
Low-LevelOutputCurrent(Commercial)
OperatingTemperature(Commercial)
V
VIL
—
—
—
0
—
0.8
–4
V
IOH
—
mA
mA
°C
IOL
—
8
TA
—
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURERANGE(Unlessotherwisenoted)
IDT723623
IDT723633
IDT723643
Commerical
tCLK = 12, 15ns
Symbol
VOH
Parameter
OutputLogic"1"Voltage
OutputLogic"0"Voltage
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Test Conditions
IOL = -4 mA
Min.
2.4
—
Typ.(1)
Max.
—
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
—
VOL
IOL = 8 mA
—
0.5
±10
±10
8
V
ILI
VI = VCC or 0
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
—
—
μA
μA
mA
mA
pF
ILO
—
—
ICC2(2)
ICC3(2)
CIN(3)
COUT(3)
Standby Current (with CLKA & CLKB running) VCC = 5.5V,
—
—
StandbyCurrent(noclocksrunning)
InputCapacitance
VCC = 5.5V,
VI = 0,
—
—
1
—
4
—
OutputCapacitance
VO = 0,
f = 1 MHZ
—
8
—
pF
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Characterized valules, not curently tested.
6
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723623/723633/723643 with CLKA
andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected
tonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT723623/723633/723643inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x [ICC(f) + (N x ΔICC x dc)] + Σ(CL x VCC X fo)
where:
N
ΔICC
dc
CL
fo
=
=
=
=
=
number of used outputs = 36-bit (long word), 18-bit (word) or 9-bit (byte) bus size
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4 V
outputcapacitanceload
switchingfrequencyofanoutput
300
250
f
data = 1/2 fS
T
A
= 25°C
C
L
= 0pF
VCC = 5.5V
VCC = 5.0V
200
150
100
VCC = 4.5V
50
0
0
10
20
30
40
50
60
70
80
90
3269 drw 02a
fS ⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723623L12 IDT723623L15
IDT723633L12 IDT723633L15
IDT723643L12 IDT723643L15
Symbol
fS
Parameter
Min. Max.
Min. Max. Unit
Clock Frequency, CLKA or CLKB
—
12
5
83
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
6
66.7 MHz
tCLK
Clock Cycle Time, CLKA or CLKB
—
—
⎯
⎯
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLKH
tCLKL
tDS
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
5
6
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑
Setup Time, ENA and MBA before CLKA↑; ENB and MBB before CLKB↑
3
4
tENS1
tENS2
tRSTS
tFSS
4
4.5
4.5
5
3
(1)
Setup Time, RS1 or PRS LOW before CLKA↑ or CLKB↑
5
Setup Time, FS0 and FS1 before RS1 HIGH
Setup Time, BE/FWFT before RS1 HIGH
7.5
7.5
7.5
3
7.5
7.5
7.5
4
tBES
tSPMS
tSDS
Setup Time, SPM before RS1 HIGH
SetupTime, FS0/SDbeforeCLKA↑
tSENS
tFWS
tDH
SetupTime, FS1/SENbeforeCLKA↑
3
4
Setup Time, FWFT before CLKA↑
0
0
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB,ENB, and MBB after CLKB↑
0.5
0.5
4
1
tENH
tRSTH
tFSH
1
(1)
Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑
4
Hold Time, FS0 and FS1 after RS1 HIGH
Hold Time, BE/FWFT after RS1 HIGH
Hold Time, SPM after RS1 HIGH
2
2
tBEH
2
2
tSPMH
tSDH
2
2
Hold Time, FS0/SD after CLKA↑
0.5
0.5
2
1
tSENH
Hold Time, FS1/SEN HIGH after CLKA↑
1
tSPH
Hold Time, FS1/SEN HIGH after RS1 HIGH
2
tSKEW1(2) Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
tSKEW2(2,3) Skew Time between CLKA↑ and CLKB↑ for AE and AF
5
7.5
12
12
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
8
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723623L12 IDT723623L15
IDT723633L12 IDT723633L15
IDT723643L12 IDT723643L15
Symbol
tA
Parameter
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
Min. Max. Min. Max. Unit
2
2
1
1
1
0
8
8
8
8
8
8
2
2
1
1
1
0
10
8
ns
ns
ns
ns
ns
ns
tWFF
tREF
tPAE
tPAF
tPMF
Propagation Delay Time, CLKA↑ to FF/IR
Propagation Delay Time, CLKB↑to EF/OR
Propagation Delay Time, CLKB↑to AE
Propagation Delay Time, CLKA↑ to AF
8
8
8
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 LOW
or MBF1 HIGH
8
tPMR Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2)
2
2
1
2
8
8
2
2
1
2
12
10
15
10
ns
ns
ns
ns
tMDV
tRSF
tEN
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF HIGH, MBF1 HIGH, and MBF2 HIGH
10
6
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH
toB0-B35Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or
W/RBLOWtoB0-B35athigh-impedance
1
6
1
8
ns
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
A HIGH on the BE/FWFT input when the Reset (RS1) input goes from
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort
Bfirst;theleastsignificantbyte(word)ofthelongwordwrittentoPortAwillbe
readfromPortBlast.
ALOWontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBfirst;the
mostsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom
PortBlast. RefertoFigure2foranillustrationoftheBEfunction.SeeFigure
3(Reset)foranEndianselecttimingdiagram.
SIGNALDESCRIPTION
RESET (RS1/RS2)
Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW
pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the
IDT723623/723633/723643undergoesacompleteresetbytakingitsReset
(RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfourPort
B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A Reset initializes the internal read and write
pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output
Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Fullflag(AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe
parallelmailboxregisterHIGH,andatthesametimetheRS2andMBF2operate
likewise. AfteraReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwo
writeclockcyclestobeginnormaloperation.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputlatchesthevalue
of the Big-Endian (BE) input for determining the order by which bytes are
transferredthroughPortB.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe
values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method (for details see Table 1, Flag Programming, and Almost-Empty and
Almost-Fullflagoffsetprogramming section).TherelevantReset timingdiagram
can be found in Figure 3.
— TIMING MODE SELECTION
AfterReset, theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT)mode. OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT
inputduringthenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectIDT
Standard mode. This mode uses the Empty Flag function (EF) to indicate
whether or not there are any words present in the FIFO memory. It uses the
FullFlagfunction(FF)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
includingthefirst,mustberequestedusingaformalreadoperation.
OncetheReset(RS1)inputisHIGH,aLOWontheBE/FWFTinputduring
thenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectFWFTmode.
ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(B0-B35). ItalsousestheInputReadyfunction
(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
PARTIAL RESET (PRS)
The FIFO memory of the IDT723623/723633/723643 undergoes a
limitedresetbytakingitsassociatedPartialReset(PRS)inputLOWforatleast
fourPortAclock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.
ThePartialResetinput canswitchasynchronouslytotheclocks. APartialReset
initializestheinternalreadandwritepointersandforcestheFull/InputReady
flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost-
Emptyflag(AE)LOW,andtheAlmost-Fullflag(AF)HIGH. APartialResetalso
forcestheMailboxflag(MBF1, MBF2)oftheparallelmailboxregisterHIGH.
AfteraPartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoclock
cycles to begin normal operation. See Figure 4, Partial Reset (IDTStandard
and FWFT Modes) for the relevant timing diagram.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedat thetimeaPartial
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Reset would be inconvenient.
Following Reset, thelevelappliedtotheBE/FWFTinputtochoosethe
desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto
Figure 3 (Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Two registers in the IDT723623/723633/723643 are used to hold the
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag
(AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled
Y.Theoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofthe
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmedinserialusingtheSerialData(SD)input(seeTable1).SPM,FS0/
SD and FS1/SEN function the same way in both IDT Standard and FWFT
modes.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,theSerialProgramMode
(SPM)andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-
to-HIGHtransitionoftheResetinput(RS1). Forexample, toloadthepreset
valueof64intoXandY,SPM,FS0andFS1mustbeHIGHwhenRS1returns
HIGH. For the relevant preset value loading timing diagram, see Figure 3.
— ENDIAN SELECTION
Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionis
active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread
fromPortB. Thisselectiondeterminestheorderbywhichbytes(orwords)of
dataaretransferredthroughthisport. Forthefollowingillustrations,assumethat
a byte (or word) bus size has been selected for Port B. (Note that when Port
Bisconfiguredforalongwordsize,theBig-Endianfunctionhasnoapplication
and the BE input is a “don’t care”1.)
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
10
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
TABLE 1 — FLAG PROGRAMMING
SPM
H
H
H
H
L
FS1/SEN
FSO/SD
RS1
↑
X AND Y REGlSTERS(1)
H
H
L
H
L
64
↑
16
H
L
↑
8
ParallelprogrammingviaPortA
SerialProgrammingviaSD
reserved
L
↑
H
H
L
L
↑
L
H
H
L
↑
L
↑
reserved
L
L
↑
reserved
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
1to252fortheIDT723623;1to508fortheIDT723633;and1to1,020forthe
IDT723643. AfteralltheoffsetregistersareprogrammedfromPortAtheFIFO
beginsnormaloperation.
— PARALLEL LOAD FROM PORT A
To program the X and Y registers from Port A, perform a Reset on with
SPMHIGHandFS0andFS1LOWduringtheLOW-to-HIGHtransitionofRS1.
Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredatain
RAM. ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X. On
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timingdiagram.ThePortAdatainputsusedbytheoffsetregistersare(A7-A0),
(A8-A0), or (A9-A0) for the IDT723623, IDT723633 or IDT723643, respec-
tively. Thehighestnumberedinputisusedasthemostsignificantbitofthebinary
numberineachcase. Validprogrammingvaluesfortheregistersrangefrom
— SERIAL LOAD
ToprogramtheXandYregistersserially,initiateaResetwithSPMLOW,
FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the X and Y register values are loaded bit-wise
throughtheFS0/SDinputoneachLOW-to-HIGHtransitionofCLKAthatthe
FS1/SEN input is LOW. There are 16-, 18- or 20-bit writes are needed to
complete the programming for the IDT723623, IDT723633, or IDT723643,
respectively. ThetworegistersarewrittenintheorderY,X.Eachregistervalue
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
PORT FUNCTION
X
H
H
H
L
X
X
X
X
↑
↑
X
↑
X
↑
None
L
X
None
L
H
L
Input
FIFO write
L
H
H
Input
Mail1write
L
L
L
Output
None
L
L
H
L
Output
None
None
L
L
L
H
Output
L
L
H
H
Output
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
X
MBB
X
CLKB
Data B (B0-B35) I/O
PORT FUNCTION
X
L
X
X
↑
↑
X
↑
X
↑
High-Impedance
Input
None
L
X
None
L
L
H
L
Input
None
Mail2write
L
L
H
H
Input
L
H
H
H
H
L
L
Output
None
L
H
L
Output
FIFO read
L
L
H
Output
None
L
H
H
Output
Mail1 read (set MBF1 HIGH)
11
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
clockedtotheoutputregisteronlywhenareadisselectedusingtheport’sChip
Select, Write/Read select, Enable, and Mailbox select. Port A Write timing
diagram can be found in Figure 7. Relevant port B Read timing diagrams
togetherwithBus-MatchingandEndianselectcanbefoundinFigure8,9and
10.
canbeprogrammedfrom1to508(IDT723623), 1to1,020(IDT723633), or
1 to 2,044 (IDT723643).
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
InputReady(FF/IR)flagremainsLOWuntilallregisterbitsarewritten.FF/IR
issetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded
toallownormalFIFOoperation.
SYNCHRONIZED FIFO FLAGS
SeeFigure6,SerialProgrammingoftheAlmost-FullFlagandAlmost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop
stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronizedtoCLKB.Table4 shows therelationshipofeachportflagtothe
number ofwordsstoredinmemory.
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(CSA)andPortAWrite/ReadSelect(W/RA). TheA0-A35linesareintheHigh-
impedancestatewheneitherCSAorW/RAisHIGH. TheA0-A35linesareactive
outputs when bothCSA and W/RAareLOW.
DataisloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGH
transitionofCLKAwhenCSAisLOW, W/RAisHIGH,ENAisHIGH,MBAis
LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
EMPTY/OUTPUTREADYFLAGS(EF/OR)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(OR)
functionisselected. WhentheOutput-ReadyflagisHIGH,newdataispresent
intheFIFOoutputregister. WhentheOutputReadyflagisLOW,theprevious
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare
ignored.
IntheIDTStandardmode,theEmptyFlag(EF)functionisselected. When
theEmptyFlagisHIGH,dataisavailableintheFIFO’smemoryforreadingto
theoutputregister. WhentheEmptyFlagisLOW, thepreviousdatawordis
present in the FIFO output register and attempted FIFO reads are ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock
thatreadsdatafromitsarray(CLKB). ForboththeFWFTandIDTStandard
modes,theFIFOreadpointerisincrementedeachtimeanewwordisclocked
to its output register. The state machine that controls an Output Ready flag
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe
FIFOmemorystatusisempty,empty+1,orempty+2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady
flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
thewordwaswritten. TheOutputReadyflagoftheFIFOremainsLOWuntil
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO
outputregister.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read
select(W/RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB). TheB0-B35
linesareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBisLOW.
The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENBisHIGH,MBBis
LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are
independent of any concurrent writes on Port A.
The setup and hold time constraints to the port clocks for the port Chip
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations
andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable
isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay
changestatesduringthesetupandholdtimewindowofthecycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagis
LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregister
bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag
HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory
arrayisclockedtotheoutputregisteronlywhenareadisselectedusingthe
port’sChipSelect,Write/Readselect,Enable,andMailboxselect.
WhenoperatingtheFIFOinIDTStandardmode,regardlessofwhether
theEmptyFlagisLOWorHIGH,dataresidingintheFIFO’smemoryarrayis
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO(1,2)
IDT723623(3)
IDT723633(3)
IDT723643(3)
EF/OR
AE
AF
FF/IR
0
0
0
L
H
H
H
H
L
H
H
1 to X
(X+1)to[256-(Y+1)]
(256-Y)to255
256
1 to X
(X+1)to[512-(Y+1)]
(512-Y)to511
512
1 to X
(X+1)to[1,024-(Y+1)]
(1,024-Y)to1,023
1,024
L
H
H
H
H
H
L
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output
register (no read operation necessary), it is not included in the memory count.
3. X is the almost-empty offset used by AE. Y is the almost-full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
12
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW ALMOST-FULL FLAG (AF)
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
thetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOWuntil writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing statusisalmost-full,almost-full-1,oralmost-full-2.TheAlmost-Fullstateisdefined
the Empty Flag HIGH; only then can data be read.
by the contents of register Y. These registers are loaded with preset values
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing duringaFlFOresetor,programmedfromPortA,orprogrammedserially(see
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). AnAlmost-
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthanorequal
can be the first synchronization cycle (see Figures 10 and 11).
to(256-Y),(512-Y),or(1,024-Y)fortheIDT723623,IDT723633,orIDT723643
respectively. AnAlmost-FullflagisHIGHwhenthenumberofwordsinitsFIFO
is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the
FULL/INPUT READY FLAGS (FF/IR)
Thisisadualpurposeflag. InFWFTmode,theInputReady(IR)function IDT723623, IDT723633, or IDT723643 respectively. Note that a data word
isselected. InIDTStandardmode,theFullFlag(FF) functionisselected. For present in the FIFO output register has been read from memory.
bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
isfreeintheFIFOtoreceivenewdata.Nomemorylocationsarefreewhenthe arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof
Full/InputReadyflagisLOWandattemptedwritestotheFIFOareignored. fill.Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat or less words remains LOW if two cycles of its synchronizing clock have not
writesdatatoitsarray(CLKA). ForbothFWFTandIDTStandardmodes,each elapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/
timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine 512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2. ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready Almost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifit
to be written to in a minimum of two cycles of the Full/Input Ready flag occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo inmemoryto[256/512/1024-(Y+1)]. Otherwise,thesubsequentsynchronizing
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe clock cycle may be the first synchronization cycle. (See Figure 16).
nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input MAILBOX REGISTERS
Ready flag HIGH.
Two 36-bit bypass registers are on the IDT723623/723633/723643 to
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock passcommandandcontrolinformationbetweenPortAandPortBwithoutputting
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursattime it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail
tSKEW1orgreateraftertheread. Otherwise,thesubsequentclockcyclecanbe registerandaFIFOforaportdatatransferoperation.Theusablewidthofboth
the first synchronization cycle (see Figures 13 and 14).
theMail1andMail2registersmatchestheselectedbussizeforPortB.
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
aPortAwriteisselectedbyCSA,W/RA,andENAwithMBAHIGH. Iftheselected
ALMOST-EMPTYFLAG(AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads PortBbussizeis36bits, theusablewidthoftheMail1registeremploysdata
datafromitsarray(CLKB).ThestatemachinethatcontrolsanAlmost-Emptyflag linesA0-A35. IftheselectedPortBbussizeis18bits,thentheusablewidthof
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe theMail1RegisteremploysdatalinesA0-A17.(Inthiscase,A18-A35aredon’t
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.The careinputs.) IftheselectedPortBbussizeis9bits,thentheusablewidthofthe
Almost-EmptystateisdefinedbythecontentsofregisterX.Theseregistersare Mail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’tcare
loaded with preset values during a FIFO reset, programmed from Port A, or inputs.)
programmedserially(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogram-
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
mingsection). AnAlmost-EmptyflagisLOWwhenitsFIFOcontainsXorless Register when a Port B write is selected by CSB, W/RB, and ENB with MBB
wordsandisHIGHwhenitsFIFOcontains(X+1)ormorewords. Notethata HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2
data word present in the FIFO output register has been read from memory. employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,thenthe
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock usablewidthoftheMail2RegisteremploysdatalinesB0-B17. (Inthiscase,B18-
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel B35aredon’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusable
offill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorewords widthoftheMail2RegisteremploysdatalinesB0-B8. (Inthiscase,B9-B35are
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe don’tcareinputs.)
writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost- Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs FIFOoutputregisterwhentheportMailboxSelectinputisLOWandfromthe
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. mailregisterwhentheportMailboxSelectinputisHIGH.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 15).
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB
13
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
to-HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduring
FIFOoperation.BEisadon’tcareinputwhenthebussizeselectedforPortB
islongword.TheendianmethodisimplementedatthecompletionofReset,by
the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Only 36-bit long word data is written to or read from the FIFO memory
ontheIDT723623/723633/723643. Bus-matchingoperationsaredoneafter
data is read from the FIFO RAM. These bus-matching operations are not
availablewhentransferringdataviamailboxregisters.Furthermore,boththe
word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused
formailregisteroperations.Inthiscase,onlythosebytelanesbelongingtothe
selected word- or byte-size bus can carry mailbox data. The remaining data
outputswillbeindeterminate.Theremainingdatainputswillbedon’tcareinputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected,thenmailboxdatacanbetransmittedonlybetweenA0-A8andB0-
B8. (See Figures 17 and 18).
HIGH. Fora36-bitbussize,36bitsofmailboxdataareplacedonB0-B35. For
an18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthiscase,
B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on B0-B8. (In this case, B9-B35 are indeterminate.)
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH.
Fora36-bitbussize,36bitsofmailboxdataareplacedonA0-A35. For
an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17. (Inthiscase,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
Thedatainamailregisterremainsintactafteritisreadandchangesonly
whennewdataiswrittentotheregister. TheEndianSelectfeaturehasnoeffect
onmailboxdata.Formailregisterandmailregisterflagtimingdiagrams,see
Figure 17 and 18.
BUS SIZING
BUS-MATCHING FIFO READS
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
9-bitbyteformatfordatareadfromtheFIFO.ThelevelsappliedtothePortB
BusSizeSelect(SIZE)andtheBus-MatchSelect(BM)determinethePortB
bussize.TheselevelsshouldbestaticthroughoutFIFOoperation. Bothbus
sizeselectionsareimplementedatthecompletionofReset,bythetimetheFull/
Input Ready flag is set HIGH, as shown in Figure 2.
TwodifferentmethodsforsequencingdatatransferareavailableforPort
B when the bus size selection is either byte-or word-size. They are referred
toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant
bytefirst). ThelevelappliedtotheBig-EndianSelect(BE)inputduringtheLOW-
DataisreadfromtheFIFORAMin36-bitlongwordincrements. Ifalong
wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO
outputregister.IfbyteorwordsizeisimplementedonPortB,onlythefirstone
ortwobytesappearontheselectedportionoftheFIFOoutputregister,withthe
restofthelongwordstoredinauxiliaryregisters. Inthiscase,subsequentFIFO
readsoutputtherestofthelongwordtotheFIFOoutputregisterintheorder
shown by Figure 2.
WhenreadingdatafromFIFOinbyteorwordformat,theunusedB0-B35
outputsareindeterminate.
14
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
Write to FIFO
A35⎯A27
A26⎯A18
A17⎯A9
A8⎯A0
BYTE ORDER ON PORT A:
A
B
C
D
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
BE BM SIZE
B
D
Read from FIFO
A
C
X
L
X
(a) LONG WORD SIZE
BYTE ORDER ON PORT B:
BE BM SIZE
B35⎯B27
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
1st: Read from FIFO
2nd: Read from FIFO
A
B
H
H
L
B26⎯B18
B17⎯B9
B8⎯B0
C
D
(b) WORD SIZE
⎯
BIG-ENDIAN
B35⎯B27
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
C
D
L
H
L
B26⎯B18
B17⎯B9
B8⎯B0
A
B
(c) WORD SIZE
⎯
LITTLE-ENDIAN
B35⎯B27
B35⎯B27
B35⎯B27
B35⎯B27
B26⎯B18
B26⎯B18
B26⎯B18
B26⎯B18
B17⎯B9
B8⎯B0
BE BM SIZE
A
1st: Read from FIFO
2nd: Read from FIFO
H
H
H
B17⎯B9
B17⎯B9
B17⎯B9
B8⎯B0
B
B8⎯B0
3rd: Read from FIFO
4th: Read from FIFO
C
B8⎯B0
D
(d) BYTE SIZE
⎯
BIG-ENDIAN
B35⎯B27
B35⎯B27
B35⎯B27
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
BE BM SIZE
D
1st: Read from FIFO
L
H
H
B26⎯B18
B26⎯B18
B26⎯B18
B17⎯B9
B17⎯B9
B8⎯B0
2nd: Read from FIFO
3rd: Read from FIFO
C
B8⎯B0
B
B17⎯B9
B8⎯B0
A
4th: Read from FIFO
3269 drw03
(e) BYTE SIZE
⎯
LITTLE-ENDIAN
Figure 2. Bus sizing
15
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
t
RSTS
tRSTH
RS1/RS2(3)
tBEH
t
BES
tFWS
BE/FWFT
BE
0,1
FWFT
t
SPMH
t
t
SPMS
FSS
SPM
t
FSH
FS1,FS0
t
WFF
t
WFF
FF/IR
EF/OR
AE
(2)
tREF
t
t
RSF
RSF
AF
t
RSF
MBF1,
MBF2
3269 drw04
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. Reset Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
CLKA
CLKB
t
RSTS
tRSTH
PRS
t
WFF
t
WFF
FF/IR
t
REF(2)
EF/OR
AE
t
RSF
t
RSF
AF
t
RSF
MBF1,
MBF2
3269 drw05
NOTES
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
16
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
2
CLKA
1
4
RS1
t
FSS
t
FSH
SPM
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FF/IR
tENS2
tENH
ENA
tDH
tDS
A0-A35
3269 drw06
AE Offset
AF Offset
(Y)
First Word to FIFO
(X)
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset. (IDT Standard and FWFT Modes)
CLKA
RS1
4
t
t
FSS
FSS
t
FSH
SPM
t
WFF
FF/IR
t
SENS
t
SENH
SDH
t
SENS
t
SENH
SDH
tSPH
FS1/SEN
tSDS
t
t
tSDS
FS0/SD(2)
AF Offset
(Y) MSB
AE Offset
(X) LSB
3269 drw07
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
17
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FF/IRA
HIGH
tENS1
tENH
CSA
t
ENS1
t
ENH
ENH
ENH
W/RA
MBA
ENA
t
ENS2
t
tENS2
tENS2
tENH
t
tENS2
tENH
tDS
tDH
W1(1)
W2(1)
No Operation
A0-A35
3269 drw08
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EF/OR HIGH
CSB
W/RB
MBB
tENS2
tENS2
tENH
tENH
tENH
tENS2
ENB
tDIS
t
MDV
tA
tA
tEN
(1)
W1
W2(1)
B0-B35
Previous Data
(Standard Mode)
t
MDV
t
DIS
OR
tA
tA
W1(1)
tEN
W3(1)
B0-B35
W2(1)
(FWFT Mode)
3269 drw09
NOTE:
1. Data read from the FIFO
DATA SIZE TABLE FOR FIFO LONG-WORD READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
DATA READ FROM FIFO
(SELECT AT RESET)
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
18
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
CLKB
FF/OR HIGH
CSB
W/RB
MBB
tENS2
tENH
ENB
No Operation
Read 2
tDIS
tDIS
tMDV
t
A
t
A
B0-B17
tEN
tEN
Read 1
Read 2
Previous Data
(Standard Mode)
tMDV
OR
t
A
t
A
B0-B17
(FWFT Mode)
Read 1
Read 3
3269 drw10
NOTE:
1. Unused word B18-B35 are indeterminate.
DATA SIZE TABLE FOR WORD READS
SIZE MODE (1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
H
A
B
C
D
1
2
A
C
B
D
H
L
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
19
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
CLKB
HIGH
EF/OR
CSB
W/RB
MBB
t
ENS2
t
ENH
A
ENB
No Operation
t
MDV
tDIS
t
A
tA
t
t
A
t
EN
B0-B8
(Standard Mode)
Read 1
Read 4
Read 5
Previous Data
Read 2
Read 3
tDIS
OR
tA
t
MDV
tA
t
A
tA
t
EN
B0-B8
(FWFT Mode)
Read 1
Read 2
Read 3
Read 4
3269 drw11
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.
DATA SIZE TABLE FOR BYTE READS
SIZE MODE(1)
SIZE
DATA WRITTEN TO FIFO
READ
NO.
DATA READ FROM FIFO
B8-B0
BM
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
H
A
B
C
C
D
1
2
3
4
D
C
B
A
H
L
A
B
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
20
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
LOW
HIGH
CSA
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
t
IR
HIGH
tDS
tDH
A0-A35
W1
t
tSKEW1
CLKtCLKL
(1)
tCLKH
CLKB
1
2
3
t
REF
tREF
FIFO Empty
LOW
OR
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
tA
B0-B35
Old Data in FIFO Output Register
W1
3269 drw12
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
21
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
HIGH
CSA
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
HIGH
FF
tDS
tDH
W1
A0-A35
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
t
REF
t
REF
FIFO Empty
LOW
EF
CSB
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
W1
B0-B35
3269 drw13
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)
22
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENH
tENS2
ENB
OR
HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
tCLK
(1)
tSKEW1
tCLKH
tCLKL
CLKA
1
2
tWFF
tWFF
FIFO Full
LOW
IR
CSA
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tDS
tENH
tDH
ENA
A0-A35
3269 drw14
To FIFO
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)
23
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
EF
HIGH
tA
Previous Word in FIFO Output Register
SKEW1
Next Word From FIFO
B0-B35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKA
WFF
ENH
WFF
t
t
FF
FIFO Full
LOW
CSA
W/RA
HIGH
t
tENS2
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
To FIFO
3269 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
CLKB
AE
t
SKEW2(1)
1
2
t
PAE
t
PAE
X Word in FIFO
(X+1) Words in FIFO
ENS2
t
tENH
ENB
3269 drw16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
24
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
CLKA
1
2
(1)
tENH
tENS2
tSKEW2
ENA
t
PAF
tPAF
(D-Y) Words in FIFO
[D-(Y+1)] Words in FIFO
AF
CLKB
tENH
tENS2
ENB
3269 drw17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723623, 512 for the IDT723633, 1,024 for the IDT723643.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
CLKA
tENS1
tENH
CSA
W/RA
MBA
t
ENH
t
ENS1
tENS2
tENH
tENS2
tENH
ENA
tDH
tDS
W1
A0-A35
CLKB
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
MDV
tEN
tDIS
t
PMR
B0-B35
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
3269 drw18
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
25
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
CLKB
tENS1
tENH
CSB
tENS1
tENH
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
tDH
tDS
W1
B0-B35
CLKA
MBF2
t
PMF
t
PMF
CSA
W/RA
MBA
ENA
tENH
tENS2
tEN
tPMR
tDIS
t
MDV
W1 (Remains valid in Mail2 Register after read)
FIFO Output Register
A0-A35
3269 drw19
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid
data (A9-A35 will be indeterminate).
Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
TRANSFER CLOCK
WRITE
WRITE CLOCK (CLKA)
READ
READ CLOCK (CLKB)
CLKB
EF/OR
ENB
CLKA
•
CHIP SELECT (CSA)
CHIP SELECT (CSB)
ENA
V
CC
EMPTY FLAG/
OUTPUT READY (EF/OR)
WRITE SELECT (W/RA)
FF/IR
WRITE ENABLE (ENA)
READ ENABLE (ENB)
ALMOST-FULL FLAG (AF)
V
CC
CSB
CSA
READ SELECT (W/RB)
IDT
IDT
723623
723633
723643
723623
723633
723643
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A0-A35
n
B0-B35
n
B0-B35
FULL FLAG/
INPUT READY (FF/IR)
MBA
DATA OUT (Qn)
Qn
Dn
V
CC
V
CC
W/RB
MBB
W/RA
3269 drw20
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO
is the sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 19. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
26
IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 k Ω
From Output
Under Test
30 pF(1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
GND
1.5 V
GND
3 V
tS
th
tW
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
≈
3 V
Input
1.5 V
1.5 V
1.5 V
tPD
Low-Level
Output
GND
V
OL
tPZH
tPD
V
OH
V
OH
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
tPHZ
OL
≈
OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3269 drw21
NOTE:
1. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms.
27
ORDERING INFORMATION
X
XXXXXX
X
XX
X
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
8
Tube or Tray
Tape and Reel
Commercial (0oC to +70oC)
Green
BLANK
G(1)
Thin Quad Flat Pack (TQFP, PK128)
PF
Clock Cycle Time (tCLK
)
12
15
Commercial Only
Low Power
Speed in Nanoseconds
L
TM
256 x 36 ⎯ SyncFIFO with Bus-Matching
723623
723633
723643
TM
512 x 36 ⎯ SyncFIFO with Bus-Matching
TM
1,024 x 36 ⎯ SyncFIFO with Bus-Matching
3269 drw22
NOTE:
1. Green parts are available. For specific speeds and packages please contact your sales office.
DATASHEETDOCUMENTHISTORY
10/04/2000
03/21/2001
08/01/2001
02/04/2009
03/24/2014
pgs. 1 through 28.
pgs 6 and 7.
pgs. 1, 6, 8, 9 and 28.
pgs. 1, and 28.
pgs. 1-3, 6, 8, 9 and 28.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
28
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