7283L20PAI8 [IDT]
FIFO, 2KX9, 20ns, Asynchronous, CMOS, PDSO56, TSSOP-56;
| 型号： | 7283L20PAI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 2KX9, 20ns, Asynchronous, CMOS, PDSO56, TSSOP-56 先进先出芯片 光电二极管 |
| 文件： | 总11页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7280
IDT7281
IDT7282
IDT7283
IDT7284
IDT7285
CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
DESCRIPTION:
FEATURES:
TheIDT7280/7281/7282/7283/7284/7285aredual-FIFOmemoriesthat
loadandemptydataonafirst-in/first-outbasis.Thesedevicesarefunctional
and compatible to two 7200/7201/7202/7203/7204/7205 FIFOs in a single
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate
pins. The devices use Full and Empty flags to prevent data overflow and
underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth
word size and depth.
•
•
•
•
•
•
•
The 7280 is equivalent to two 7200 256 x 9 FIFOs
The 7281 is equivalent to two 7201 512 x 9 FIFOs
The 7282 is equivalent to two 7202 1,024 x 9 FIFOs
The 7283 is equivalent to two 7203 2,048 x 9 FIFOs
The 7284 is equivalent to two 7204 4,096 x 9 FIFOs
The 7285 is equivalent to two 7205 8,192 x 9 FIFOs
Low power consumption
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data.
Data is toggled in and out of the devices through the use of the Write (W)
and Read (R) pins.
— Active: 685 mW (max.)
— Power-down: 83 mW (max.)
Ultra high speed—12 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bi-directional, width expansion, depth expansion, bus-
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS technology
Space-saving TSSOP
Industrial temperature range (–40oC to +85oC) is available
•
•
•
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user’s option. This feature is especially useful in data commu-
nications applications where it is necessary to use a parity bit for transmis-
sion/reception error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position when RT is
pulsedLOWtoallowforretransmissionfromthebeginningofdata.AHalf-Full
Flagis available inthe single device mode andwidthexpansionmodes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and
simultaneous read/writes in multiprocessing and rate buffer applications.
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
DATA INPUTS
(DA0-DA8)
(DB0-DB8)
RSA
RSB
WB
WRITE
CONTROL
WRITE
CONTROL
RAM
RAM
WA
ARRAY A
256 x 9
ARRAY B
256 x 9
512 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
WRITE
POINTER
WRITE
POINTER
READ
POINTER
READ
POINTER
THREE-
STATE
BUFFERS
THREE-
STATE
BUFFERS
READ
CONTROL
READ
CONTROL
RA
RESET
LOGIC
RESET
LOGIC
FLAG
LOGIC
FLAG
LOGIC
EXPANSION
LOGIC
EXPANSION
LOGIC
XIA
FFA EFA
RB
XIB
XOA/HFA
FLA/RTA
FFB EFB
FLB/RTB
DATA
OUTPUTS
(QA0-QA8)
XOB/HFB
DATA
OUTPUTS
(QB0-QB8)
3208 drw 01
DECEMBER 1998
1
1998 Integrated Device Technology, Inc.
DSC-3208/3
IDT7280/81/82
IDT
PINCONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Com'l & Ind'l
Unit
1
FFA
QA
QA
QA
QA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
XIA
DA
DA
DA
VTERM
TerminalVoltagewith
Respect to GND
–0.5 to +7.0
V
2
0
1
2
3
0
1
2
3
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55to+125
–50to+50
oC
mA
4
5
DA3
6
QA8
DA8
NOTE:
3208 tbl 01
7
WA
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
RA
VCC
9
QA
4
DA
DA
DA
DA
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
QA
QA
QA
5
5
6
7
6
7
XOA/HFA
EFA
FLA/RTA
RSA
RECOMMENDEDDCOPERATING
CONDITIONS
FFB
XIB
QB
0
DB0
QB
QB
QB
1
DB
DB
DB
DB
WB
1
Symbol
Parameter
SupplyVoltage
Min.
4.5
0
Typ.
5.0
0
Max. Unit
2
3
2
3
VCC
5.5
0
V
V
QB
8
8
GND
SupplyVoltage
GND
(1)
RB
VCC
VIH
InputHighVoltage
InputLowVoltage
2.0
—
0
—
—
—
—
0.8
70
V
QB
4
DB
DB
DB
DB
4
(2)
VIL
V
oC
QB
QB
QB
5
5
6
7
6
7
TA
OperatingTemperature
Commercial
XOB/HFB
FLB/RTB
RSB
EFB
TA
OperatingTemperature
Industrial
–40
—
85
oC
3208 drw 02
TSSOP (SO56-2, order code: PA)
TOP VIEW
NOTES:
3208 tbl 03
1. For RT/RS/XI input, VIH = 2.6V (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0oC to +70oC; Industrial: VCC = 5V ± 10%, TA = –40oC to +85oC)
IDT7280L
IDT7281L
IDT7282L
IDT7283L
IDT7284L
IDT7285lL
Com'l & Ind'l(1)
tA = 12, 15, 20 ns
Com'l & Ind'l(1)
tA = 12, 15, 20 ns
Symbol
Parameter
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Min.
–1
Max.
1
Min.
–1
Max.
—
Unit
µ A
µ A
V
(2)
ILI
(3)
ILO
–10
2.4
—
10
–10
2.4
—
10
VOH
VOL
OutputLogic“1”Voltage
OutputLogic“0”Voltage
IOH = –2mA
IOL = 8mA
—
0.4
—
0.4
V
(4,5)
(6)
ICC1
Active Power Supply Current (both FIFOs)
—
125
—
150
15
mA
mA
(4,7)
ICC2
Standby Current (R=W=RS=FL/RT=VIH)
—
15
—
NOTES:
1. Industrial temperature range product for the 20ns speed grade is available as a standard
device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. Tested at f = 20 MHz.
6. Typical ICC1 = 2*[15 + 2*fS + 0.02*CL*fS] (in mA) with VCC = 5V, TA = 25oC, fS = WCLK
ACTESTCONDITIONS
InputPulseLevels
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
GND to 3.0V
5ns
1.5V
1.5V
SeeFigure1
frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
3208 tbl 08
7. All Inputs = VCC - 0.2V or GND + 0.2V.
5V
1.1K
TO
OUTPUT
PIN
CAPACITANCE(TA = +25oC, f = 1.0 MHz)
30pF*
Symbol
CIN
Parameter
Condition
VIN = 0V
Max.
Unit
pF
680Ω
InputCapacitance
OutputCapacitance
8
8
3208 drw 03
COUT
VOUT = 0V
pF
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
NOTE:
1. Characterized values, not currently tested.
2679 tbl 02
2
IDT
IDT7280/81/82
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0oC to +70oC; Industrial: VCC = 5V ± 10%, TA = –40oC to +85oC)
Commercial
Com'l & Ind'l(2)
7280L12
7281L12
7282L12
7283L12
7284L12
7285L12
7280L15
7280L20
7281L20
7282L20
7283L20
7284L20
7285L20
7281L15
7282L15
7283L15
7284L15
7285L15
Symbol
tS
Parameter
Min.
—
Max.
50
Min.
—
Max.
40
Min.
Max.
33.3
Unit
MHz
ShiftFrequency
ReadCycleTime
AccessTime
—
30
—
10
20
3
tRC
20
—
8
—
12
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
—
—
12
17
20
12
14
—
12
14
17
17
—
12
12
—
—
—
25
—
10
15
3
—
15
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tRR
ReadRecoveryTime
ReadPulseWidth(3)
tRPW
tRLZ
tWLZ
tDV
12
3
(4)
ReadPulseLowtoDataBusatLowZ
(4,5)
WritePulseHightoDataBusatLowZ
DataValidfromReadPulseHigh
5
5
5
5
5
5
(4)
tRHZ
tWC
tWPW
tWR
tDS
ReadPulseHightoDataBusatHighZ
WriteCycleTime
WritePulseWidth(3)
WriteRecoveryTime
DataSet-upTime
—
20
12
8
—
25
15
10
11
0
—
30
20
10
12
0
9
tDH
DataHoldTime
0
tRSC
tRS
ResetCycleTime
20
12
12
8
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
(3)
ResetPulseWidth
tRSS
tRSR
tRTC
tRT
ResetSet-upTime(4)
ResetRecoveryTime
RetransmitCycleTime
20
12
12
8
(3)
RetransmitPulseWidth
tRTS
tRTR
tEFL
RetransmitSet-upTime(4)
RetransmitRecoveryTime
ResettoEmptyFlagLow
—
—
—
—
—
12
—
—
—
—
12
—
—
12
8
tHFH,FFH ResettoHalf-FullandFullFlagHigh
tRTF
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
tXOL
tXOH
tXI
RetransmitLowtoFlagsValid
Read Low to Empty Flag Low
ReadHightoFullFlagHigh
ReadPulseWidthafterEFHigh
WriteHightoEmptyFlagHigh
WriteLowtoFullFlagLow
WriteLowtoHalf-FullFlagLow
ReadHightoHalf-FullFlagHigh
WritePulseWidthafterFFHigh
Read/WritetoXOLow
Read/WritetoXOHigh
XIPulseWidth(3)
tXIR
XI Recovery Time
tXIS
XISet-upTime
8
ns
NOTES:
3208 tbl 06
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range is available by special order for speed grades faster than 20ns.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
3
IDT7280/81/82
IDT
DeviceMode,thispinactsastheretransmitinput.TheSingleDeviceModeis
initiated by grounding the Expansion In (XI).
SIGNALDESCRIPTIONS
INPUTS:
These devices can be made to retransmit data when the Retransmit
Enablecontrol(RT)inputispulsedLOW. Aretransmitoperationwillsetthe
internal read pointer to the first location and will not affect the write pointer.
Read Enable (R) and Write Enable (W) must be in the HIGH state during
retransmit.Thisfeatureisusefulwhenlessthan256/512/1,024/2,048/4,096/
8,192 writes are performed between resets. The retransmit feature is not
compatiblewiththeDepthExpansionModeandwillaffecttheHalf-FullFlag
(HF), dependingonthe relative locations ofthe readandwrite pointers.
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW
state. During reset, both internal read and write pointers are set to the first
location.Aresetis requiredafterpowerupbeforeawriteoperationcantake
place. Both the Read Enable (R) and Write Enable (W) inputs must be
in the HIGH state during the window shown in Figure 2, (i.e., tRSS
before the rising edge of RS) and should not change until tRSR after
the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after
Reset (RS).
EXPANSION IN (XI)
This input is a dual-purpose pin. Expansion In (XI) is grounded to
indicate an operation in the single device mode. Expansion In (XI) is
connected to Expansion Out (XO) of the previous device in the Depth
Expansion or Daisy Chain Mode.
OUTPUTS:
WRITE ENABLE (W)
FULL FLAG (FF)
A write cycle is initiated on the falling edge of this input if the Full Flag
(FF) is not set. Data set-up and hold times must be adhered to with respect
to the rising edge of the Write Enable (W). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(HF)willbesettoLOWandwillremainsetuntilthe
differencebetweenthewritepointerandreadpointeris less thanorequalto
onehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(HF)isthenreset
by the rising edge of the read operation.
TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
write pointer is one location less than the read pointer, indicating that the
deviceis full.Ifthereadpointeris notmovedafterReset(RS),theFull-Flag
(FF) will go LOW after 256 writes for IDT7280, 512 writes for the IDT7281,
1,024writes for the IDT7282, 2,048writes forthe IDT7283, 4,096writes for
the IDT7284 and 8,192 writes for the IDT7285.
EMPTY FLAG (EF)
TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when
the read pointer is equal to the write pointer, indicating that the device is
empty.
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations.Uponthecompletionofavalidreadoperation,theFullFlag
(FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO
is full, the internal write pointer is blocked from W, so external changes in
W will not affect the FIFO when it is full.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
This is a dual-purpose output. In the single device mode, when Expan-
sion In (XI) is grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(HF)willbesetLOWandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal
toone halfofthe totalmemoryofthe device. The Half-FullFlag(HF)is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to
Expansion Out (XO) of the previous device. This output acts as a signal to
the next device in the Daisy Chain by providing a pulse to the next device
when the previous device reaches the last location of memory.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the Read Enable (R)
providedtheEmptyFlag(EF)isnotset.ThedataisaccessedonaFirst-In/First-
Outbasis,independentofanyongoingwriteoperations.AfterReadEnable(R)
goesHIGH,theDataOutputs(Q0–Q8)willreturntoahighimpedancecondition
until the next Read operation. When all data has been read from the FIFO, the
EmptyFlag(EF)willgoLOW,allowingthe“final”readcyclebutinhibitingfurther
read operations with the data outputs remaining in a high impedance state.
Once a validwrite operationhas beenaccomplished, the EmptyFlag(EF)will
goHIGHaftertWEF anda validReadcanthenbegin. Whenthe FIFOis empty,
theinternalreadpointerisblockedfromRsoexternalchangesinRwillnotaffect
the FIFO when it is empty.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (R) is in a HIGH state.
FIRST LOAD/RETRANSMIT (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
groundedtoindicatethatitisthefirstloaded(seeOperatingModes). IntheSingle
4
IDT
IDT7280/81/82
RSC
t
RS
t
RS
W
RSS
t
RSR
t
RSS
t
R
EFL
t
EF
HFH FFH
t
, t
HF, FF
3208 drw 04
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset
t
RC
t
RPW
t
RR
t
A
t
A
R
t
DV
t
RHZ
t
RLZ
Q0-Q8
DATA OUT VALID
DATA OUT VALID
t
WC
t
WR
t
WPW
W
t
DS
t
DH
D0-D8
DATA IN VALID
DATA IN VALID
3208 drw 05
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
R
W
t
WFF
RFF
t
3208 drw 06
FF
Figure 4. Full Flag From Last Write to First Read
5
IDT7280/81/82
IDT
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
R
EF
WEF
t
REF
t
A
t
DATA OUT
VALID
VALID
3208 drw 07
Figure 5. Empty Flag From Last Read to First Write
t
RTC
t
RT
RT
W,R
RTS
t
RTR
t
t
RTF
HF, EF, FF
FLAG VALID
3208 drw 08
Figure 6. Retransmit
W
EF
R
WEF
t
RPE
t
3208 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
FF
W
RFF
t
WPF
t
3208 drw 10
Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse
6
IDT
IDT7280/81/82
W
R
RHF
t
WHF
t
HALF-FULL OR LESS
HALF-FULL OR LESS
MORE THAN HALF-FULL
Figure 9. Half-Full Flag Timing
HF
3208 drw 11
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
W
R
XOL
t
XOH
t
XOH
t
XOL
t
3208 drw 12
XO
Figure 10. Expansion Out
XI
XIR
t
t
XI
XIS
t
WRITE TO
FIRST PHYSICAL
LOCATION
W
R
XIS
t
READ FROM
FIRST PHYSICAL
LOCATION
3208 drw 13
Figure 11. Expansion In
7282/7283/7284/7285s. Any depth can be attained by adding additional
IDT7280/7281/7282/7283/7284/7285s.TheseFIFOsoperateintheDepth
Expansionmodewhenthefollowingconditionsaremet:
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by
each system (i.e. FF is monitored on the device where W is used; EF is
monitored on the device where R is used).
1. The first FIFO must be designated by grounding the First Load (FL)
control input.
Single Device Mode
2. AllotherFIFOs musthave FLinthe HIGHstate.
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (FF) and
Empty Flag (EF). This requires the ORing of all EFs and ORing of all
FFs (i.e. all must be set to generate the correct composite FF or EF).
See Figure 14.
A single IDT7280/7281/7282/7283/7284/7285 may be used when the
applicationrequirementsarefor256/512/1,024/2,048/4,096/8,192wordsor
less. TheseFIFOsareinaSingleDeviceConfigurationwhentheExpansion
In (XI) control input is grounded (see Figure 12).
Depth Expansion
These devices can easily be adapted to applications when the require-
mentsareforgreaterthan256/512/1,024/2,048/4,096/8,192words. Figure
14 demonstrates a four-FIFO Depth Expansion using two IDT7280/7281/
5. TheRetransmit(RT)functionandHalf-FullFlag(HF)arenotavailable
in the Depth Expansion Mode.
7
IDT7280/81/82
IDT
theFIFOpermitsareadingofasinglewordafterwritingonewordofdatainto
anemptyFIFO.Thedataisenabledonthebusin(tWEF+tA)nsaftertherising
edge ofW, calledthe firstwrite edge, anditremains onthe bus untilthe R
lineisraisedfromLOW-to-HIGH,afterwhichthebuswouldgointoathree-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertionandthenwouldbeasserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
fullFIFO.TheRlinecausestheFFtobedeassertedbuttheWlinebeingLOW
causesittobeassertedagaininanticipationofanewdataword.Ontherising
edge of W, the new word is loaded in the FIFO. The Wline must be toggled
whenFFisnotassertedtowritenewdataintheFIFOandtoincrementthewrite
pointer.
USAGEMODES:
Width Expansion
Word width may be increased simply by connecting the corresponding
input control signals of multiple FIFOs. Status flags (EF, FF and HF) can
be detected from any one FIFO. Figure 13 demonstrates an 18-bit word
widthbyusingthetwoFIFOscontainedintheIDT7280/7281/7282/7283/7284/
7285s. Any word width can be attained by adding FIFOs (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7280/7281/7282/7283/7384/7285s as shown in Figure 16. Both Depth
ExpansionandWidthExpansionmaybeusedinthis mode.
Compound Expansion
Thetwoexpansiontechniquesdescribedabovecanbeappliedtogether
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Data Flow-Through
Two types of flow-through modes are permitted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17),
(HALF-FULL FLAG)
WRITE (W)
(HF)
FIFO
A or B
IDT
7280
7281
7282
7283
7284
7285
READ (R)
9
9
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
3208 drw 14
EXPANSION IN (XI)
Figure 12. Block Diagram of One 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 FIFO Used in Single Device Mode
9
HFA
HFB
18
9
IN
DATA
(D)
FIFO A
FIFO B
WRITE (W)
FULL FLAG (FFA)
RESET (RS)
READ (R)
EMPTY FLAG (EFB)
RETRANSMIT (RT)
9
7280/7281/7282/
7283/7284/7285
9
XIA
XIB
18
OUT
(Q)
DATA
3208 drw 15
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 FIFO Memory Used in Width Expansion Mode
8
IDT
IDT7280/81/82
TABLE IRESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
Internal Status
Write Pointer
Outputs
Mode
RS
RT
XI
Read Pointer
EF
FF
HF
Reset
0
1
1
X
0
0
0
0
Location Zero
Location Zero
Increment(1)
Location Zero
Unchanged
Increment(1)
0
1
1
Retransmit
Read/Write
NOTE:
X
X
X
X
X
1
X
2679 tbl 09
1. Pointer will increment if flag is High.
TABLE IIRESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
Internal Status
Write Pointer
Outputs
Mode
RS
FL
XI
Read Pointer
EF
FF
Reset First Device
Reset All Other Devices
Read/Write
0
0
1
0
1
(1)
(1)
(1)
Location Zero
Location Zero
X
Location Zero
Location Zero
X
0
0
1
1
X
X
X
NOTE:
2679 tbl 10
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
XI = Expansion Input, HF = Half-Full Flag Output
XOA
EFA
FFA
FIFO A
FLA
XIA
7280/7281/
7282/7283/
7284/7285
XOB
W
R
EFB
FFB
FIFO B
D
Q
9
9
9
FLB
VCC
XIB
XOA
FFA
EFA
FULL
EMPTY
FIFO A
9
FLA
XIA
7280/7281/
7282/7283/
7284/7285
XOB
EFB
FFB
FIFO B
9
RSA
FLB
XIB
3208 drw 16
Figure 14. Block Diagram of 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 FIFO Memory (Depth Expansion)
9
IDT7280/81/82
IDT
Q
0
-Q
8
Q
(N-8)-Q
N
N
Q
9
-Q17
Q9
-Q17
Q0
-Q
8
Q(N-8)-Q
IDT7280/7281/
7282/7283/
7284/7285
DEPTH
EXPANSION
BLOCK
IDT7280/7281/
7282/7283/
7284/7285
DEPTH
EXPANSION
BLOCK
IDT7280/7281/
7282/7283/
7284/7285
DEPTH
EXPANSION
BLOCK
R, W, RS
D0-D8
D(N-8)-DN
D9-D17
D0-DN
D18-D
N
D(N-8)-DN
D9-DN
3208 drw 17
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
WA
FF
RA
EF
HF
A
A
FIFO A
A
QA0-8
D
A0-8
IDT
7280
7281
7282
7283
7284
7285
SIDE 1
SIDE 2
Q
B0-8
D
B0-8
FIFO B
R
HF
B
B
WB
EF
B
FFB
3208 drw 18
Figure 16. Bidirectional FIFO Mode
IN
W
R
DATA
RPE
t
EF
REF
t
WEF
t
WLZ
t
A
t
DATAOUT
OUT
DATA
VALID
3208 drw 19
Figure 17. Read Data Flow-Through Mode
10
R
W
WPF
t
RFF
t
FF
DH
t
WFF
t
IN
DATA
VALID
IN
DATA
A
t
DS
t
OUT
DATA
OUT
DATA
VALID
3208 drw 20
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT
XXXX
X
XXX
X
X
Device Type Power Speed Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0OC to +70OC)
Industrial (-40OC to +85OC)
PA
Thin Shrink SOIC (TSSOP, SO56-2)
Commercial
Commercial
Commercial and Industrial
12
15
20
Access Time (t
in Nanoseconds
A) Speed
L
Low Power
256 x 9 Dual FIFO
512 x 9 Dual FIFO
1,024 x 9 Dual FIFO
2,048 x 9 Dual FIFO
4,096 x 9 Dual FIFO
8,192 x 9 Dual FIFO
7280
7281
7282
7283
7284
7285
3208 drw 21
NOTE:
1. Industrial temperature grade is available by special order for speed grades faster than 20ns.
2975StenderWay
Santa Clara, CA 95054
800-345-7015
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
11
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