728985DB [IDT]
Telecom IC, PQFP44;
| 型号： | 728985DB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Telecom IC, PQFP44 |
| 文件： | 总13页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT728985
andwriteaccess toindividualchannels.As animportantfunctionofadigital
switchis tomaintainsequenceintegrityandminimizethroughputdelay,the
IDT728985isanidealsolutionformostswitchingneeds.
ꢀEATURES:
•
•
•
•
•
•
•
•
•
•
256 x 256 channel non-blocking switch
Automatic signal identification (ST-BUS®, GCI)
8 RX inputs — 32 channels at 64 Kbit/s per serial line
8 TX outputs — 32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
5V Power Supply
Operating Temperature Range -40°C to +85°C
Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
44-pin Plastic Quad Flatpack (PQFP) and 40-pin Plastic Dip
(P-DIP)
ꢀUNCTIONALDESCRIPTION
Framesequence,constantthroughputdelay,andguaranteedminimum
delayarehighpriorityrequirementsintoday’sintegrateddataandmultimedia
networks. TheIDT728985provides thesefunctions onaper-channelbasis
usingastandardmicroprocessorcontrolinterface. Eachoftheeightseriallines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
InProcessorMode,themicroprocessorcanaccesstheinputandoutputtime
slotstocontrolotherdevicessuchasISDNtransceiversandtrunkinterfaces.
SupportingbothGCIandST-BUS® formats,IDT728985hasincorporatedan
internal circuit to automatically identify the polarity and format of the frame
synchronization.
DESCRIPTION:
TheIDT728985isaST-BUS®/GCIcompatibledigitalswitchcontrolledby
amicroprocessor. TheIDT728985canhandleasmanyas256,64Kbit/sinput
andoutputchannels. Those256channelsaredividedinto8serialinputsand
outputs,eachofwhichconsistsof32channels. TheIDT728985providesper-
channelvariableorconstantthroughputdelaymodesandmicroprocessorread
AfunctionalblockdiagramoftheIDT728985deviceisshownonpage1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µswideframeseachcontaining32,8-bitchannels. Eightinput(RX0-7)and
ꢀUNCTIONAL BLOCK DIAGRAM
ODE
C4i
F0i
VCC GND
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
Timing
Unit
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Output MUX
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Control Register
Microprocessor Interface
5708 drw01
CCO
DS
A0/
A5
CS
R/W
D0/
D7
DTA
APRIL 2001
1
2001 Integrated Device Technology, Inc.
DSC-5708/2
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
PINCONꢀIGURATION
INDEX
INDEX
RX3
1
33
32
31
30
TX3
RX3
7
TX3
TX4
TX5
TX6
39
38
37
36
RX4
RX5
RX6
2
3
4
TX4
TX5
TX6
TX7
GND
RX4
RX5
RX6
8
9
10
11
12
13
14
RX7
VCC
5
6
7
8
29
28
27
26
35
34
33
32
RX7
TX7
V
CC
GND
CCO
ODE
TX0
TX1
TX2
TX3
TX4
DTA
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
40
39
38
37
36
35
34
33
32
31
30
29
28
F0i
D
0
1
1
F0i
C4i
D0
D1
D2
D3
D4
D
C4i
2
A0
25
24
23
9
D
2
3
3
A
0
15
16
17
31
30
29
A1
A2
10
D
4
A
A
1
2
D4
11
5
6
5708 drw03
7
5708 drw02
TX5
TX6
TX7
GND
D0
8
9
VCC
10
11
12
13
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
F0i
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
C4i
A0
D1
D2
A1
27
26
14
15
A2
A3
A4
A5
D3
D4
D5
D6
D7
25
24
23
22
21
16
17
18
19
20
DS
NOTE:
R/W
CS
1. DNC - Do Not Connect
5708 drw04
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
TOP VIEW
PINDESCRIPTIONS
SYMBOL
NAME
I/O
DESCRIPTION
GND
VCC
Ground.
VCC
Ground Rail.
+5.0 Volt Power Supply.
DTA
Data Acknowledgment
(Open Drain)
O
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
RX0-7
RX Input 0 to 7
Frame Pulse
I
I
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
F0i
This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS® and GCI.
C4i
A0-A5
Clock
I
I
I
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT728985 internal registers.
Address 0 to 5
Data Strobe
DS
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
R/W
CS
Read/Write
I
I
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Active LOW input enabling a microprocessor read or write of control register or internal memories.
Chip Select
D0-D7
Data Bus 0 to 7
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX0-7
ODE
TX Outputs 0 to 7
(Three-state Outputs)
O
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
Output Drive Enable
I
This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
CCO
Control Channel Output
O
This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
2
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
functionsavailableintheIDT728985.Outputchannelsareselectedintospecific
modessuchas:ProcessorModeorConnectionmode,VariableorConstant
throughputdelaymodes,OutputDriversEnabledorinthree-statecondition.
Thereis alsoonebittocontrolthestateoftheCCOoutputpin.
ꢀUNCTIONALDESCRIPTION(Cont'd)
eight output (TX0-7) serial streams are provided in the IDT728985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. Theserialinterfaceclockforthedeviceis4.096MHz,asrequired
inST-BUS® andGCIspecifications.
OUTPUT DRIVE ENABLE (ODE)
The received serial data is internally converted to parallel by the on chip
serial-to-parallel converters and stored sequentially in a 256-position Data
Memory.Byusinganinternalcounterthatisresetbytheinput8KHzframepulse,
F0i,theincomingserialdatastreamscanbeframedandsequentiallyaddressed.
Dependingonthetypeofinformationtobeswitched,theIDT728985device
canbeprogrammedtoperformtimeslotinterchangefunctionswithdifferent
throughput delay capabilities on a per-channel basis. The Variable Delay
mode,mostcommonlyusedforvoiceapplications,canbeselectedensuring
minimumthroughputdelaybetweeninputandoutputdata.InConstantDelay
mode,usedinmultipleorgroupedchanneldataapplications,theintegrityofthe
informationthroughtheswitchismaintained.
TheODEpinisthemasteroutputthree-statecontrolpin. IftheODEinput
isheldLOWallTDM(TimeDivisionMultiplexed) outputswillbeplacedinhigh
impedanceregardlessConnectionMemoryHighprogramming. However,if
ODEisHIGH,thecontentsofConnectionMemoryHighcontroltheoutputstate
on a per-channel basis.
SERIAL INTERFACE TIMING
TheIDT728985masterclock(C4i)is4.096MHzsignalallowingserialdata
link configuration at 2.048 Mb/s to be implemented. The IDT728985 can
automaticallydetectthepresenceofaninputframepulse,identifythetypeof
backplanepresentontheserialinterface,andformatthesynchronizationpulse
accordingtoST-BUS® orGCIinterfacespecifications(activeHIGHinGCIor
activeLOWinST-BUS®). UpondeterminingthecorrectinterfaceConnected
totheserialport,theinternaltimingunitestablishestheappropriateserialdata
bittransmitandsamplingedges. InST-BUS® mode,everysecondfallingedge
ofthe 4.096MHzclockmarks a boundaryandthe inputdata is clockedinby
therisingedge,threequarters ofthewayintothebitcell. InGCImodeevery
secondrisingedgeofthe4.096MHzclockmarksthebitboundarywhiledata
sampling is performed during the falling edge, at three quarters of the bit
boundaries.
CONNECTIONMEMORY
Datatobeoutputontheserialstreamsmaycomefromtwosources:Data
MemoryorConnectionMemory. TheConnectionMemoryis splitintoHIGH
andLOWpartsandisassociatedwithparticularTXoutputstreams. InProcessor
Mode,dataoutputontheTXstreamsistakenfromtheConnectionMemoryLow
andoriginates fromthe microprocessor(Figure 2). Where as inConnection
Mode (Figure 1), data is read from Data Memory and originated from the
incomingRXstreams. Datadestinedforaparticularchannelontheserialoutput
streamisreadinternallyduringthepreviouschanneltimeslottoallowtimefor
memoryaccessandinternalparallel-to-serialconversion.
DELAYTHROUGHTHEIDT728985
Thetransferofinformationfromtheinputserialstreamstotheoutputserial
streamsresultsinadelaythroughthedevice. ThedelaythroughtheIDT728985
devicevariesaccordingtothemodeselectedintheV/CbitoftheConnection
MemoryHigh.
CONNECTIONMODE
InConnectionMode,theaddressesofinputsourceforalloutputchannels
are stored in the Connection Memory Low. The Connection Memory Low
locationsaremappedtocorresponding8-bitx32-channeloutputs.Thecontents
oftheDataMemoryattheselectedaddressarethentransferredtotheparallel-
to-serialconvertersbeforebeingoutput. Byhavingtheoutputchanneltospecify
theinputchannelthroughtheConnectionMemory,thesameinputchannelcan
bebroadcasttoseveraloutputchannels.
VARIABLEDELAYMODE
The delayinVariable DelayMode is dependentonlyonthe combination
ofsourceanddestinationontheinputandoutputstreams. Theminimumdelay
achievable in the IDT728985 device is three time slots. In the IDT728985
device,theinformationthatistobeoutputinthesamechannelpositionasthe
information is input (position n), relative to frame pulse, will be output in the
followingframe(channeln,framen+1). Thesameoccursiftheinputchannels
succeeding(n+1,n+2)thechannelpositionastheinformationisinput.
Theinformationswitchedtothethirdtimeslotaftertheinputhasenteredthe
device(forinstance,inputchannel0tooutputchannel3orinputchannel30to
outputchannel1),isalwaysoutputthreechannelslater.
PROCESSOR MODE
In Processor Mode the CPU writes data to the Connection Memory Low
locationswhichcorrespondtotheoutputlinkandchannelnumber. Thecontents
of the Connection Memory Low are transferred to the parallel-to-serial
converteronechannelbeforeitistobeoutputandaretransmittedeachframe
totheoutputuntilitis changedbytheCPU.
Anyswitchingconfigurationthatprovidesthreeormoretimeslotsbetween
inputandoutputchannels,willhaveathroughputdelayequaltothedifference
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
Data
Memory
Data
Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
TX
RX
TX
Connection
Memory
Connection
Memory
5708 drw06
5708 drw05
Microprocessor
Figure 1. Connection Mode
Figure 2. Processor Mode
3
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
betweentheoutputandinputchannels;i.e.,thethroughputdelaywillbeless mode(Bit7oftheControlregister)readsarefromtheDataMemoryandwrites
thanoneframe. Table1showsthepossibledelaysfortheIDT728985device are to the Connection Memory LOW. The Memory Select bits allow the
in Variable Delay Mode. An example is shown in Figure 3.
ConnectionMemoryHighorLOWortheDataMemorytobechosen,andthe
StreamAddressbitsdefineinternalmemorysubsectionscorrespondingtoinput
oroutputstreams.
CONSTANTDELAYMODE
The Processor Enable bit (bit 6) places every output channel on every
outputstreaminProcessorMode;i.e.,thecontentsoftheConnectionMemory
LOW(CML,Table5)areoutputontheoutputstreamsonceeveryframeunless
theODEinputpinisLOW.IfPEbitisHIGH,thentheIDT728985behavesas
ifbits2(ChannelSource)and0(OutputEnable)ofeveryConnectionMemory
High(CMH)locationsweresettoHIGH,regardlessoftheactualvalue. IfPE
is LOW,thenbit2and0ofeachConnectionMemoryHighlocationoperates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channelisinProcessorMode. Ifbit2oftheCMHisLOW,thenthecontentsof
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
is tobe switchedtoanoutput, Table 4.
Inthismodeframeintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipleDataMemorybuffertechniquewhereinputchannels
writteninanyofthebuffersduringframeNwillbereadoutduringframeN+2.
IntheIDT728985,theminimumthroughputdelayachievableinConstantDelay
modewillbe32timeslots;forexample,wheninputtimeslot32(channel31)is
switched to output time slot 1 (channel 0). Likewise, the maximum delay is
achievedwhenthefirsttimeslotinaframe(channel0)isswitchedtothelasttime
slotintheframe(channel31),resultingin94timeslotsofdelay(seeFigure4).
Tosummarize,anyinputtimeslotfrominputframeNwillbealwaysswitched
tothedestinationtimeslotonoutputframeN+2. InConstantDelaymodethe
devicethroughputdelayiscalculatedaccordingtothefollowingformula:
IftheODEinputpinisLOW,thenalltheserialoutputsarehigh-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
ordisables(ifLOW)forthatparticularchannel.
DELAY=[32+(32-IN)+(OUT-1)]
Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see
Table4)isoutputonCCOpinonceeveryframe. TheCCOpinisa2.048Mb/s
output,whichcarries256bits. IfCCObitissetHIGH,thecorrespondingbiton
CCOoutputistransmittedHIGH. IfCCOisLOW,thecorrespondingbitonthe
CCOoutputistransmittedLOW. Thecontentsofthe256CCObitsoftheCMH
aretransmittedsequentiallyontotheCCOoutputpinandaresynchronousto
theTXstreams. Toallowfordelayinanyexternalcontrolcircuitrythecontents
oftheCCObitisoutputonechannelbeforethecorrespondingchannelonthe
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding
toTX0,CH0),istransmittedsynchronouslywiththeTXchannel31,bit7.Bit1's
ofCMHforchannel1ofstreams0-7areoutputsynchronouslywithTXchannel
0 bits 7-0.
IN=thenumberoftheinputtimeslot(from1to32)
OUT=thenumberoftheoutputtimeslot(from1to32).
MICROPROCESSORPORT
TheIDT728985microprocessorportis anon-multiplexedbusarchitecture.
Theparallelportconsistsofan8-bitparalleldatabus(D0-D7),sixaddressinput
lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel
microportallowstheaccesstotheControlRegisters,ConnectionMemoryLow,
ConnectionMemoryHigh,andtheDataMemory. Alllocationsareread/written
except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
MemoryaremultiplexedwithaccessesfromtheinputandoutputTDMports.
ThiscancausevariableDataAcknowledgedelays(DTA). IntheIDT728985
device,theDTAoutputprovidesamaximumacknowledgmentdelayof800ns
forread/writeoperationsintheConnectionMemory. However,foroperations
intheDataMemory(ProcessorMode),themaximumacknowledgmentdelay
can be 1220ns.
INITIALIZATION
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
intothehighimpedancestate. CareshouldbetakenthatnotwoConnectedTX
outputsdrivethebussimultaneously. TheODEpinshouldbeheldlowonpower
up to keep all output pins in high-impedance. With the CMH setup, the
microprocessor controlling the matrices can bring the ODE signal high to
relinquishhighimpedancestatecontroltotheConnectionMemoryHighbits
outputs.
SOꢀTWARECONTROL
IftheA5,A1,A0addresslineinputsareLOWthentheIDT728985Internal
ControlRegisteris addressed(seeTable2). IfA5inputlineis high,thenthe
remainingaddressinputlinesareusedtoselectthe32possiblechannelsper
inputoroutputstream. As explainedintheControlRegisterdescription,the
addressinputlinesandtheStreamAddressbits(STA)oftheControlregister
give the userthe capabilityofselectingallpositions ofIDT728985Data and
Connectmemories. SeeFigure6foraccessinginternalmemories.
The data in the control register consists of Memory Select and Stream
Addressbits,SplitMemoryandProcessorEnablebits(Table3).InSplitMemory
TABLE2 ADDRESSMAPPING
A5
A4
A3
A2
A1
A0
LOCATION
0
1
1
1
1
1
1
1
1
X
0
0
•
X
0
0
•
X
0
0
•
0
0
0
•
0
0
1
•
Control Register(1)
Channel 0(2)
Channel 1(2)
TABLE 1 VARIABLE DELAY MODE
•
Input Channel
Output Channel
Throughput Delay
•
•
•
•
•
•
n
n
n
m=n, n+1 or n+2
m>n+2
m-n+32time slot
m-ntimeslot
•
•
•
•
•
•
•
•
•
•
•
•
m<n
32-(n-m) time slot
•
•
•
•
•
•
1
1
1
1
1
Channel 31(2)
4
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
Incoming Now
Outgoing Next
Outgoing Now
Time Slot 32 31 30 29 28............ 3 2 1
32 31........7
6
5
4
3
2
J
1
J
32 31.........7 6
G H
5
I
4
3
2 1 Time Slot
J
A
B
C
D
E
F
G
H
I
J
J
32 Slots
32 Slots
32 Slots
For J: DELAY=3 Slots, 32 Slots, 33 Slots, and 34 Slots
For G, H, and I: DELAY= 3 slots
Figure 3. Variable Delay Mode
Incoming
Switching
Outgoing
Time Slot 32 31 30 29 28............ 3 2 1
32 31 30 29 28............. 3 2 1 Time Slot
A
B
C
D
E
F
G
H
I
J
J
I
H
G
F
E
D C B A
32 Slots
32 Slots
32 Slots
5708 drw07
For Slot 1 ("A"): IN=32, OUT=1, DELAY=(32-32)+32+(1-1)=32 time slots minimum delay
For Slot 32 ("J"): IN=1, OUT=32, DELAY=(32-1)+32+(32-1)=94 time slots maximum delay
Figure 4. Constant Delay Mode
5
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0
Control Register
b
b
b
b
b
b
b
b
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
CR 4 CR 3
b
b
When A5 =1, only 32 bytes are randomly accessable via
A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
0
1
1
1
0
1
Connection Memory High
Connection Memory Low
Data Memory
CR 2 CR 1 CR 0
Stream
b
b
b
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
0
0
0
0
1
2
0
0
0
1
1
0
1
0
1
0
1
1
1
0
0
3
4
5
1
1
1
1
0
1
6
7
111111
External Address Bits A5-A0
100000
100001
100010
5708 drw08
Figure 6. Addressing Internal Memories
6
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
TABLE3 CONTROLREGISTER
7
6
5
4
3
2
1
0
SM
PE
X
MS1
MS0 STA2 STA1 STA0
Bit
Name
Description
7
SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except when
the Control Register is accessed again. The Memory Select bits need to specify the memory for the operations.
6
PE (Processor Mode)
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when in high-
impedance. When 0, the Connection Memory bits for each channel determine what is output.
5
unused
4-3
MS1-MS0
0-0 - Not to be used.
(Memory Select Bits)
0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2-0
STA2-0
(Stream Address Bits)
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
subsection of memory made accessible for subsequent operations.
x = don't care
TABLE 4 CONNECTION MEMORY HIGH
7
6
5
4
3
2
1
0
X
V/C
X
X
X
CS
CCO
OE
Bit
7,5,4,3
6
Name
Description
unused
V/C (Variable/Constant
Throughput Delay Mode)
This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis.
2
CS
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
(Channel Source)
1
0
CCO (CCO Bit)
This bit drives a bit time on the CCO output pin.
OE (Output Enable)
This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to
bemadehigh-impedance,allowingswitchmatrices tobeconstructed.AHIGHenables thedriverandaLOWdisables it.
x = don't care
TABLE 5 CONNECTION MEMORY LOW
7
6
5
4
3
2
1
0
SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0
Bit
7-5 SAB2-0(1)
(Source Stream Address Bits)
4-0(1) CAB2-0(1)
Name
Description
These three bits are used to select eight source streams for the Connection.
These five bits are used to select 32 different source channels for the Connection (the stream where the channel
(Source Channel Address Bits) is present is defined by bits SAB2-0). Bit 4 is the most significant bit.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the Connection which is output on the channel and stream associated with this location.
7
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS
Symbol Parameter
Min.
Max.
Unit
Symbol
Parameter
Min. Typ.(1) Max.
Unit
V
VCC - GND
-0.3
7
V
V
VCC
Positive Supply
InputVoltage
4.75
0
5.0
5.25
VCC
+85
Vi
VO
VoltageonDigitalInputs
GND - 0.3 VCC +0.3
GND - 0.3 VCC +0.3
40
VI
V
VoltageonDigitalOutputs
CurrentatDigitalOutputs
StorageTemperature
V
TOP
OperatingTemperature
Commercial
-40
25
°C
IO
mA
° C
W
TS
-65
+150
2
NOTE:
PD
PackagePowerDissapation
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject
to production testing.
NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
ICC
Parameter
Min.
Typ.(1)
Max.
Units
mA
V
Test Conditions
SupplyCurrent
7
10
OutputsUnloaded
VIH
VIL
InputHighVoltage
InputLowVoltage
2.0
0.8
5
V
IIL
InputLeakage(Inputs)
InputLeakage(I/Opins)
InputCapacitance
µA
µA
pF
VI between GND and VCC
IIL
34
8
100
CI
VOH
IOH
VOL
IOL
OutputHighVoltage
OutputHighCurrent
OutputLowVoltage
OutputLowCurrent
HighImpedanceLeakage
OutputPinCapacitance
2.4
10
V
IOH = 10mA
Sourcing. VOH = 2.4V
IOL = 5mA
15
10
8
mA
V
0.4
5
5
mA
µA
pF
Sinking. VOL = 0.4V
VO between GND and VCC
IOZ
CO
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
S1isopencircuitexceptwhentestingoutput
levelsorhighimpedancestates.
R
L
Output
Pin
S
2
S
1
C
L
S2is switchedtoVCC orGNDwhentesting
outputlevelsorhighimpedancestates.
GND
GND
5708 drw09
Figure 6. Output Load
8
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
ACELECTRICALCHARACTERISTICS(1) ST-BUS® TIMING
Symbol
tF0iW
tF0iS
tF0iH
tDAA
tSTiS
tSTiH
tC4i
Parameter
Min.
Typ.(2)
Max.
Units
ns
Test Conditions
FramePulseWidth
FramePulseSetupTime
FramePulseHoldTime
TX delay Active to Active
RXSetupTime
244
OutputsLoaded
10
20
190
190
60
ns
ns
ns
40
CL = 150pF
20
20
ns
RXHoldTime
ns
Clock Period
200
85
244
122
122
300
150
150
10
ns
tCL
CK Input Low
ns
tCH
CK Input High
85
ns
ns
tr,tf
ClockRise/FallTime
NOTE:
1. Timing is over recommended temperature and power supply voltages (VCC=5V±5%, GND=0V, TA=40°C to 85°C).
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
tF0iW
F0i
C4i
t
CH
t
CL
tF0iS
tF0iH
tC4i
tDAA
tf
tr
TX
RX
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
Ch. 0, Bit 5
Ch. 0,
Bit 5
t
STiS
tSTiH
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
5708 drw 10
Figure 7. ST-BUS® Timing
9
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) GCI TIMING
Symbol
tC4i
Parameter
Min.
150
73
Typ.(2)
Max.
300
Units
ns
Test Conditions
Clock Period
244
OutputsLoaded
tCL, tCH
tWFH
tF0iS
PulseWidth
122
150
ns
FrameWidthHigh
FrameSetup
244
ns
ns
10
20
190
190
60
tF0iH
FrameHold
ns
tDAA
Data Delay/Clock Active to Active
SerialInputSetup
SerialInputHold
ClockRise/FallTime
40
ns
CL = 150pF
tSTiS
20
20
ns
tSTiH
tr,tf
ns
10
ns
NOTE:
1. Timing is over recommended temperature and power supply voltages (VCC=5V±5%, GND=0V, TA=40°C to 85°C).
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
tWFH
F0i
C4i
tF0iS
tF0iH
tr
tf
tCL
t
CH
t
C4i
TX
RX
Ch. 31
Bit 7
Ch. 0
Bit 0
Ch. 0
Bit 1
Bit 1
tDAA
tSTiS
tSTiH
Ch. 31
Bit 7
Ch. 0
Bit 0
Ch. 0
5708 drw11
Figure 8. GCI Timing
10
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) SERIAL STREAM TIMING
Symbol
tTAZ
Characteristics
Min.
Typ.(2)
Max.
60
Unit
ns
Test Conditions
RL = 1KΩ(3), CL = 150pF
CL = 150pF
TX0-7 Delay - Active to High Z
TX0-7 Delay - High Z to Active
OutputDriverEnableDelay
CCO Output Delay
40
tTZA
40
60
ns
tOED
40
60
ns
RL = 1KΩ(3), CL = 150pF
tXCD
0
20
40
ns
CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Bit Cell Boundary
(GCI)
C4i
(ST-BUS )
tTAZ
TX0-7
TX0-7
CCO
t
TZA
ODE
tOED
tOED
t
XCD
TX0-7
5708 drw13
5708 drw12
Figure 9. Serial Outputs and External Control
Figure 10. Output Driver Enable
11
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
ACELECTRICALCHARACTERISTICS(1) MICROPROCESSORTIMING
Symbol
tCSS
Characteristics
Min.
0
Typ.(2)
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
CS Setup from DS Rising
R/W Setup from DS Rising
AddSetupfromDSRising
CS Hold after DS Falling
R/WHold after DS Falling
AddHoldafterDSFalling
Data SetupfromDTA LowonRead
DataHoldonRead
tRWS
tADS
5
5
tCSH
tRWH
tADH
tDDR
0
5
5
10
10
10
CL = 150pF
RL = 1KΩ(3), CL = 150pF
tDHR
50
90
tDSW
tSWD
tDHW
tAKD
DataSetuponWrite(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldonWrite
122
8
AcknowledgmentDelay:
CL = 150pF
ReadingDataMemory
560
300/370
40
1220
730/800
70
ns
ns
ns
ns
Reading/WritingConnectionMemory
WritingtoControlRegister
ReadingtoControlRegister
40
70
tAKH
AcknowledgmentHoldTime
10
20
50
ns
RL = 1KΩ(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
CS
tCSH
tCSS
t
RWH
t
RWS
R/W
tADH
tADS
A0-A5
D0-D7
READ
VALID DATA
t
SWD
t
DHR
t
DSW
VALID DATA
D0-D7
WRITE
t
DHW
AKH
t
DDR
t
t
AKD
DTA
5708 drw14
Figure 11. Motorola Non-Multiplexed Bus Timing
12
ORDERINGINꢀORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Plastic Leaded Chip Carrier (PLCC, J44-1)
Plastic Dip (P40-1)
Plastic Quad Flatpack (PQFP, DB44-1)
J
P
DB
728985
256 x 256
Time Slot Interchange Digital Switch
5708 drw15
DATASHEETDOCUMENTHISTORY
5/08/2000
6/05/2000
8/18/2000
01/24/2001
04/05/2001
pg. 1
pgs. 1, 2, 12 and 13.
pg. 2
pgs. 1 and 8.
pg. 10
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The IDT logo is a registered trademark of Integrated Device Technology, Inc. and the ST-BUS® is a trademark of Mitel Corp.
13
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