72P51339L6BBGI [IDT]
FIFO, 16KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256;
| 型号： | 72P51339L6BBGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 16KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总87页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8VMULTI-QUEUEFLOW-CONTROLDEVICES
(8QUEUES)36BITWIDECONFIGURATION
589,824bits
1,179,648bits
2,359,296bits
IDT72P51339
IDT72P51349
IDT72P51359
IDT72P51369
4,718,592bits
– x36 in to x36 out
– x36in to x18out
– x36in to x9out
User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL
100% Bus Utilization, Read and Write on every clock cycle
Selectable First Word Fall Through (FWFT) or IDT standard
mode of operation
Ability to operate on packet or word boundaries
Mark and Re-Write operation
– x18 in to x36 out
– x18 in to x18 out
– x18 in to x9 out
– x9 in to x36 out
– x9 in to x18 out
– x9 in to x9 out
FEATURES
•
Choose from among the following memory density options:
IDT72P51339
IDT72P51349
IDT72P51359
IDT72P51369
Total Available Memory = 589,824 bits
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
Total Available Memory = 4,718,592 bits
•
•
•
•
•
•
Configurable from 1 to 8 Queues
•
•
•
•
•
•
•
Default configuration of 8 or 4 symmetrical queues
Default multi-queue device configurations
– IDT72P51339: 2,048 x 36 x 8Q
Mark and Re-Read operation
Individual, Active queue flags (OR / EF, IR / FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Direct or polled operation of flag status bus
Expansion of up to 64 queues and/or 32Mb logical configura-
tion using up to 8 multi-queue devices in parallel
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
Green parts available, see Ordering Information
– IDT72P51349: 4,096 x 36 x 8Q
– IDT72P51359: 8,192 x 36 x 8Q
– IDT72P51369: 16,384 x 36 x 8Q
•
•
Default configuration can be augmented via the queue address
bus
Number of queues and individual queue sizes may be
configured at master reset though serial programming
200 MHz High speed operation (5ns cycle time)
3.6ns access time
•
•
•
•
•
•
•
•
•
Independent Read and Write access per queue
User Selectable Bus Matching Options:
FUNCTIONALBLOCKDIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
RADEN
ESTR
Q7
WADEN
FSTR
RDADD
WRADD
8
8
REN
RCLK
RCS
WEN
Q6
Q5
WCLK
WCS
OE
Q
out
x36, x18 or x9
DATA OUT
D
in
x36, 18 or x9
DATA IN
EF/OR
FF/IR
PAF
PR
PAE
Q0
PAFn
PAEn
PRn
8
8
6716 drw01
CIDTOandMtheMIDTElogRoaCretrIaAdemLarksAofInNtegDratedIDNevicDeTUechSnolTogyR,InIcAL TEMPERATURE RANGES
AUGUST 2005
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6716/3
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Table of Contents
Features ........................................................................................................................................................................................................................ 1
Description ................................................................................................................................................................................................................... 5
Pin configuration ......................................................................................................................................................................................................... 7
Detailed Description .................................................................................................................................................................................................... 8
Pin Descriptions ......................................................................................................................................................................................................... 10
Pin number table ........................................................................................................................................................................................................ 16
Recommended DC operating conditions ................................................................................................................................................................ 17
Absolute maximum ratings ........................................................................................................................................................................................ 17
DC electrical characteristics ..................................................................................................................................................................................... 18
AC electrical characteristics ...................................................................................................................................................................................... 20
Functional description .............................................................................................................................................................................................. 22
Serial Programming.............................................................................................................................................................................................. 23
Default Programming ............................................................................................................................................................................................ 23
Parallel Programming ........................................................................................................................................................................................... 23
Queue Description ..................................................................................................................................................................................................... 25
Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25
Standard mode operation ..................................................................................................................................................................................... 26
Read Queue Selection and Read Operation ......................................................................................................................................................... 27
Switching Queues on the Write Port ...................................................................................................................................................................... 29
Switching Queues on the Read Port ..................................................................................................................................................................... 31
Flag Description......................................................................................................................................................................................................... 42
PAFn Flag Bus Operation ..................................................................................................................................................................................... 42
Full Flag Operation............................................................................................................................................................................................... 42
Empty or Output Ready Flag Operation (EF/OR) .................................................................................................................................................. 42
Almost Full Flag .................................................................................................................................................................................................... 43
Almost Empty Flag ................................................................................................................................................................................................ 43
Packet Ready Flag............................................................................................................................................................................................... 47
Packet Mode Demarcation bits .............................................................................................................................................................................. 49
JTAG Interface ............................................................................................................................................................................................................ 82
JTAGAC electrical characteristics ............................................................................................................................................................................ 86
Ordering Information ................................................................................................................................................................................................. 87
List of Tables
Table 1 — Device programming mode comparison ........................................................................................................................................................ 22
Table 2 — Setting the queue programming mode during master reset ............................................................................................................................. 22
Table 3 — Mode Configuration ...................................................................................................................................................................................... 25
Table 4 — WriteAddress Bus, WRADD[7:0]................................................................................................................................................................... 26
Table 5 — ReadAddress Bus, RDADD[7:0] .................................................................................................................................................................. 27
Table 6 — Write Queue Switch Operation ...................................................................................................................................................................... 30
Table 7 — Read Queue Switch Operation ..................................................................................................................................................................... 32
Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32
Table 9 — Flag operation boundaries and Timing .......................................................................................................................................................... 45
Table 10 — Packet Mode Valid Byte for x36 bit word configuration ................................................................................................................................. 48
Table 11 — Bus-Matching Set-Up .................................................................................................................................................................................. 52
AUGUST4,2005
2
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
List of Figures
Figure 1. Multi-Queue Flow-Control Device Block Diagram .............................................................................................................................................. 6
Figure 2a. AC Test Load................................................................................................................................................................................................ 19
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 19
Figure 3. Reference Signals .......................................................................................................................................................................................... 22
Figure 4. Device Programming Hierarchy ..................................................................................................................................................................... 24
Figure 5. IDT Standard mode illustrated (Read Port) ..................................................................................................................................................... 25
Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port) ........................................................................................................................ 25
Figure 7. Write Port Switching Queues Signal Sequence ................................................................................................................................................ 29
Figure 8. Switching Queues Bus Efficiency ..................................................................................................................................................................... 29
Figure 9. Simultaneous Queue Switching ....................................................................................................................................................................... 30
Figure 10. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 31
Figure 11. Switching Queues Bus Efficiency ................................................................................................................................................................... 31
Figure 12. Simultaneous Queue Switching ..................................................................................................................................................................... 32
Figure 13. MARK and Re-Write Sequence .................................................................................................................................................................... 33
Figure 14. MARK and Re-Read Sequence ................................................................................................................................................................... 33
Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK ............................................................................................................................. 34
Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK ............................................................................................................................ 34
Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK ................................................................................................................ 35
Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK ............................................................................................................... 35
Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK ............................................................................................................................... 37
Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK .............................................................................................................................. 37
Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK .................................................................................................................. 38
Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK ................................................................................................................. 38
Figure 23. Leaving a MARK active on the Write Port ...................................................................................................................................................... 39
Figure 24. Leaving a MARK active on the Read Port ..................................................................................................................................................... 39
Figure 25. Inactivating a MARK on the Write PortActive ................................................................................................................................................. 40
Figure 26. Inactivating a MARK on the Read PortActive ................................................................................................................................................ 40
Figure 27. 36bit to 36bit word configuration .................................................................................................................................................................... 49
Figure 28. 36bit to 18bit word configuration .................................................................................................................................................................... 49
Figure 29. 36bit to 9bit word configuration ...................................................................................................................................................................... 49
Figure 30. 18bit to 36bit word configuration .................................................................................................................................................................... 50
Figure 31. 18bit to 18bit word configuration .................................................................................................................................................................... 50
Figure 32. 18bit to 9bit word configuration ...................................................................................................................................................................... 50
Figure 33. 9bit to 36bit word configuration ...................................................................................................................................................................... 51
Figure 34. 9bit to 18bit word configuration ...................................................................................................................................................................... 51
Figure 35. 9bit to 9bit word configuration ........................................................................................................................................................................ 51
Figure 36. Bus-Matching ByteArrangement ................................................................................................................................................................... 53
Figure 37. Master Reset ................................................................................................................................................................................................ 54
Figure 38. Default Programming .................................................................................................................................................................................... 55
Figure 39. Parallel Programming ................................................................................................................................................................................... 56
Figure 40. Queue Programming via WriteAddress Bus .................................................................................................................................................. 57
Figure 41. Queue Programming via ReadAddress Bus ................................................................................................................................................. 57
Figure 42. Serial Port Connection for Serial Programming .............................................................................................................................................. 57
Figure 43. Serial Programming ...................................................................................................................................................................................... 58
Figure 44. Write Queue Select, Write Operation and Full Flag Operation ........................................................................................................................ 59
Figure 45. Write Queue Select and Mark ....................................................................................................................................................................... 60
Figure 46. Write Operations in First Word Fall Through mode ....................................................................................................................................... 61
Figure 47. Full Flag Timing in Expansion Configuration.................................................................................................................................................. 62
Figure 48. Read Queue Select, Read Operation (IDT mode) ......................................................................................................................................... 63
Figure 49. Read Queue Select, Read Operation (FWFT mode) ..................................................................................................................................... 64
Figure 50. Read Queue Select and Mark (IDT mode).................................................................................................................................................... 65
Figure 51. Output Ready Flag Timing (In FWFT Mode) ................................................................................................................................................. 66
Figure 52. Read Queue Selection with Read Operations (IDT mode)............................................................................................................................. 67
Figure 53. Read Queue Select, Read Operation and OE Timing .................................................................................................................................... 68
Figure 54. Writing in Packet Mode during a Queue change ............................................................................................................................................ 69
AUGUST4,2005
3
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
List of Figures (Continued)
Figure 55. Reading in Packet Mode during a Queue change ......................................................................................................................................... 70
Figure 56. Writing Demarcation Bits (Packet Mode) ........................................................................................................................................................ 71
Figure 57. Data Output (Receive) Packet Mode of Operation ......................................................................................................................................... 72
Figure 58.Almost Full FlagTiming and Queue Switch .................................................................................................................................................... 73
Figure 59.Almost Full Flag Timing ................................................................................................................................................................................. 73
Figure 60.Almost Empty FlagTiming and Queue Switch (FWFTmode) ......................................................................................................................... 74
Figure 61.Almost Empty FlagTiming ............................................................................................................................................................................. 74
Figure 62. PAEn/PRn - Direct Mode - Status Word Selection ......................................................................................................................................... 75
Figure 63. PAFn - Direct Mode - Status Word Selection ................................................................................................................................................. 75
Figure 64. PAEn - Direct Mode, Flag Operation............................................................................................................................................................. 76
Figure 65. PAFn - Direct Mode, Flag Operation............................................................................................................................................................. 77
Figure 66. PAFn Bus - Polled Mode .............................................................................................................................................................................. 78
Figure 67. Expansion using ID codes ............................................................................................................................................................................ 79
Figure 68. Expansion using WCS/RCS ......................................................................................................................................................................... 80
Figure 69. Expansion Connection Read Chip Select (RCS) ........................................................................................................................................... 81
Figure 70. Expansion Connection Write Chip Select (WCS) ........................................................................................................................................... 81
Figure 71. Boundary ScanArchitecture ......................................................................................................................................................................... 82
Figure 72. TAPController State Diagram ....................................................................................................................................................................... 83
Figure 73. Standard JTAGTiming.................................................................................................................................................................................. 86
AUGUST4,2005
4
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
withinaqueueisavailableforreading.ThePacketReadyindicatorisgenerated
upondetectionofthestartandendofpacketdemarcationbits.Themulti-queue
devicethenprovidestheuserwithaninternallygeneratedpacketreadystatus
per queue.
DESCRIPTION
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
troldevicesaresinglechipswithupto32discreteconfigurableFIFOqueues.
Allqueues withinthe device have a commondata inputbus, (write port)and
acommondataoutputbus,(readport).Datawrittenintothewriteportisdirected
toaspecificqueueviaaninternalde-multiplexoperation,addressedbythewrite
addressbus(WRADD).Datareadfromthereadportisaccessedfromaspecific
queueviaaninternalmultiplexoperation,addressedbythereadaddressbus
(RDADD). Data writes and reads can be performed at high speeds up to
200MHz,withaccesstimesof3.6ns.Datawriteandreadoperationsaretotally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
simultaneously.
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueuesbetween1and32,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
Iftheuserdoesnotwishtoprogramthemulti-queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
AMasterResetmustbeprovidedtothedevice.AMasterResetlatchesin
configuration/setuppinsandmustbeperformedbeforefurtherprogrammingof
thedevicecantakeplace.Ontherisingedgeofmasterresetthedeviceoperating
modeisset,thedeviceprogrammingmode(serial,parallelordefault)issetand
theexpansionconfigurationdevicetype(masterorslave)is set.
Themulti-queueflow-controldevicehasthecapabilityofoperatingitsI/Oin
either2.5VLVTTL,1.5VHSTLor1.8VeHSTLmode.ThetypeofI/Oisselected
viatheIOSELinput.Thecoresupplyvoltage(VDD)tothemulti-queueis1.8V,
however the output levels can be set independently via a separate supply,
VDDQ.
ThedeviceprovidesFullflagandEmptyflagstatusforthequeueselected
forwriteandreadoperationsrespectively.AlsoaProgrammableAlmostFull
andProgrammableAlmostEmptyflagforeachqueueis provided. Two8bit
programmable flag busses are available, providing status of queues not
selectedforwrite orreadoperations. When8orless queues are configured
inthedevicetheseflagbussesprovideanindividualflagperqueue,whenmore
than8queuesareused,eitheraPolledorDirectmodebusoperationprovides
theflagbusseswithallqueuesstatus.
BusMatchingisavailableonthisdevice,eitherportcanbe9bits,18bitsor
36bitswide.WhenBusMatchingisusedthedeviceensuresthelogicaltransfer
ofdatathroughputinaLittleEndianmanner.
Apacketmodeofoperationisalsoprovided.Packetmodeprovidesapacket
readyflagoutput(PR)indicatingwhenatleastone(ormore)packetsofdata
AJTAGtestportisprovided,herethemulti-queueflow-controldevicehas
afullyfunctionalBoundaryScanfeature,compliantwithIEEE1149.1Standard
TestAccessPortandBoundaryScanArchitecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an
outlineofthefunctionalblockswithinthedevice.
AUGUST4,2005
5
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D
D
, D , D = TEOP
D
35 17
8
in
x9, x18, x36
- D
, D , D = TSOP
2
34 16
8
D
0
35
WCLK
WEN WCS
TMS
TDI
INPUT
DEMUX
JTAG
Logic
TDO
TCK
8
WRADD
WADEN
Write Control
Logic
TRST
Write Pointers
PR
Packet
Mode Logic
8
PAF
PRn/PAEn
FSTR
PAFn
8
General Flag
Monitor
FSYNC
Upto 8
FIFO
Queues
FXO
FXI
EF/OR
Active Q
Flags
PAE
4.7 Mbit
Dual Port
Memory
Active Q
Flags
FF/IR
PAF
PAE
SI
SO
SCLK
General Flag
Monitor
Serial
Multi-Queue
Programming
ESTR
ESYNC
EXI
SENI
SENO
EXO
Read Pointers
FM
8
4
Reset
Logic
BM[3:0]
RDADD
RADEN
RCS
Read Control
Logic
MAST
PKT
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
2
Offset
D
, D , D = REOP
35 17
DFM
8
D
, D , D = RSOP
34 16
8
OUTPUT
REGISTER
MRS
6714 drw02
IOSEL
Vref
IO Level Control
OE
Q
- Q
0
35
Q
x9, x18, x36
out
Figure 1. Multi-Queue Flow-Control Device Block Diagram
AUGUST4,2005
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IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D17
D20
D23
D26
D29
D32
BM3
QSEL1
SI
D13
D16
D12
D11
D19
D22
D25
D28
D31
D34
D35
VREF
D10
D9
Q9
Q8
Q7
Q15
Q19
D7
D6
D5
D4
D3
D2
D1
D0
TCK
TMS
TDO
TDI
ID2
ID1
ID0
Q3
Q2
Q1
Q6
Q5
Q4
Q12
Q11
Q10
Q16
Q24
Q14
Q13
Q17
Q21
Q23
B
C
D
E
F
D18
D8
TRST
IOSEL
Q0
Q18
Q20
Q22
D21
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VCC
V
CC
GND
GND
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VDDQ
VDDQ
GND
GND
D24
VDDQ
VCC
VDDQ
VCC
GND
VCC
VDDQ
D27
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Q27
Q30
Q25
Q28
Q26
Q29
G
H
J
D30
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
D33
VCC
GND
GND
VCC
Q33
PKT
GND
Q32
Q31
Q34
FM
GND
GND
QSEL0
GND
VCC
VCC
Q35
K
L
VCC
VCC
VCC
MAST
VCC
GND
GND
VDDQ
VCC
DFM
DF
SO
VCC
VDDQ
BM2
BM1
BM0
M
N
P
R
T
SENO
SENI
OE
VDDQ
RDADD0 RDADD1
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VDDQ
VDDQ
WRADD1 WRADD0 SCLK
RDADD2 RDADD3 RDADD4
RDADD5 RDADD6 RDADD7
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
V
DDQ
V
DDQ
PAE3
PAE2
PAE1
WRADD4 WRADD3 WRADD2 WADEN
PAF3
PAF2
PAF1
PAF6
PAF5
WEN
PAF7
IR/FF
PAF
OR/EF
PR
PAE
RCS
PAE6
PAE5
PAE4
PAE7
FWFT
REN
WRADD6 WRADD5 FSYNC
ESTR ESYNC
RADEN
FSTR
PAF4
EXO
EXI
WRADD7 FXI
FXO
WCS
MRS
RCLK
PAE0
PAF0
WCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6716 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
AUGUST4,2005
7
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
provides a user programmable almost full flag for all 8 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
forthatqueue.Conversely,thereadporthasanEmptyflag,providingstatus
ofthedatabeingreadfromthequeueselectedonthereadport.Aswellasthe
Emptyflagthedeviceprovidesadedicatedalmostemptyflag.Thisalmostempty
flagissimilartothealmostemptyflagofaconventionalIDTFIFO.Thedevice
providesauserprogrammablealmostemptyflagforeach8queuesandwhen
arespectivequeueisselectedonthereadport,thealmostemptyflagprovides
statusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
singledataoutputportwithupto32FIFOqueuesinparallelbufferingbetween
thetwoports.Theusercansetupbetween1and8queueswithinthedevice.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independentofoneanother.
MEMORYORGANIZATION/ALLOCATION
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual
queuesizestheusermustallocatethememorytorespectivequeues,inunits
ofblocks,thatis,asinglequeuecanbemadeupfrom0tomblocks,wherem
isthetotalnumberofblocksavailablewithinadevice.Alsothetotalsizeofany
given queue must be in increments of 256 x36. For the IDT72P51339,
IDT72P51349,IDT72P71759andIDT72P51369theTotalAvailableMemory
is128,256,and512blocksrespectively(ablockbeing256x36).Queuescan
bebuiltfromtheseblockstomakeanysizequeuedesiredandanynumberof
queuesdesired.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandOutput
Ready&almostemptyonthereadport,therearetwoflagstatus busses.An
almostfullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostempty
flagstatusbusisprovided,againthisbusis8bitswide.Thepurposeofthese
flagbussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby
the user) for each of the 8 queues in the device.
BUS WIDTHS
In the IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-
controldevicestheuserhastheoptionofutilizinganywherebetween1and8
queues,thereforethe8bitflagstatus busses aremultiplexedbetweenthe8
queues,aflagbuscanonlyprovidestatusfor2ofthe8queuesatanymoment,
thisisreferredtoasa“StatusWord”,suchthatwhenthebusisprovidingstatus
ofqueues1through8,thisisstatusword1,whenitisqueues9through16,this
isstatusword2andsoonuptostatusword16.Iflessthan8queuesaresetup
inthedevice,therearestill4statuswords,suchthatin“Polled”modeofoperation
theflagbuswillstillcyclethrough4statuswords.Ifforexampleonly22queues
aresetup,statuswords1and2willreflectstatusofqueues1through8and9
through16respectively.Statusword3willreflectthestatusofqueues17through
22ontheleastsignificant6bits,themostsignificant2bitsoftheflagbusaredon’t
care.Theremainingstatuswordsarenotusedastherearenoqueuestoreport.
The flag busses are available in two user selectable modes of operation,
“Polled”or“Direct”.Whenoperatinginpolledmodeaflagbusprovidesstatus
ofeachstatuswordsequentially,thatis,oneachrisingedgeofaclocktheflag
busisupdatedtoshowthestatusofeachstatuswordinorder.Therisingedge
ofthewriteclockwillupdatethealmostfullbus andarisingedgeontheread
clockwillupdatethealmostemptybus.Themodeofoperationisalwaysthesame
forboththealmostfullandalmostemptyflagbusses.Whenoperatingindirect
mode,thestatuswordontheflagbusisselectedbytheuser.Sotheusercan
actuallyaddressthestatuswordtobeplacedontheflagstatusbusses,these
flagbussesoperateindependentlyofoneanother.Addressingofthealmostfull
flagbusisdoneviathewriteportandaddressingofthealmostemptyflagbus
is done via the read port.
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
andoutputportcanbeeitherx9,x18orx36bits wide,thereadandwriteport
widthscanbesetindependentlyofoneanother.Becauseaportsarecommon
toallqueuesthewidthofthequeuesisnotindividuallyset.Theinputwidthof
allqueues are the same andthe outputwidthofallqueues are the same.
WRITING TO AND READING FROM THE MULTI-QUEUE
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
queueviathewritequeueaddressinput.Conversely,databeingreadfromthe
devicereadportisreadfromaqueueselectedviathereadqueueaddressinput.
Data can be simultaneously written into and read from the same queue or
differentqueues.Onceaqueueisselectedfordatawritesorreads,thewriting
andreadingoperationisperformedinthesamemannerasaconventionalIDT
synchronous FIFO, utilizing clocks and enables, there is a single clock and
enable per port. When a specific queue is addressed on the write port, data
placedonthedatainputsiswrittentothatqueuesequentiallybasedontherising
edgeofawriteclockprovidedsetupandholdtimesaremet.Conversely,data
isreadontotheoutputportafteranaccesstimefromarisingedgeonareadclock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
Whenaqueueis selectedontheoutputport,thenextwordinthatqueuewill
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueis empty,thereadportprovides anEmptyflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromthepreviousqueuewillremainontheoutputbus.Inadditionto
FirstWordFallThrough(FWFT)thedevicecanoperateinIDTStandardmode
or packet mode. In IDT Standard mode the read port provides a word to the
outputbus(Qout)foreachclockcyclethatRENisasserted.RefertoFigure48,
ReadQueueSelect,ReadOperation(IDTMode).Inpacketmodethedevice
assertsapacketreadystatusflagtoindicateoneormorepacketsareavailable
forreading.
PACKETREADY
Themulti-queueflow-controldevicealsooffersa“PacketMode”operation.
PacketModeisuserselectable.Inpacketmodewithax36bitwordlength,users
candefinethelengthofpacketsorframebyusingthetwomostsignificantbits
ofthe word.Ina36-bitword,bit34is usedtomarktheStartofPacket(SOP)
andbit35isusedtomarktheEndofPacket(EOP)asshowninTable10.When
writingdataintoagivenqueue,thefirstwordbeingwrittenis marked,bythe
user setting bit 34 as the “Start of Packet” (SOP) and the last word written is
markedasthe“EndofPacket”(EOP)withallwordswrittenbetweentheStart
ofPacket(SOP)marker(bit34)andtheEndofpacket(EOP)packetmarker
AUGUST4,2005
8
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
(bit35)constitutingtheentirepacket.Apacketcanbeanylengththeuserdesires, individual queues. Queue expansion means increasing the total number of
uptothetotalavailablememoryinthemulti-queuedevice.Thedevicemonitors queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore
theSOP(bit34)andlooksforthewordthatcontainstheEOP(bit35).Theread memoryblockswithinamulti-queuedevicecanbeallocatedtoafewernumber
portissuppliedwithanadditionalstatusflag,“PacketReady”.ThePacketReady ofqueuesto increasethedepthofeachqueue.Forexample,depthexpansion
(PR) flag in conjunction with Empty Flag or Output Ready flag (EF/OR) of8devicesprovidesthepossibilityof8queuesof4096Kbits,eachqueuebeing
indicateswhenatleastonepacketisavailabletoread.Wheninpacketmode setupwithinasingledeviceutilizingallmemoryblocksavailabletoproducea
thealmostemptyflagstatus,providespacketreadyflagstatusforindividual singlequeue.This is thedeepestqueuethatcansetupwithinadevice.
queues.
Forqueue expansiona maximumnumberof256queues (32x8queues)
maybe setup, witha average ofeachqueue being16,384Kx36deepusing
8devices,eachwith8queues.Iffewerqueuesaredesired,thenmorememory
EXPANSION (IDT STANDARD MODE)
Expansionofmulti-queuedevicesisalsopossible.Upto8devicescanbe blockswillbeavailabletoincreasequeuedepthsifdesired.Whenconnecting
connectedinaparallelbusconfigurationasindicatedinFigure67, Expansion multi-queuedevicesinexpansionconfigurationallrespectiveinputpins(data
using ID codes, and Figure 68, Expansion using WCS/RCS providing both & control) and output pins (data & flags), should be “connected” together
depthexpansionand/orqueueexpansion.Expansionofdevicesissupported betweenindividualdevices.RefertoFigure67,ExpansionusingIDcodes,and
onlyinIDTStandardmode.DepthExpansionmeansexpandingthedepthsof Figure68,ExpansionusingWCS/RCSfordeviceconnectiondetails.
AUGUST4,2005
9
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
Symbol &
(Pin No.)
Name
I/OTYPE
Description
BM [3:0]
BusMatching HSTL-LVTTL These pins define the bus widthofthe inputwrite portandthe outputreadportofthe device. The bus
(J1, L14,15,16)
INPUT
widthsaresetduringaMasterRestcycle.TheBM[3:0]signalsmustmeetthesetupandholdtime
requirementsofMasterResetandmustnottoggle/changestateafteraMasterReset cycle.
D[35:0]
DataInputBus HSTL-LVTTL These are the 36data inputpins. Data is writtenintothe device via these inputpins onthe risingedge
Din
INPUT
ofWCLKprovidedthatWEN is LOW.Note,thatinPacketmodeD32-D35maybeusedas packet
markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs
maybe used, anyunusedinputs shouldbe tiedLOW.
D[35]TransmitEndofPacket(TEOP)
(See Pin No.
tablefordetails)
D[34]TransmitStartofPacket(TSOP)
D[33:32]Userdefinablebits
D[31:0]Datainputbits
DF(1)
(L3)
DefaultFlag
DefaultMode
HSTL-LVTTL Iftheuserrequiresdefaultprogrammingofthemulti-queuedevice,thispinmustbesetupbeforeMaster
INPUT
Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
HSTL-LVTTL The multi-queue device requires programmingaftermasterreset. The usercandothis seriallyvia the
(L2)
INPUT
serialport,orviaparallelprogrammingorbythedefaultprogrammingoptionThedefaultprogramming
optionprovidesapre-definedconfiguration.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
EF/OR
(P9)
EmptyFlag/
OutputReady
HSTL-LVTTL This signalisbi-modal.WhenIDTStandardmodeisselectedthepinprovidesEmptyFlag(EF)status.
OUTPUT
WhenFWFTmodeisselectedthepinprovidesoutputready(OR)status.ThisoutputflagprovidesOutput
Readystatusforthedatawordpresentonthemulti-queueflow-controldevice dataoutputbus,Qoutin
FWFTmode.Thisflagisa2-stagedelayedtomatchthedataoutputpathdelay.Thereisa3RCLKcycle
delayinIDTStandardmodeanda4cycledelayforFWFTmode fromthetimeagivenqueueisselected
forreads,tothetimetheORflagrepresentsthedatainthatqueue.Whenaselectedqueueonthereadport
isreadtoempty,theORflagwillgoHIGH,indicatingthatdataontheoutputbusisnotvalid.TheORflagalso
hasHigh-Impedancecapability,requiredwhenmultipledevicesareusedandtheORflagsaretiedtogether.
ESTR
(R15)
PAEn Flag Bus HSTL-LVTTL IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
Strobe
INPUT
andtheRDADDbustoselectastatuswordofqueuestobeplacedontothePAEnbusoutputs.Astatus
wordaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovidedthatESTRisHIGH.
IfPolledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.Note,thataPAEnflagbus
selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
ESYNC
(R16)
PAEn Bus Sync HSTL-LVTTL ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT
duringPolledoperationofthePAEnbus.DuringPolledoperationeachstatuswordofqueuestatusflags
is loadedontothePAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads
status word1ontoPAEn,thesecondRCLKrisingedgeloads status word2andsoon.ThefifthRCLK
risingedgewillagainloadstatusword1.DuringtheRCLKcyclethatstatusword1ofaselecteddevice
isplacedontothePAEnbus,theESYNCoutputwillbeHIGH.Forallotherstatuswordsofthatdevice,
theESYNCoutputwillbeLOW.
EXI
(T16)
PAEnBus
ExpansionIn
HSTL-LVTTL TheEXIinputis usedwhenmulti-queuedevices areconnectedinexpansionconfigurationandPolled
INPUT
PAEnbusoperationhasbeenselected.EXIofdevice‘N’connectsdirectlytoEXOofdevice‘N-1’.The
EXIreceivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheEXIinputmustbetied
LOWifthe PAEnbus is operatedindirectmode. Ifthe PAEnbus is operatedinpolledmode the EXI
inputmustbeconnectedtotheEXOoutputofthesamedevice.InexpansionconfigurationtheEXIof
thefirstdeviceshouldbetiedLOW,whendirectmodeisselected.
EXO
(T15)
PAEnBus
ExpansionOut
HSTL-LVTTL EXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionconfigurationand
OUTPUT
PolledPAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.
This pinpulses whendevice Nhas placedits final(4th)status wordontothe PAEnbus withrespectto
RCLK.This pulse(token)is thenpassedontothenextdeviceinthechain‘N+1’andonthenextRCLK
risingedgethefirststatuswordofdeviceN+1willbeloadedontothePAEnbus.Thiscontinuesthrough
thechainandEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputof
eachdeviceinthechainprovides synchronizationtotheuserofthis loopingevent.
AUGUST4,2005
10
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
FF/IR
(P8)
Full Flag/
Input Ready
HSTL-LVTTL This pinprovidesthefullflagoutputfortheactiveQueue,thatis,thequeueselectedontheinputport
OUTPUT
forwriteoperations,(selectedviaWCLK,WRADDbusandWADEN).Onthe3rdWCLKcycleafteraqueue
selection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueueon
thenextcycleprovidedFF is HIGH.This flaghas High-Impedancecapability,this is importantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
(1)
FM
Flag Mode
HSTL-LVTTL Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
(K16)
INPUT
FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
FSTR
(R4)
PAFn Flag Bus HSTL-LVTTL IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
Strobe
INPUT
andtheWRADDbustoselectastatuswordofqueuestobeplacedontothePAFnbusoutputs.Astatus
wordaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovidedthatFSTRisHIGH.
If Polledoperationshasbeenselected,FSTRshouldbetiedinactive,LOW.Note,thataPAFnflagbus
selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
FSYNC
(R3)
PAFn Bus Sync HSTL-LVTTL FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus
OUTPUT
duringPolledoperationofthePAFnbus.DuringPolledoperationeachstatuswordofqueuestatusflags
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
statusword1ontoPAFn,thesecondWCLKrisingedgeloadsstatusword2andsoon.ThefifthWCLK
risingedgewillagainloadstatusword1.DuringtheWCLKcyclethatstatusword1ofaselecteddevice
isplacedontothePAFnbus,theFSYNCoutputwillbeHIGH.Forallotherstatuswordsofthatdevice,
theFSYNCoutputwillbeLOW.
FWFT
(R11)
FirstWordFall HSTL-LVTTL Firstwordfallthrough(FWFT)orIDTStandardmodeisselectedduringaMasterResetcycle.Toselect
Through
INPUT
FWFTmodeasserttheFWFTsignal=HIGH,ifFWFT=LOWduringthemasterresetthenIDTStandard
modeisselected.
FXI
(T2)
PAFnBus
ExpansionIn
HSTL-LVTTL TheFXIinputisusedwhenmulti-queuedevicesareconnectedinexpansionconfigurationandPolled
INPUT
PAFnbusoperationhasbeenselected.FXIofdevice‘N’connectsdirectlytoFXOofdevice‘N-1’.The
FXIreceives a tokenfromthe previous device ina chain. Insingle device mode the FXIinputmustbe
tiedLOWifthePAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXI
inputmustbeconnectedtotheFXOoutputofthesamedevice.InexpansionconfigurationtheFXIofthe
firstdeviceshouldbetiedLOW,whendirectmodeisselected.
FXO
(T3)
PAFnBus
ExpansionOut
HSTL-LVTTL FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionconfigurationand
OUTPUT
PolledPAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.
This pinpulses whendeviceNhas placedits final(4th)status wordontothe PAFnbus withrespectto
WCLK.Thispulse(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextWCLK
risingedgethefirststatuswordofdeviceN+1willbeloadedontothePAFnbus.Thiscontinuesthrough
thechainandFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputof
eachdeviceinthechainprovides synchronizationtotheuserofthis loopingevent.
(1)
ID[2:0]
Device ID Pins HSTL-LVTTL Forthe8Qmulti-queuedevicetheWRADDandRDADDaddressbussesare8bitswide.Whenaqueue
(ID2-C9
ID1-A10
ID0-B10)
INPUT
selectiontakesplacethe3MSb’s(bits7,6,5)ofthis8bitaddressbusareusedtoaddressthespecific
device (the 5-7LSb’s are usedtoaddress the queue withinthatdevice). Duringwrite/readoperations
the3MSb’softheaddressarecomparedtothedeviceIDpins.Inaneightdeviceexpansionconfiguration,
thefirstdeviceinachainofmulti-queue’s(connectedinexpansionconfiguration),maybesetupas‘000'
(thisisreferredtoastheMasterDevice),thesecondas‘001’andsoonthroughtodevice8whichis‘111’,
however the ID does not have to match the device order. In single device mode these pins should be
setupas ‘000’andthe 3MSb’s ofthe WRADDandRDADDaddress busses shouldbe tiedLOW. The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
anydeviceoperation.Note,thedeviceselectedasthe‘Master’mustbeID‘000’.Inserialprogramming,
themasterdevice(ID000)mustbeprogrammedlast.
AUGUST4,2005
11
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
IOSEL
(C8)
IOSelect
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
requiredthenIOSELshouldbetiedHIGH(VDDQ).IfLVTTLI/OarerequiredthenitshouldbetiedLOW.
(1)
MAST
(K15)
MasterDevice HSTL-LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
INPUT
Masterdevice ora Slave. Ifthis pinis HIGH, the device is the masterifitis LOWthenitis a Slave. The
masterdeviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-
Impedance,preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,this
pinmustbesetHIGH.
MRS
MasterReset
HSTL-LVTTL AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
INPUT aftermasterreset.
OutputEnable HSTL-LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
(T9)
OE
(M14)
INPUT
dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill
beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe
inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
PAE
(P10)
Programmable HSTL-LVTTL ThispinprovidestheAlmost-EmptyflagstatusfortheQueuethathasbeenselectedontheoutputport
Almost-Empty
Flag
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Queueisalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagis
synchronizedtoRCLK.
PAEn/PRn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
Programmable HSTL-LVTTL Onthe 32Qdevice the PAEn/PRnbus is 8bits wide. Duringa MasterResetthis bus is setupforeither
Almost-Empty
OUTPUT
AlmostEmptymodeorPacketmode.ThisoutputbusprovidesPAE/PRnstatusof8queues(1statusword),
withinaselecteddevice,havingamaximumof16status words.DuringQueueread/writeoperations
theseoutputsprovideprogrammableemptyflagstatusorpacketreadystatus,ineitherdirect orpolled
mode.ThemodeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.
ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.
DuringdirectoperationthePAEn/PRnbusisupdatedtoshowthePAE/PRstatusofastatuswordofqueues
withinaselecteddevice. Selectionis madeusingRCLK, ESTRandRDADD. DuringPolledoperation
thePAEn/PRnbusisloadedwiththePAE/PRnstatusofmulti-queueflow-controlstatuswordssequentially
basedonthe rising edgeofRCLK.PAEorPRoperationisdeterminedbythestateofPKTduringmaster
reset.
FlagBus/Packet
Ready Flag Bus
PAF
(R8)
Programmable HSTL-LVTTL ThispinprovidestheAlmost-FullflagstatusfortheQueuethathasbeenselectedontheinputportfor
Almost-FullFlag OUTPUT
writeoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselected
Queueisalmost-full.ThisflagoutputmaybeduplicatedononeofthePAFnbuslines.Thisflagis
synchronizedtoWCLK.
PAFn
Programmable HSTL-LVTTL Onthe 32Qdevice the PAFnbus is 8bits wide. Atanyone time this outputbus provides PAF status
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
Almost-FullFlag OUTPUT
Bus
of8queues(1statusword),withinaselecteddevice,havingamaximumof16statuswords.DuringQueue
read/writeoperationstheseoutputsprovideprogrammablefullflagstatus,ineitherdirectorpolledmode.
ThemodeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbus
iscapableofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirect
operationthePAFnbusisupdatedtoshowthePAFstatusofastatuswordofqueueswithinaselected
device.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthePAFn
busisloadedwiththePAFstatusofmulti-queueflow-controlstatuswordssequentiallybasedontherising
edgeofWCLK.
(1)
PKT
PacketMode
HSTL-LVTTL ThestateofthispinduringaMasterResetwilldeterminewhetherthepartisoperatinginPacketmode
(J14)
INPUT
providingbothaPacketReady(PR)outputandaProgrammableAlmostEmpty(PAE)discreteoutput,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operateinpacketmode,ifitisLOWthenalmostemptymode.Ifpacketmodehasbeenselectedtheread
portflagbusbecomespacketreadyflagbus,PRnandthediscretepacketreadyflag,PRisfunctional.
Ifalmostemptyoperationhasbeenselectedthentheflagbusprovidesalmostemptystatus,PAEnand
thediscretealmostemptyflag,PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.
PacketReadyutilizesusermarkedlocationstoidentifystartandendofpacketsbeingwrittenintothedevice.
AUGUST4,2005
12
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
PR
(R9)
PacketReady HSTL-LVTTL IfpacketmodehasbeenselectedthisflagoutputprovidesPacketReadystatusoftheQueueselected
Flag
OUTPUT
forreadoperations.DuringamasterresetthestateofthePKTinputdetermineswhetherPacketmode
ofoperationwillbeused.IfPacketmodeisselected,thentheconditionofthePRflagandEF/ORsignal
areassertedindicatesapacketisreadyforreading.Theusermustmarkthestartofapacketandtheend
ofapacketwhenwritingdataintoaqueue.UsingtheStartOfPacket(SOP)andEndOfPacket(EOP)
markers,themulti-queuedevicesetsPRLOWifoneormore“complete”packetsareavailableinthequeue.
Acompletepacket(s)mustbewrittenbeforetheuserisallowedtoswitchqueues.
Q[35:0]
DataOutputBus HSTL-LVTTL Thesearethe36dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
Qout
(See Pin No.
tablefordetails)
OUTPUT
ofRCLKprovidedthatRENisLOW,OEisLOWandtheQueueisselected.Note,thatinPacketReady
modeQ32-Q35maybeusedaspacketmarkers,pleaseseepacketreadyfunctionaldiscussionformore
detail.Duetobusmatchingnotalloutputsmaybeused,anyunusedoutputsshouldnotbeconnected.
QSEL[1:0]
(QSEL1-K1
QSEL0-J2
QueueSelect HSTL-LVTTL The QSEL pins provides various queue programming options. Refer to Table 2, for details.
INPUT
1.AQSELvalueof00,enablestheusertoprogramthenumberofqueuesusingtheWriteAddressbus.
2.AQSELvalueof01,enablestheusertoprogramthenumberofqueuesusingtheReadAddressbus.
3. AQSELvalue of10, Selects a configurationof4queues.
4. AQSELvalue of11, selects a configurationof8queues
RADEN
(R14)
ReadAddress HSTL-LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
Enable
INPUT
bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthe
parthas beencompletedandSENO has goneLOW.
RCLK
(T10)
ReadClock
HSTL-LVTTL When enabledbyREN, the risingedge ofRCLKreads data fromthe selectedqueue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
PAEn/PRnflagstatuswordtobeplacedonthePAEn/PRnbusduringdirectflagoperation.Duringpolled
flagoperationthePAEn/PRnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronized
toRCLK.ThePAE,PRandORoutputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXO
and EXI signals are based on RCLK. RCLK must be continuous and free-running.
RCS
(R10)
Read Chip
Select
HSTL-LVTTL TheRCSsignalinconcertwithRENsignalprovidescontroltoenabledataontotheoutputreaddatabus.
INPUT Duringa MasterResetcycle theRCS itis don’tcare signal.
RDADD
ReadAddress HSTL-LVTTL For the 8Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first
[7:0]
Bus
INPUT
functionofRDADDistoselectaQueuetobereadfrom.Theleastsignificant5bitsofthebus,RDADD[4:0]
areusedtoaddress 1of32possiblequeueswithinamulti-queuedevice.Themostsignificant3bits,
RDADD[7:5]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode.Aninexpansionconfigurationthe3MSb’swilladdressadevicewiththematchingIDcode.The
addresspresentontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENis
HIGH,(note,thatdatacanbeplacedontotheQoutbus,readfromthepreviouslyselectedqueueonthis
RCLKedge). TwoRCLKrisingedgesafterreadqueueselect,datawillbeplacedontotheQoutoutputs
fromthenewlyselectedqueue,regardlessofRENduetothefirstwordfallthrougheffect.
The secondfunctionofthe RDADDbus is toselectthe status wordofqueues tobe loadedontothe
PAEn/PRnbusduringstrobedflagmode.Theleastsignificant4bits,RDADD[3:0]areusedtoselectthe
statuswordofadevicetobeplacedonthePAEnbus.Themostsignificant3bits,RDADD[7:5]areagain
usedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionconfiguration.
Address bits RDADD[4]is don’tcareduringstatus wordselection.Thestatus wordaddress present
ontheRDADDbuswillbeselectedontherisingedgeofRCLKprovidedthatESTRisHIGH,(note,that
data canbe placedontothe Qoutbus, readfromthe previouslyselectedQueue onthis RCLKedge).
Please refer to Table 5 for details on RDADD bus.
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
REN
(T11)
ReadEnable
HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK.
INPUT
IntheFWFTmode,aqueuetobereadfromcanbeselectedviaRCLK,RADENandtheRDADDaddress
bus regardless ofthestateofREN.Areadenableis notrequiredtocyclethe PAEn/PRnbus (inpolled
mode)ortoselectthePAEnstatus word,(indirectmode).
AUGUST4,2005
13
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
(Pin No.)
Name
I/OTYPE
Description
SCLK
SerialClock
HSTL-LVTTL Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput
(N3)
INPUT
clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
(M2)
SerialInput
Enable
HSTL-LVTTL Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT
part(via a risingedge ofSCLK), providedthe SENI inputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
(M1)
SerialOutput
Enable
HSTL-LVTTL Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queuedevice
OUTPUT
hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutput
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENO willgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedtheSENO output
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
(L1)
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregistersareshiftregisters.
SO
SerialOut
HSTL-LVTTL Thisoutputisusedinexpansionconfigurationandallowsserialdatatobepassedthroughdevicesinthe
(M3)
OUTPUT
chaintocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdevice
inthe chain. The SOofthe finaldevice ina chainshouldnotbe connected.
(2)
TCK
JTAGClock
HSTL-LVTTL ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
(A8)
INPUT
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds
tobe tiedtoGND.
(2)
TDI
JTAGTestData HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
(B9)
Input
INPUT
testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister
andBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(A9)
Output
OUTPUT
operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whilein
SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(B8)
JTAGMode
Select
HSTL-LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
INPUT devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
HSTL-LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
(2)
TRST
JTAGReset
(C7)
INPUT
resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.IftheJTAG
function is used but the user does not want to use TRST, thenTRST can be tied withMRS to ensure
properqueue operation. Ifthe JTAGfunctionis notusedthenthis signalneeds tobe tiedtoGND. An
internalpull-upresistorforcesTRSTHIGHifleftunconnected.
WADEN
(P4)
WriteAddress HSTL-LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
Enable
INPUT
bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).WADEN
shouldnotbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,
AUGUST4,2005
14
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
WADEN
WriteAddress HSTL-LVTTL thatawritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingofthepart
(Continued)
Enable
INPUT
has beencompletedandSENO has goneLOW.
WCLK
(T7)
WriteClock
HSTL-LVTTL WhenenabledbyWEN,therisingedgeofWCLKwrites dataintotheselectedQueueviatheinput
INPUT
bus, Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of
WCLKwhile WADENis HIGH. Arisingedge ofWCLKinconjunctionwithFSTRandWRADDwillalso
selecttheflagstatuswordtobeplacedonthePAFnbusduringdirectflagoperation.Duringpolledflag
operationthePAFnbusiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.
The PAFn, PAF and FF outputs are allsynchronizedtoWCLK. Duringdevice expansionthe FXOand
FXIsignals are basedonWCLK. The WCLKmustbe continuous andfree-running.
WCS
(T8)
WriteChip
Select
HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WEN
(T6)
WriteEnable
HSTL-LVTTL The WEN input enables write operations to a selected Queue based on a rising edge of WCLK. A
INPUT
queue tobe writtentocanbe selectedvia WCLK, WADENandthe WRADDaddress bus regardless
ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK
cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn
bus (in polled mode) or to select the PAFn status word , (in direct mode).
WRADD
WriteAddress HSTL-LVTTL For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The
[7:0]
Bus
INPUT
firstfunctionofWRADDistoselectaQueuetobewrittento. The leastsignificant5bits ofthe bus,
WRADD[4:0] are usedtoaddress 1of32possible queues withina multi-queue device. Inexpansion
configurationthemostsignificant3bits,WRADD[7:5]areusedtoselect1of8possiblemulti-queuedevices
(dependantonthenumberofqueuesaddressed)thatmaybeconnectedinexpansionconfiguration.These
3MSb’s willaddress adevicewiththematchingIDcode.Theaddress presentontheWRADDbus will
beselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,thatdatapresentontheDin
buscanbewrittenintothepreviouslyselectedqueueonthisWCLKedgeandonthenextrisingWCLK
also,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeueselect,datacanbewritten
intothenewlyselectedqueue.
(WRADD7-T1
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
ThesecondfunctionoftheWRADDbusistoselectthestatuswordofqueuestobeloadedontothePAFn
busduringstrobedflagmode.Theleastsignificant4bits,WRADD[3:0]areusedtoselectthestatusword
ofa device tobe placedonthe PAFnbus. The mostsignificant3bits, WRADD[7:5]are againusedto
select1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionconfiguration.Addressbits
WRADD[4]isdon’tcareduringstatuswordselection.ThestatuswordaddresspresentontheWRADD
bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be
writtenintothepreviouslyselectedqueueonthisWCLKedge).PleaserefertoTable4fordetailsonthe
WRADDbus.
VDD
(See pg. 16)
+1.8VSupply
Power
Power
These are VDD power supply pins and must all be connected to a +1.8V supply rail.
VDDQ
(See pg. 16)
O/PRailVoltage
Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected
to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected
to+1.8V.
GND
GroundPin
Ground
These are Ground pins and must all be connected to the GND supply rail.
(See pg. 16)
Vref
(K3)
Reference
Voltage
HSTL
INPUT
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable
"RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL
inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 82-86 and Figures 71-73.
AUGUST4,2005
15
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN NUMBER TABLE
Symbol
Name
I/OTYPE
Pin Number
D[35:0]
Din
DataInputBus HSTL-LVTTL D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1),
INPUT
D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5,
D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
Q[35:0]
Qout
DataOutputBus HSTL-LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16),
OUTPUT Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14,
Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11,
Q(1,0)-C(11,10)
VDD
+1.8VSupply
O/PRailVoltage
GroundPin
Power
Power
Ground
D(7-10),E(6,7,10,11),F(5,12),G(4,5,12,13),H(4,13),J(4,13),K(4,5,12,13),L(5,12),M(6,7,10,11),N(7-10)
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
VDDQ
GND
E(8-9), F(6-11), G(6-11), H(5-12), J(1,5-12), K(2,6-11,14), L(6-11), M(8-9)
AUGUST4,2005
16
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Unit
Symbol
Parameter(1)
Conditions
Max.
Unit
VTERM
TerminalVoltage
–0.5to+2.9(2)
V
(2,3)
CIN
Input
VIN = 0V
10(3)
pF
with respect to GND
Capacitance
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
(1,2)
COUT
Output
VOUT = 0V
15
pF
Capacitance
NOTES:
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
2. Compliant with JEDEC JESD8-5. VDD terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VDD
Parameter
Min.
Typ.
Max.
Unit
SupplyVoltage
1.7
1.8
1.9
V
VDDQ
OutputRailVoltageforI/Os LVTTL
2.375
1.7
1.4
2.5
1.8
1.5
2.625
1.9
1.6
V
V
V
eHSTL
HSTL
GND
SupplyVoltage
0
0
0
V
(2)
VIH
InputHighVoltage
LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
2.625
—
—
V
V
V
VIL
InputLowVoltage
LVTTL
eHSTL
HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF(1)
(HSTL only)
VoltageReferenceInput
eHSTL
HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. VIH AC Component = VREF + 0.4V
AUGUST4,2005
17
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DCELECTRICALCHARACTERISTICS
(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C)
Symbol
Parameter
Min.
–10
–10
Max.
10
Unit
µA
µA
V
V
V
ILI
InputLeakageCurrent
OutputLeakageCurrent
ILO
10
(3)
VOH
OutputLogic“1”Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
OutputLogic“0”Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
IDD1(1,2)
IDD2(1, 5)
Active VDD Current (VDD = 1.8V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
80
150
150
mA
mA
mA
Standby VDD Current (VDD = 1.8V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
25
100
100
mA
mA
mA
(1,2)
IDDQ
ActiveVDDQ Current (VDDQ =2.5VLVTTL)
(VDDQ = 1.5V HSTL)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
10
10
10
mA
mA
mA
(VDDQ = 1.8V eHSTL)
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Total Power consumed: PT = [(VDD x IDD) + (VDDQ x IDDQ)].
4. Outputs are not 3.3V tolerant.
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VDD: WEN, REN, SENI, MRS, TDI, TMS and TRST.
All other inputs are don't care and should be at a known state.
AUGUST4,2005
18
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
VDDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
InputRise/FallTimes
50Ω
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
VDDQ/2
I/O
6716 drw04
NOTE:
1. VDDQ = 1.5V ± 0.1V.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V ± 0.1V.
20 30 50 80 100
200
Capacitance (pF)
6716 drw04a
2.5VLVTTL
2.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VDD/2
VDDQ/2
NOTE:
1. VDDQ = 2.5V ± 0.125V.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
CC/2
OL
V
CC/2
100mV
100mV
100mV
V
V
OH
Output
Normally
HIGH
100mV
VCC/2
VCC/2
6716 drw05
NOTE:
1. REN is HIGH.
AUGUST4,2005
19
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72P51339L5
IDT72P51349L5
IDT72P51359L5
IDT72P51369L5
IDT72P51339L6
IDT72P51349L6
IDT72P51359L6
IDT72P51369L6
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency (WCLK & RCLK)
DataAccessTime
—
0.6
5
200
3.6
—
—
0.6
6
166
3.7
—
—
—
—
—
—
—
—
—
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock High Time
2.25
2.25
1.5
0.5
1.5
0.5
30
—
2.7
2.7
2.0
0.5
2.0
0.5
30
Clock Low Time
—
DataSetupTime
—
tDH
DataHoldTime
—
tENS
tENH
tRS
EnableSetupTime
—
EnableHoldTime
—
ResetPulseWidth
—
tRSS
tRSF
tRSR
ResetSetupTime
15
—
15
ResetOutputStatus
—
10
10
—
10
ResetRecoveryTime
—
—
3.7
3.7
3.7
10
(2)
tOLZ(OE-Qn)
OutputEnabletoOutputinLow-Impedance
OutputEnabletoOutputinHigh-Impedance
OutputEnabletoDataOutputReady
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
0.6
0.6
0.6
—
100
45
3.6
3.6
3.6
10
0.6
0.6
0.6
—
100
45
(2)
tOHZ
tOE
fC
tSCLK
tSCKH
tSCKL
tSDS
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCSF
tAS
—
—
—
—
—
—
—
—
20
Serial Clock High
—
Serial Clock Low
45
—
45
SerialDataInSetup
20
—
20
Serial Data In Hold
1.2
20
—
1.2
20
SerialEnableSetup
—
SerialEnableHold
1.2
—
—
0.6
0.6
—
1.5
0.5
—
—
1.5
0.5
1.5
0.5
0.6
0.6
0.6
0.6
0.6
—
1.2
—
—
0.6
0.6
—
2.0
0.5
—
—
1.5
0.5
2.0
0.5
0.6
0.6
0.6
0.6
0.6
SCLK to Serial Data Out
SCLK to Serial Enable Out
SerialDataOutPropagationDelay
SerialEnablePropagationDelay
ProgrammingCompletetoStatusFlag
AddressSetup
20
20
20
3.7
3.7
7+1 SCLK
—
3.7
3.7
7+1 SCLK clock cycles
—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
3.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address Hold
—
tWFF
tREF
tSTS
tSTH
tQS
Write Clock to Full Flag
Read Clock to Empty Flag
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
QueueSetup
3.6
3.6
—
—
—
tQH
QueueHold
—
tWAF
tRAE
tPAF
tPAE
WCLK to PAF flag
RCLK to PAE flag
Write ClocktoSynchronous Almost-FullFlagBus
Read Clock to Synchronous Almost-Empty Flag Bus
RCLK to PAE Flag Bus to Low-Impedance
3.6
3.6
3.6
3.6
3.6
(2)
tPAELZ
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
AUGUST4,2005
20
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(CONTINUED)
(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72P51339L5
IDT72P51349L5
IDT72P51359L5
IDT72P51369L5
IDT72P51339L6
IDT72P51349L6
IDT72P51359L6
IDT72P51369L6
Symbol
Parameter
Min.
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
5
Max.
Min.
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
6
Max.
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
Unit
ns
(2)
tPAEHZ
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLKtoFullFlag/InputReadytoHigh-Impedance
WCLKtoFullFlag/InputReadytoLow-Impedance
RCLKtoEmptyFlag/OutputReadyFlagtoLow-Impedance
RCLKtoEmptyFlag/OutputReadyFlagtoHigh-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
RCLK to Packet Ready Flag
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
(2)
tPAFLZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tPAFHZ
(2)
tFFHZ
(2)
tFFLZ
(2)
tEFLZ
(2)
tEFHZ
tFSYNC
tFXO
tESYNC
tEXO
tPR
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tXIS
SKEW time between RCLK and WCLK for FF/IR and EF/OR
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for PR and EF/OR
ExpansionInputSetup
5
6
—
5
6
—
5
6
—
1.5
0.5
15
2.0
0.5
15
—
tXIH
ExpansionInputHold
—
tPPMS
tPPMH
NOTES:
ParallelProgrammingSetup
—
ParallelProgrammingHold
5
5
—
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
AUGUST4,2005
21
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DFM–Programmingmode,serialordefault
DF – Offset value for PAE and PAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.
See Figure 37, Master Reset for relevant timing.
FUNCTIONALDESCRIPTION
MASTERRESET
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registersareinitializedandrequireprogrammingeitherseriallybytheuservia
theserialport,orviaparallelprogrammingorbyusingthedefaultsettings.Refer
to Figure 4, Device Programming Hierarchy for the programming hierarchy
structure.Duringamasterresetthestateofthefollowinginputsdeterminethe
functionalityofthepart,thesepinsshouldbeheldHIGHorLOW.
PKT–PacketMode
PROGRAMMINGMODECAPTURED
On the rising of /MRS the programming mode signals (QSEL 0 &1,
DEFAULT)arecaptured.Oncetheprogrammingmodesignalsarecaptured
(latched),refertoTable1fordetails.Itwillthenrequireanumberofclockcycles
forthedevicetocompletetheconfiguration.Configurationcompletionisindicated
whentheSENOsignaltransitionsfromhightolow.Theconfigurationcompletion
indicationisconsistentwiththepreviousMQdevice.
FM – Flag bus Mode
BM[3:0]–Bus Matchingoptions
MAST – Master Device
ID0, 1, 2 – Device ID
MRS
QSEL0
QSEL1
See Table 2 for definition of value
See Table 2 for definition of value
Default mode
(DFM)
DFM = LOW for Serial Programming mode
6716 drw06
Figure 3. Reference Signals
TABLE 1 — DEVICE PROGRAMMING MODE COMPARISON
ProgrammableParameter Serial Programming
ParallelProgramming
Default Programming
Number of Queues
Queue Depth
Any number from 1 to 8
Any number from 1 to 8
4 or 8
Each queue depth can be
individualized
The total memory is evenly divided
acrossthequeues
The total memory is evenly divided
acrossthequeues
PAE/PAF Offset Value
Programmable to any value
Fixed value
Fixed value
Bus Matching
Any combination of x9 or x18 or x36 can Any combination of x9 or x18 or x36 Any combination of x9, x18, or x36 can
beselectedusingtheBM[3:0]bits.
canbeselectedusingtheBM[3:0]bits. beselectedusingtheBM[3:0]bits
I/O voltage
LVTTL, eHSTL, HSTL
LVTTL, eHSTL, HSTL LVTTL, eHSTL, HSTL
TABLE2—SETTINGTHEQUEUEPROGRAMMINGMODEDURINGMASTERRESET
Default
Queue Programming Method
Mode
MRS (DFM) QSEL 1 QSEL 0
0
0
0
0
0
1
RESERVED
RESERVED
0
1
0
RESERVED
0
1
1
0
1
0
Serial programming mode
Enables the user to program the number
of Queues using the Write Address bus
1
1
1
0
1
1
1
0
1
Enables the user to program the number
of Queues using the Read Address bus
Selects 4 Queue
Selects 8 Queue
6716 drw07
AUGUST4,2005
22
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SERIAL PROGRAMMING
SeeFigure42,SerialPortConnectionandFigure43,SerialProgramming
Themulti-queueflow-controldeviceisafullyprogrammabledevice,provid- forconnectionandtiminginformation.
ingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthenumber
of queues, depth of each queue and position of the PAF/PAE flags within DEFAULTPROGRAMMING
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe multi-
resethas takenplace. Internallythe multi-queue device has setupregisters queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming
whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue is not permitted). Default programming provides the user with a simpler,
within the device, such as the depth and PAE/PAF offset values. The howeverlimitedmeanstosetupthemulti-queueflow-controldevice,ratherthan
IDT72P51339/72P51349/72P51359/72P51369devicesarecapableofupto usingtheserialprogrammingmethod.Thedefaultmodewillconfigureamulti-
8queuesandthereforecontain128setsofregistersforthesetupofeachqueue. queuedevicewiththemaximumnumberofqueues setup,andtheavailable
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice memoryallocatedequallybetweenthequeues.Thevalues ofthePAE/PAF
willrequire serialprogrammingbythe user. Itis recommendedthatthe user offsetsisdeterminedbythestateoftheDF(default)pinduringamasterreset.
utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall
FortheIDT72P51339/72P51349/72P51359/72P51369devicesthedefault
informationregardingthemulti-queuesetup.Theprogramwillthengenerate mode willsetup8queues, eachqueue being512x36, 1024x36, 2048x36,
aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial and4096x36deeprespectively.Foreachdevice,thevalueofthePAE/PAF
port. For the IDT72P51339/72P51349/72P51359/72P51369 devices the offsetsisdeterminedatmasterresetbythestateoftheDFinput.IfDFisLOW
serialprogrammingrequiresatotalnumberofseriallyloadedbitsperdevice, then both the PAE & PAF offsetwillbe 8, ifHIGHthenthe value is 128.
(SCLKcycles withSENI enabled), calculatedby:19+(Qx72)where Qis the
numberofqueues theuserwishes tosetupwithinthedevice.
WhenconfiguringtheIDT72P51339/72P51349/72P51359/72P51369de-
vicesindefaultmodetheusersimplyhastoapplyWCLKcyclesafteramaster
Once the master reset is complete and MRS is HIGH, the device can be reset,untilSENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial Theseclockcyclesarerequiredforthedevicetoloaditsinternalsetupregisters.
port on a rising edge of SCLK (serial clock), provided that SENI (serial in Whenasinglemulti-queuedeviceisused,thecompletionofdeviceprogram-
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully mingissignaledbytheSENOoutputofadevicegoingfromHIGHtoLOW.Note,
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going thatSENImustbeheldLOWwhenadeviceissetupfordefaultprogramming
active,LOW.Upondetectionofcompletionofprogramming,theusershould mode.
ceaseallprogrammingandtakeSENIinactive,HIGH.Note,SENOfollowsSENI
Whenmulti-queuedevicesareconnectedinexpansionconfiguration,the
onceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOWafter SENIofthefirstdeviceinachaincanbeheldLOW.TheSENOofadeviceshould
programmingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO connecttotheSENIofthenextdeviceinthechain.TheSENOofthefinaldevice
willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming isusedtoindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthe
ofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.
master(ID='000')SENOgoesLOWnormaloperationsmaybegin.Again,all
Ifdevicesarebeingusedinexpansionconfigurationtheserialportsofdevices devices will be programmed with their maximum number of queues and the
shouldbecascaded.Theusercanloadalldevicesviatheserialinputportcontrol memory divided equally between them. Please refer to Figure 38, Default
pins,SI&SENI,ofthefirstdeviceinthechain.Again,theusermayutilizethe Programming.
‘C’programtogeneratetheserialbitstream,theprogrampromptingtheuser
forthenumberofdevicestobeprogrammed.TheSENOandSO(serialout) PARALLELPROGRAMMING
ofthefirstdeviceshouldbeconnectedtotheSENIandSIinputsofthesecond
DuringaMasterResetcycle(i.e.theMRSsignaltransitionsfromHIGHto
devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe LOWthenLOWtoHIGH)iftheDFM(DefaultMode)inputsignalisHIGHand
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould the QSEL 1 input signal is LOW the Multi-Queue Flow Control device is
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould configured for Parallel Programming. Parallel Programming enables the
be monitored by the user. When SENO of the final device goes LOW, this numberofqueueswithinthedevicetobesetthrougheithertheWriteAddress
indicates thatserialprogrammingofalldevices has beensuccessfullycom- (WRADD)busorReadAddress(RDADD)busaftertheMasterResetcycle.
pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall WithinParallelProgrammingmodetheMulti-Queue(MQ)deviceprogram-
programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.
mableparametersare;numberofqueues,queuedepth,PAE/PAFflagoffset
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled value, bus matching and the I/O voltage level. As previously indicated, the
bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded number of queues are configured using the write or read address bus,
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake howeverbusmatchingissetduringtheMasterResetcycle.Thevaluethatis
its SENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits setduringtheMasterResetcycleisdeterminedbytheBusMatching(BM)bits.
SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith FortheIDT72P51339/72P51349/72P51359/72P51369devices inParallel
thedatafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENI Programming Mode the value of the PAE/PAF offsets at master reset is
input LOW. This process continues through the chain until all devices are determinedbythestateoftheDFinput.IfDFisLOWthenboththePAE&PAF
programmedandthe SENO ofthe finaldevice (ormasterdevice, ID='000') offsetwillbe 8, ifHIGHthenthe value is 128.
goesLOW.
When configuring the IDT72P51339/72P51349/72P51359/72P51369
Once all serial programming has been successfully completed, normal devices inParallelProgrammingMode the usersimplyhas toapplyWCLK
operations,(queueselectionsonthereadandwriteports)maybegin.When cycles aftera masterreset, untilSENO goes LOW,this signals thatParallel
connectedinexpansionconfiguration,theIDT72P51339/72P51349/72P51359/ Programmingiscomplete.Theseclockcyclesarerequiredforthedeviceto
72P51369devicesrequireatotalnumberofseriallyloadedbitsperdeviceto loaditsinternalsetupregisters.Whenasinglemulti-queuedeviceisused,the
completeserialprogramming,(SCLKcycleswithSENIenabled),calculatedby: completionofdeviceprogrammingissignaledbytheSENOoutputofadevice
n[19+(Qx72)]whereQisthenumberofqueuestheuserwishestosetupwithin goingfromHIGHtoLOW.Note,thatSENImustbeheldLOWwhenadevice
the device, where n is the number of devices in the chain.
issetupforParallelProgrammingmode.
AUGUST4,2005
23
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WhenMulti-QueuedevicesareconnectedinanExpansionConfiguration, PROGRAMMINGHIERARCHY
theSENIsignalofthefirstdeviceinachainmustbeheldLOW.TheSENOsignal
Configuring the device is a 2 stage sequence. The first stage is to set the
ofadeviceshouldconnecttotheSENIofthenextdeviceinthechain.TheSENO expansion device type, the desired programming mode and the device
of the final device is used to indicate that the programming of all devices is operatingmodeduringthemasterresetcycle(i.e.ontherisingedgeofMaster
complete. When the master device (ID=’000') SENO signal goes LOW the Reset(MRS)).ThesecondstageistosetvaluessuchasPAE/PAF,number
internalprogrammingiscompleteandqueuewrite/readoperationmaybegin. of queues, queue depth, etc. using the programming mode (serial, parallel,
PleaserefertoFigure39,ParallelProgrammingforsignaltimingdetails.
default)selectedinstage1.RefertoFigure4,DeviceProgrammingHierarchy.
Master Reset Cycle
Device Operating Mode
Selected
Expansion
Device Type
Selected
Device
Programming
Mode Selected
(Packet Mode)
(FIFO Mode)
(IDT Mode)
(FWFT Mode)
(IDT Mode)
(FWFT Mode)
Master
Device
Slave
Device
Serial
Programming
Parallel Queue
Programming
Default
Programming
6716 drw08
Figure 4. Device Programming Hierarchy
AUGUST4,2005
24
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
mode,Standardmode,andFWFTmode.Toconfigurethedeviceoperational
mode setthe configurationpins (PKT, FWFT)as indicatedinTable 3, Mode
Configuration.
QUEUEDESCRIPTION
CONFIGURATIONOFTHEIDTMULTI-QUEUEFLOW-CONTROLDEVICE
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
troldevicescanbeconfiguredindistinctmodes,namelyPacketmode,FIFO
TABLE 3 — MODE CONFIGURATION
Configuration Signals
Modes
Operational Modes
PKT
FWFT
LOW
Packet Mode
FIFO Mode
LOW
LOW
HIGH
HIGH
FIFO mode - IDT Standard Mode
FIFO mode - FWFT
HIGH
LOW
Packet mode - IDT Standard Mode
Packetmode-FWFT
IDT Standard
Mode
FWFTMode
IDTStandard FWFTMode
Mode
HIGH
InIDTStandardmodethereadportsignalEF/OR is configuredforempty forfullflag(FF)signaling.FFisanactiveLOWsignal.WhenFFisLOWitsignifies
flag(EF)signaling.EFisanactiveLOWsignal.WhenEFisLOWitsignifiesthe the selected (present) queue is full. Refer to Figure 5, IDT Standard mode
selected(present)queueisempty.Onthewriteport,signalFF/IRisconfigured illustrated (Read Port).
RCLK
EF
Last Data Word
Qout
REN
6716 drw09
Figure 5. IDT Standard mode illustrated (Read Port)
InFWFTmodethereadportsignalEF/ORisconfiguredforoutputready(OR) ready(IR)signaling.IRisanactiveLOWsignal.WhenIRisLOWitsignifiesthe
signaling.ORisanactiveLOWsignal.WhenORisHIGH,itsignifiesthereisno writeportisreadyforwritingintotheselectedqueue.RefertoFigure6,FWFT
available wordtoread. Onthe write port, signalFF/IR is configuredforinput mode illustrated (Read Port).
RCLK
OR
Qout
Data Bus
Last Data Word
REN
6716 drw10
Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port)
AUGUST4,2005
25
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
STANDARDMODEOPERATION
Changingqueuesrequires4WCLKcyclesonthewriteport(seeFigure44,
WriteQueueSelect,WriteOperationandFullflagOperation).WADENgoes
highsignalingachangeofqueue(clockcycle“A”).Theaddress onWRADD
atthattimedeterminesthenextqueue.Datapresentedduringeachcycle,will
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARDMODE)
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con- bewrittentotheactivequeue,providedWENisLOW.IfWENisHIGH(inactive),
troldevices canbeconfigureduptoamaximumof8queues whichdatacan datawillnotbewritteninaqueue.Thewriteportdiscretefullflagwillupdateto
be written via a common write port using the data inputs (Din), write clock showthefullstatusofthenewlyselectedqueue.Datapresentonthedatainput
(WCLK)andwriteenable(WEN).Thequeuetobewrittenis selectedbythe bus (Din), canbe writtenintothe newlyselectedqueue onthe risingedge of
address presentonthewriteaddress bus (WRADD)duringarisingedgeon WCLKachangeofqueue,providedWENisLOWandthequeueisnotfull.If
WCLKwhilewriteaddressenable(WADEN)isHIGH.ThestateofWENdoes theselectedqueueisfullatthepointofitsselection,anywritestothatqueuewill
notimpactthequeueselection.Thequeueselectionrequires4WCLKcycle. be prevented. Data cannotbe writtenintoa fullqueue.
Allsubsequentdatawriteswillbetothisqueueuntilanotherqueueisselected.
Refer to Figure 44, Write Queue Select, Write Operation and Full flag
Standardmodeoperationisdefinedasindividualwordswillbewrittentothe Operation,Figure46, WriteOperations inFirstWordFallThroughfortiming
deviceasopposedtoPacketModewherecompletepacketsarewritten.The diagramsandFigure47,FullFlagTiminginExpansionConfigurationfortiming
write port is designed such that 100% bus utilization can be obtained. This diagrams.
means that data can be written into the device on every WCLK rising edge
includingthe cycle thata newqueue is beingaddressed.
TABLE 4 — WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN FSTR
WRADD[7:0]
7 6 5 4 3 2 1 0
Write
Queue
Select
1
0
0
1
Device Select
(Compared to
ID2,1,0)
Write Queue Address
(2 bits = 4 Queues
3 bits = 8 Queues)
7 6 5
4
3 2 1 0
PAFn
Quadrant
Select
Device Select
(Compared to
ID2,1,0)
X
Status Word
Address
Status Word
Address
Queue Status on PAFn Bus
Q0 : Q7 → PAF0 : PAF7
0000
6716 drw11
AUGUST4,2005
26
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
READ QUEUE SELECTION AND READ OPERATION
(STANDARDMODE)
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
obtained.ThismeansthatdatacanbereadoutofthedeviceoneveryRCLK
risingedge includingthe cycle that a newqueue is beingaddressed.
ChangingqueuesrequiresaminimumoffourRCLKcyclesonthereadport
troldevices canbe configureduptoa maximumof8queues whichdata can (see Figure 48, Read Queue Select, Read Operation). RADEN goes high
be read via a common read port using the data outputs (Qout), read clock signalingachangeofqueue(clockcycle“D”).TheaddressonRDADDatthat
(RCLK) and read enable (REN). An output enable, OE control pin is also time determines the next queue. Data presented during that cycle will be
providedtoallowHigh-ImpedanceselectionoftheQoutdataoutputs.Themulti- read.Readingdatacancontinuefromtheactive,providedRENisLOW.IfREN
queue device readportoperates instandardIDTmode and“FirstWordFall isHIGH(inactive)forthesetwoclockcycles,datawillnotbereadfromthequeue.
Through”mode(seeFigure46,WriteOperationsinFirstWordFallThrough). Ifanewselectedqueueisempty,anyreadsfromthatqueuewillbeprevented.
Thequeuetobereadisselectedbytheaddresspresentedonthereadaddress Datacannotbereadfromanemptyqueue. RememberthatOEallowstheuser
bus (RDADD) during a rising edge on RCLK while read address enable toplacethedataoutputbus(Qout)intoHigh-Impedanceandthedatacanbe
(RADEN)isHIGH.ThestateofRENdoesnotimpactthequeueselection.The readintotheoutputregisterregardless ofOE.
queueselectionrequires4RCLKcycles.Allsubsequentdatareadswillbefrom
thisqueueuntilanotherqueueisselected.
RefertoTable5,forReadAddressBusarrangement.Also,refertoFigures
13,15,and16forreadqueueselectionandreadportoperationtimingdiagrams.
Standardmodeoperationisdefinedasindividualwordswillbereadfromthe
device. The read port is designed such that 100% bus utilization can be
TABLE 5 — READ ADDRESS BUS, RDADD[7:0]
Operation
RCLK RADEN ESTR
RDADD[7:0]
7 6 5 4 3 2 1 0
Read Queue
Select
1
0
Device Select
(Compared to
ID2,1,0)
Read Queue Address
(2 bits = 4 Queues
3 bits = 8 Queues)
7 6 5
Device Select
(Compared to
ID2,1,0)
4
X
3 2 1 0
Status Word
Address
PAEn/PRn
Quadrant
Select
0
1
Status Word
Address
Queue Status on PAEn/PRn Bus
0000
Q0 : Q7 → PAF0 : PAF7
6716 drw12
AUGUST4,2005
27
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PACKETMODEOPERATION
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)
The Packet mode operation provides the capability where, user defined
Changingqueuesrequires4RCLKcyclesonthereadport(seeFigure55,
packetsorframescanbewrittentothedeviceasopposedtoStandardmode Reading in Packet Mode during a Queue Change). RADEN goes high
whereindividualwordsarewritten.Forclarification,inPacketMode,apacket signalinga change ofqueue (clockcycle “B”or“I”). The address onRDADD
canbewrittentothedevicewiththestartinglocationdesignatedasTransmitStart atthe risingedge ofRCLKdetermines the queue. As illustratedinFigure 55
ofPacket(TSOP)andtheendinglocationdesignatedasTransmitEndofPacket during cycle (“B” or “I”), and the next cycle (“C” or “J”) data can continue to
(TEOP). Inconjunction, a packetreadfromthe device willbe designatedas bereadfromtheactive(old)queue(QA orQBrespectively),providedbothREN
Receive StartofPacket(RSOP)anda Receive EndofPacket(REOP). The andOEareLOW(active)simultaneouslywithchangingqueues.Inapplications
minimumsizeforapacketisfourwords(SOP,twowordsofdataandEOP).The where the multi-queue flow-control device is connected to a shared bus, an
4words mustbe the largestwordthatis configured. Forexample ina x18to outputenable,OEcontrolpinisalsoprovidedtoallowHigh-Impedanceselection
x9busmatchingconfigurationthefourwordsmustbex18bitwords.Thealmost ofthedataoutputs(Qout).
emptyflagbus becomes the “PacketReady” PRflagbus whenthedeviceis
Refer to Figure 55, Reading in Packet Mode during a Queue Change as
configuredforpacketmode.ValidpacketsareindicatedwhenbothPRandOR wellasFigure38,39,40,41, and42fortimingdiagramsandTable5,forRead
areasserted.
Addressbusarrangement.
Note,thealmostemptyflagbusbecomesthe“PacketReady”flagbuswhen
WRITEQUEUESELECTIONANDWRITEOPERATION(PACKETMODE) thedeviceis configuredforpacketreadymode.
Changingqueuesrequires 4WCLKcyclesonthewriteport(seeFigure54,
WritinginPacketModeduringaQueueChange).WADENgoeshighsignaling EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES
achangeofqueue(clockcycle“B”or“I”).TheaddressonWRADDattherising
ExpansioncantakeplaceonlyinIDTStandardmode.Inthe8Queuemulti-
edgeofWCLKdeterminesthenextqueue.DatapresentedonDinduringthat queuedevice,theWRADDaddressbusis8bitswide.The7LeastSignificant
cycle (“B” or “I”) and the next cycle (“C” or “J”) can continue to be written to bits(LSbs)areusedtoaddressoneofthe32availablequeueswithinasingle
theactive(old)queue(QA orQB respectively),providedWENisLOW(active). multi-queuedevice.TheMostSignificantbit(MSbs)isusedwhenadeviceis
IfWENisHIGH(inactive)forthesetwoclockcycles(H),datawillnotbewritten connectedinexpansionconfigurationwithupto8devicesconnectedinwidth
intothepreviousqueue(QA). Thewriteportdiscretefullflagwillupdatetoshow expansion,eachdevicehavingitsownbitaddress.Whenlogicallyexpanded
thefullstatusofthenewlyselectedqueue(QB)atthislastcycle’srisingedge(“D” withmultipleparts,eachdeviceisstaticallysetupwithauniquechipIDcodeon
or“K”).Datavaluespresentedonthedatainputbus(Din),canbewritteninto theIDpins,ID0,ID1,andID2.AdeviceisselectedwhentheMostSignificant
thenewlyselectedqueue(QX)ontherisingedgeofWCLKonthethirdcycle bit of the WRADD address bus matches the ID code. The maximum logical
(“E”)followingarequestforchangeofqueue,providedWENisLOW(active) expansion is 64 queues (8 queues x 8 devices).
andthenewqueueisnotfull.Ifaselectedqueueisfull(FFisLOW),thenwrites
Note:TheWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag
tothatqueuewillbeprevented.Note,datacannotbewrittenintoafullqueue. busstrobe),toaddressthealmostfullflagbusduringdirectmodeofoperation.
RefertoFigure54,WritinginPacketModeduringaQueueChangefortiming
diagrams.
RefertoTable4,forWriteAddressbusarrangement.Also,refertoFigure
47,FullFlagTimingExpansionConfiguration,Figure51,OutputReadyFlag
Timing (In Expansion Configuration), and Figure 67, Expansion using ID
codes,fortimingdiagrams.
AUGUST4,2005
28
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SWITCHING QUEUES ON THE WRITE PORT
WriteAddressbus(WRADD)duringarisingedgeofWCLKwhileWriteAddress
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con- Enable(WADEN)isHIGH.Forreference,thestateofWriteEnable(WEN)is
troldevicescanbeconfigureduptoamaximumof8queues.Dataiswritteninto a“Don’tCare”duringaqueueselection.WENhassignificanceduringthequeue
aqueueusingtheDataInput(Din)bus,WriteClock(WCLK)andWriteEnable markoperation. Selectinga queue requires 4WCLKcycles. RefertoFigure
(WEN)signals.Selectingaqueueoccursbyplacingthequeueaddressonthe 7, Write PortSwitchingQueues SignalSequence.
Queue Switch Cycle
QS-1
QS0
QS1
QS2
QS3
WCLK
Queue
address
Queue
address
WRADD
WADEN
6716 drw13
Figure 7. Write Port Switching Queues Signal Sequence
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
Formaximumefficiency,duringthe4clockcyclesrequiredtoswitchqueues
troldevicesupportschanging(switching)queueseveryfour(4)clockcycles. theIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-control
To switch from the Present Queue (PQ) to another queue requires a queue devicecancontinuetowriteintothePresentQueue(PQ).ThePresentQueue
addresstobeplacedontheWriteAddressBus(WRADD)busandarisingedge isdefinedasthecurrentselectedqueue.RefertoFigure8,SwitchingQueues
ofWriteClock(WCLK)andWriteAddressEnable(WADEN)isHIGH.There BusEfficiency.
arenorestrictionsastotheordertowhichqueuesareselectedorswitchedinto
oroutof.
*
Queue Switch Cycles
WCLK
WEN
WADEN
PQ
PQ
PQ
PQ
NQ
NQ
Din
6716 drw14
NOTES:
1. PQ = Present Queue
NQ = Next Queue
* Requires 4 clock cycles to switch queues.
Figure 8. Switching Queues Bus Efficiency
AUGUST4,2005
29
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con- the write andreadports. The simultaneous queue switchingmayoccurwith
trol device supports writing and reading from either the same queue of from eithertheWriteClockandReadClocksynchronousorasynchronoustoeach
differentqueues.Thedevicealsosupportssimultaneousqueueswitchingon other. For reference refer to Figure 9, Simultaneous Queue Switching.
WCLK
WEN
WADEN
PQ
PQ
PQ
PQ
PQ
NQ
Din
RCLK
REN
RADEN
Qout
PQ
PQ
PQ
PQ
PQ
PQ
NQ
6716 drw15
Figure 9. Simultaneous Queue Switching
Themulti-queueflow-controldevicerequires4clockcyclestoswitchqueues
onthewriteport.RefertoTable6,WriteQueueSwitchOperationforadetailed
descriptionofeachqueueswitchclockcycle.
TABLE 6 — WRITE QUEUE SWITCH OPERATION
Queue Switch
Cycle
IDT Mode
FWFT Mode
QS-1
QS0
QS1
QS2
QueueSwitchInitiated,Rewrite/NoRewriteselection QueueSwitchInitiated,Rewrite/NoRewriteselection
Queue MARK / Un-MARK
—
Queue MARK / Un-MARK
—
• PAF signal updated for Next Queue (NQ)
• Packet Ready (PR) signal updated
• Full Flag (FF) updated for NQ
• PAF signal updated for Next Queue (NQ)
• Packet Ready (PR) signal updated
• IR flag updated for NQ
QS3
StartofWriteDataOperation
StartofWriteDataOperation
AUGUST4,2005
30
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SWITCHING QUEUES ON THE READ PORT
of RCLK while Read Address Enable (RADEN) is HIGH. For reference, the
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con- stateofReadEnable(REN)isa“Don’tCare”duringareadportqueueselection.
troldevicescanbeconfigureduptoamaximumof8queues.Dataisreadfrom REN has significance during the queue mark operation. Selecting a queue
a queue using the Data Output (Qout) bus, Read Clock (RCLK) and Read requires 4 WCLK cycles. Refer to Figure 10, Read Port Switching Queues
Enable (REN)signals. Selectinga queue onthe readportoccurs byplacing SignalSequence.
the queue address onthe ReadAddress bus (RDADD)duringa risingedge
Queue Switch Cycle
QS-1
QS0
QS1
QS2
QS3
RCLK
Queue
address
Queue
address
RDADD
RADEN
6716 drw16
Figure 10. Read Port Switching Queues Signal Sequence
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
Formaximumefficiency,duringthe4clockcyclesrequiredtoswitchqueues
troldevicesupportschanging(switching)queueseveryfour(4)clockcycles. theIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-control
To switch from the Present Queue (PQ) to another queue requires a queue devicecancontinuetoreadfromthePresentQueue(PQ).ThePresentQueue
addresstobeplacedontheReadAddressBus(RDADD)busandarisingedge isdefinedasthecurrentselectedqueue.RefertoFigure11,SwitchingQueues
of Read Clock (RCLK) and Read Address Enable (RADEN) is HIGH. There BusEfficiency.
arenorestrictionsastotheordertowhichqueuesareselectedorswitchedinto
oroutof.
Queue Switch Cycles
RCLK
REN
RADEN
PQ
PQ
PQ
PQ
PQ
NQ
NQ
Qout
6716 drw17
NOTE:
PQ = Present Queue
NQ = Next Queue
Figure 11. Switching Queues Bus Efficiency
AUGUST4,2005
31
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SIMULTANEOUS QUEUE SWITCHING
the readandwrite ports. The simultaneous queue switchingmayoccurwith
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con- eithertheReadClockandWriteClocksynchronousorasynchronoustoeach
trol device supports reading and writing from either the same queue of from other. For reference refer to Figure 12, Simultaneous Queue Switching.
differentqueues.Thedevicealsosupportssimultaneousqueueswitchingon
WCLK
WEN
WADEN
PQ
PQ
PQ
PQ
NQ
Din
RCLK
REN
RADEN
Qout
PQ
PQ
PQ
PQ
PQ
PQ
NQ
6716 drw18
Figure 12. Simultaneous Queue Switching
Themulti-queueflow-controldevicerequires4clockcyclestoswitchqueues
onthereadport,refertoTable7,ReadQueueSwitchOperationforadetailed
descriptionofeachqueueswitchclockcycles.
TABLE 7 — READ QUEUE SWITCH OPERATION
Queue Switch
Cycle
IDT Mode
FWFT Mode
QS-1
QS0
QS1
QS2
QueueSwitchInitiated,Re-read/NoRe-readselection QueueSwitchInitiated,Re-read/NoRe-readselection
Queue MARK / Un-MARK Queue MARK / Un-MARK
—
—
• PAE signal updated for Next Queue (NQ)
• Packet Ready (PR) signal updated
• Empty Flag (EF) updated for NQ
• PAE signal updated for Next Queue (NQ)
• Packet Ready (PR) signal updated
QS3
StartofReadDataOperation
• StartofReadData Operation
• OR updated for NQ
TABLE 8 — SAME QUEUE SWITCH
PQ
NQ
Supported
Comment
NotMarked
NotMarked
Marked
NotMarked
Marked
Yes
Yes
QueueSwitchisignored
Add Mark to current queue
Not Marked, No Reread
Not Marked, Reread
Marked, No Reread
Marked, Reread
NotAllowed
Yes
Marked
Remove Mark
Legend:
PQ = Present Queue
NQ = Next Queue
Marked
NotAllowed
Yes
Marked
Keep Mark
AUGUST4,2005
32
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
QUEUE MARKing
MARK AND REWRITE/ MARK AND REREAD
TheoverallintentoftheMARKfunctionistoprovidetheabilitytoeitherre-
writeand/orre-readinformationthatis storedintoaqueue.
TheMARKfunctionalityoperatesinanymodecombination (Packetmode,
IDTStandardMode,FIFOMode,FWFTMode),FWFT). QueuesontheWrite
AqueuecanbeMARKedbyeitherthewriteportorthereadport.TheMARK Portare MARKedusingthe WCLK& WADENsignals. Queues onthe Read
operationisportindependent.Thesamequeuecanbemarkedbythewriteport PortareMARKedusingtheRCLKandRADENsignals.Refertothefollowing
and the read port simultaneously. Only the active queue can be MARKed, timingdiagramsforadditionalqueueMARKdetails.RefertoFigure13through
multiplequeuescanNOTbeMARKedbyaport.Aport(writeorread)mayonly 18forfurtherinformation.
designateonequeueMARKedatatime. Uponaqueueswitchadecisionmust
bemadeastowhethertoreturntotheMarkedlocationorthelastaccessaddress.
A
QS-1
B
QS0
C
QS1
D
E
QS2
QS3
WCLK
WEN
QS
WADEN
DIN
Present Queue (PQ)
Next Queue (NQ)
6716 drw29
•
•
@QS-1, if WEN=0 and WADEN=1, PQ will be updated in QS0,1, and 2, and NQ data will be written in QS3.
@QS-1,ifWEN_N=1andWADEN=1,there is noupdate forPQduringQS0-QS2.Nexttime PQis switchedback,data willbe writtenintolastupdate
location(rewrite).
•
•
@QS0, WADENstatus is usedtodetermine if a “mark”is requestedforNQ. IfWADEN=1inQS0, NQwillbe marked. InFIFOmode, the firstNQ
positionafterQSis marked(latchWFCRvalues before QS3), data can’tbe readoutbeyondthis location. Inpacketmode, everySOPpositionis
markedtillnextSOPcomes,thenthemarkmovestonewposition.
@QS0,ifWADEN=0,NQisnotmarked.
Figure 13. MARK and Re-Write Sequence
A
QS-1
B
QS0
C
QS1
D
E
QS2
QS3
RCLK
REN
QS
RADEN
QOUT
Present Queue
Next Queue
6716 drw30
•
•
•
@QS-1(A),ifREN=0andRADEN=1,(requestforaQueueSwitchoccurs RADEN=1andsimultaneouslyreadingfromaqueue)theQueueAddress
Register will be updated in QS2, and the data from the Next Queue (NQ) will be available in QS3.
@QS-1,ifREN=1andRADEN=1,(requestforaQueueSwitchoccurs RADEN=1)theQueueAddress RegisterwillbeupdatedinQS2.ThePresent
Queueaddress pointerwillnotincrementduringQS0-QS2.TheNexttimePQis selected,thedatawillbefromthelastaddressedlocation.
@QS0,RADENstatusisusedtodetermineifa“mark”isrequestedforNQ.IfRADEN=1inQS0,NQwillbemark.InFIFOmode,firstNQpositionafter
QSismarked(latchRFCRvaluesbeforeQS3),datacan’t overwritethislocation.Inpacketmode,everySOPpositionismarkedtillnextSOPcomes,
thenthemarkmovestonewposition.
Figure 14. MARK and Re-Read Sequence
AUGUST4,2005
33
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
This rising edge of
WCLK is the start of
the 1st cycle
Write Queue MARK
A
B
Wri te Queue
Select Cycle
Write Queue
MARK Cycle
WCLK
WADEN
WADEN
ACTION
A
B
1
1
1
0
Selects a Queue & MARK the Queue
Selects a Queue
6716 drw31
Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK
Read Queue MARK
This rising edge of RCLK is
the start of the 1st cycle
B
A
Read Queue
Select Cycle
Read Queue
MARK Cycle
RCLK
RADEN
RADEN
ACTION
A
B
1
1
1
0
Selects a Queue & MARK the Queue
Selects a Queue
6716 drw32
Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK
AUGUST4,2005
34
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
This rising edge of
WCLK isthestart
Write Queue UN-MARK
of the 1st cycle.
B
A
Write Queue
Select Cycle
Write Queue
MARK Cycle
WCLK
WADEN
WADEN
ACTION
B
A
1
1
1
0
Selects a Queue and MARK the Queue
Selects a Queue and Remove MARK
6716 drw33
Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK
This rising edge of
RCLK isthestart
Read Queue UN-M A RK
of the 1st cycle.
B
A
Read Queue
Select Cycle
Read Queue
MARK Cycle
RCLK
RADEN
RADEN
ACTION
B
A
1
1
1
0
Selects a Queue and MARK the Queue
Selects a Queue & Remove MARK
6716 drw34
Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK
AUGUST4,2005
35
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARKOPERATIONAL NOTES:
IN PACKET MODE
WritePort
-
-
-
-
-
-
-
MARKing a location can only occur during a Queue switch cycle
There is only one MARKed location within a Queue
Only1packetcanbe MARKedata time withina Queue.
Inpacketmode,forafullpacketre-writetheMARKmustoccurattheSOPlocationofthepacket.
Inpacketmodedatacanbere-writtenfromtheMARK
InpacketmodetheMARKmovesfrompackettopacketwithinaqueuewhenthenextpacketiswritten.
The sequence tomove the MARKtothe nextpacketis, firstanEOPmustoccur, thena validwrite occurs.
MARK Move Sequence
EOP
SOP
Queue MARK
6716 drwX35
ReadPort
- MARKing can only occur during a Queue switch cycle
-
-
Only1packetcanbe MARKedata time withina Queue.
Inpacketmode,MARKismovedtoalocationofthepacket.
- Inpacketmode the MARKcanbe movedfromSOP(startofpacket)toSOP(startofpacket)withinthe queue bya validread.
AUGUST4,2005
36
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
This rising edge of
Wri te Queue M A RK
WCLK isthestart of the
1st cycle
A
B
Wri te Queue
Select Cycle
Write Queue
MARK Cycle
WCLK
WADEN
WADEN
ACTION
B
A
1
1
1
0
Selects the Queue and MARK the Queue
Selects a Queue
6716 drw36
Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK
This rising edge of
Read Queue MARK
RCLK isthestart
of the1st cycle
A
B
Read Queue
Select Cycle
Read Queue
MARK Cycle
RCLK
RADEN
RADEN
ACTION
B
A
1
1
1
0
Selects the Queue and MARK the Queue
Selects a Queue
6716 drw37
Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK
MARK Operational Notes:
In FIFO Mode
WritePort
ReadPort
-
-
-
MARKing can only occur during a Queue switch cycle
The entire Queue is MARKedata time.
InIDTStandard/FWFTmode,MARKisusedtomarkthefirstlocation
-
-
MARKing can only occur during a Queue switch cycle
OnlythefirstlocationoftheQueuecanbeMARKedinStandard/FWFT
mode.
oftheQueue.
-
InIDTStandardmodetheMARKcanNOTbemovedlocationtolocation
withinthequeue.
-
InIDTStandard/FWFTmodetheMARKcanNOTbemovedwithinthe
queue.
AUGUST4,2005
37
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Un-MARKing a Queue
UN-MARKing a Queue in FIFO Mode
This rising edge of
Write Queue UN-MARK
WCLK i s the start
of the1st cycle
A
B
Write Queue
Select Cycle
Write Queue
MARK Cycle
WCLK
WADEN
WADEN
ACTION
B
A
1
0
Selects a Queue and UN-MARK the Queue
6716 drw38
Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK
This rising edge of
Read Queue UN-MARK
RCLK isthestart
of the1st cycle
A
B
Read Queue
Select Cycle
Read Queue
MARK Cycle
RCLK
RADEN
RADEN
ACTION
B
A
1
0
Selects a Queue and UN-MARK the Queue
6716 drw39
Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK
UN-MARK Operational Notes:
In FIFO Mode
WritePort
ReadPort
-
-
Un-MARKing can only occur during a Queue switch cycle.
-
-
Un-MARKing can only occur during a Queue switch cycle.
InFIFOMode,UN-MARKingaQueuecanbeaccomplishedbyeither
switchingtothesamequeueorswitchingtoanotherqueue.
Note only 1 queue can be marked at any given time.
InStandard/FIFOmode the MARKcanNOTbe movedlocationto
locationwithinthequeue.
InStandard/FIFOmode,UN-MARKingaQueuecanbeaccomplished
byeitherswitchingtothesamequeueorswitchingtoanotherqueue.
Note only 1 queue can be marked at any given time.
InStandard/FIFOmode the MARKcanNOTbe movedlocationto
locationwithinthequeue.
-
-
-
-
AUGUST4,2005
38
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Leaving a MARK Active
DuringaQueueswitchthevalueofWENforthewriteportandRENforthe
readportdetermineswhethertheMARKremainsactiveorisde-activated.
Leaving a MARK active on the Write Port
Write Queue
Select Cycle
Write Queue
MARK Cycle
WCLK
WADEN
Leave the MARK
WEN
(A rewrite
request)
6716 drw40
Figure 23. Leaving a MARK active on the Write Port
Leaving a MARK active on the Read Port
Read Queue
Select Cycle
Read Queue
MARK Cycle
RCLK
RADEN
Leave the MARK
REN
(A re-read
request)
6716 drw41
Figure 24. Leaving a MARK active on the Read Port
AUGUST4,2005
39
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Inactivating a MARK
DuringaQueueswitchthevalueofWENforthewriteportandRENforthe
readportdetermineswhethertheMARKremainsactiveorisde-activated.
Inactivating a MARK on the Write Port
Write Queue
Select Cycle
Write Queue
MARK Cycle
WCLK
WADEN
Inactivate the
Write Port MARK
WEN
6716 drw42
(No re-write)
Figure 25. Inactivating a MARK on the Write Port Active
Inactivating a MARK on the Read Port
Read Queue
Select Cycle
Read Queue
MARK Cycle
RCLK
RADEN
Inactivate the
Read Port MARK
REN
6716 drw43
(No re-read)
Figure 26. Inactivating a MARK on the Read Port Active
AUGUST4,2005
40
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Write Cycle
1st Cycle
2nd Cycle
WEN
(active LOW)
WEN
(active LOW)
0
Action
WADEN
(active HIGH)
0
WADEN
(active HIGH)
0
NO
0
Operation
Selects a
Queue
NO
Operation
NO
0
1
1
1
0
1
1
0
0
1
1
1
Operation
6716 drw44
Read Cycle
Action
1st Cycle
2nd Cycle
REN
REN
(active LOW)
0
RADEN
(active HIGH)
0
RADEN
(active HIGH)
0
(active LOW)
NO
0
0
1
1
Operation
Selects a
Queue
NO
Operation
NO
0
1
1
1
0
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6716 drw45
AUGUST4,2005
41
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
madeonlyasingledevicedrivestheFFflagbusandallotherFF flagoutputs
connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control
devicewillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhennone
ofitsqueuesareselectedforwriteoperations.
FLAGDESCRIPTION
PAFn FLAG BUS OPERATION
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
trol device can be configured for up to 8 queues, each queue having its own
almostfullstatus.Anactivequeuehasitsflagstatusoutputtothediscreteflags,
FFandPAF,onthewriteport.Queuesthatarenotselectedforawriteoperation
canhavetheirPAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis
8bitswide,sothat8queuesatatimecanhavetheirstatusoutputtothebus.
If9ormorequeuesaresetupwithinadevicethenthereare2methodsbywhich
thedevicecansharethebusbetweenqueues,“Direct”modeand“Polled”mode
dependingonthestateoftheFM(FlagMode)inputduringaMasterReset.If
8orlessqueuesaresetupwithinadevicetheneachwillhaveitsowndedicated
outputfromthe bus. If8orless queues are setupinsingle device mode, itis
recommendedtoconfigurethePAFnbustopolledmodeasitdoesnotrequire
usingthewriteaddress (WRADD).
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF
flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill
simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased
onthe1-3bitIDcode(1iftwomulti-queueareconfiguredwithamaximumtotal
of256queues,2iffourdevicesareusedtotallingamaximumof256queues,
and3ifthereareuptoeightdeviceswithamaximumtotalof256queues)found
inthe1-3mostsignificantbitsofthewritequeueaddressbus,WRADD.Ifthe
1-3mostsignificantbitsofWRADDmatchthe1-3bitIDcodesetuponthestatic
inputs,ID0,ID1andID2thentheFFflagoutputoftherespectivedevicewillbe
inaLow-Impedancestate.Iftheydonotmatch,thentheFFflagoutputofthe
respectivedevicewillbeinaHigh-Impedancestate.SeeFigure47,FullFlag
TiminginExpansionConfigurationfordetailsofflagoperation,includingwhen
more thanone device is connectedinexpansion.
FULL FLAG OPERATION
Themulti-queueflow-controldeviceprovidesasingleFullFlagoutput,FF.
TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
writeportforwriteoperations.Internallythemulti-queueflow-controldevice
monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.
Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
onthe3rdcycleafteranewqueueselectionismade.Theuserthenhasafull
status forthenewqueueonecycleaheadoftheWCLKrisingedgethatdata
can be written into the new queue. That is, a new queue can be selected on
thewriteportviatheWRADDbus,WADENenableandarisingedgeofWCLK.
Onthe4thrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthe
newlyselectedqueue.OntheforthrisingedgeofWCLKfollowingthequeue
selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata
andenablesetup&holdtimesaremet.
Note,theFFflagwillprovidestatusofanewlyselectedqueuethreeWCLK
cycleafterqueueselection,whichisonecyclebeforedatacanbewrittentothat
queue.Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assuming
thataqueueswitchhas beenmadetoaqueuethatis actuallyfull).
TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur
basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand
keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa
FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue
flag (selected on the write port). A queue selected on the read port may
experienceachangeofitsinternalfullflagstatusbasedonreadoperations.
See Figure 44, Write Queue Select, Write Operation and Full Flag
OperationandFigure47,FullFlagTiminginExpansionConfigurationfortiming
information.
EMPTYOROUTPUTREADYFLAGOPERATION(EF/OR)
The multi-queue flow-control device provides a single Empty or Output
Readyflagoutput,EF/OR.TheOR provides anemptystatus ordataOutput
Readystatusforthedatawordcurrentlyavailableontheoutputregisterofthe
readport.TherisingedgeofanRCLKcyclethatplacesnewdataontotheoutput
registerofthereadport,alsoupdatestheORflagtoshowwhetherornotthat
newdatawordisactuallyvalid.Internallythemulti-queueflow-controldevice
monitorsandmaintainsastatusoftheemptyconditionofallqueueswithinit,
howeveronlythequeuethatisselectedforreadoperationshasitsOutputReady
(empty)statusoutputtotheORflag,givingavalidstatusforthewordbeingread
atthattime.
Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast
datawordisreadfromaselectedqueue,theORflagwillgoHIGHonthenext
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
Whenqueueswitchesarebeingmadeonthereadport,theORflagwillswitch
toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue.
Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon
theQoutdataoutputs4RCLKcycleslater,theORwillchangestatetoindicate
validityofthedatafromthenewlyselectedqueueonthis3rd RCLKcyclealso.
Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand
theORflagwillindicatethestatusofthoseoutputs.Again,theORflagalways
indicatesstatusforthedatacurrentlypresentontheoutputregister.
TheORflagissynchronoustotheRCLKandalltransitionsoftheORflagoccur
basedonarisingedgeofRCLK.Internallythemulti-queuedevicemonitorsand
keepsarecordoftheOutputReady(empty)statusforallqueues.Itispossible
that the status of an OR flag may be changing internally even though that
respectiveflagisnottheactivequeueflag(selectedonthereadport).Aqueue
selectedonthewriteportmayexperienceachangeofitsinternalORflagstatus
basedonwriteoperations,thatis,datamaybewrittenintothatqueuecausing
ittobecome“notempty”.
EXPANSION CONFIGURATION - FULL FLAG OPERATION
Whenmulti-queuedevicesareconnectedinExpansionconfigurationtheFF
flagsofalldevicesshouldbeconnectedtogether,suchthatasystemcontroller
monitoring and managing the multi-queue devices write port only looks at a
singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag
isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime.
Remember,thatwheninexpansionconfigurationonlyonemulti-queuedevice
canbewrittentoatanymomentintime,thustheFFflagprovidesstatusofthe
active queue onthe write port.
SeeFigure48,ReadQueueSelect,ReadOperationandFigure51,Output
ReadyFlagTimingfordetailsofthetiming.
EXPANSION–EMPTYFLAGOPERATION
Whenmulti-queuedevicesareconnectedinExpansionconfiguration,theEF
flagsofalldevicesshouldbeconnectedtogether,suchthatasystemcontroller
monitoring and managing the multi-queue devices read port only looks at a
singleEFflag(asopposedtoadiscreteEFflagforeachdevice).ThisEFflag
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis
AUGUST4,2005
42
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
is onlypertinenttothequeuebeingselectedforreadoperations atthattime.
SothePAFflagdelayfromawriteoperationtoPAFflagLOWis2WCLK+
Remember,thatwheninexpansionconfigurationonlyonemulti-queuedevice tWAF.ThedelayfromareadoperationtoPAFflagHIGHistSKEW2 +WCLK+
canbereadfromatanymomentintime,thustheEFflagprovidesstatusofthe tWAF.
active queue on the read port.
Note, if tSKEW is violated there will be one added WCLK cycle delay.
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheEFflag
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis occur based on a rising edge of WCLK. Internally the multi-queue device
madeonlyasingledevicedrivestheEFflagbusandallotherEFflagoutputs monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible
connectedtotheEFflagbusareplacedintoHigh-Impedance.Theuserdoes thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe
devicewillautomaticallyplaceitsEFflagoutputintoHigh-Impedancewhennone readportmayexperienceachangeofitsinternalalmostfullflagstatusbased
ofitsqueuesareselectedforreadoperations.
on read operations. The multi-queue flow-control device also provides a
Whenqueueswithinasingledeviceareselectedforreadoperations,theEF duplicateofthePAFflagonthePAF[7:0]flagbus,thiswillbediscussedindetail
flagoutputofthatdevicewillmaintaincontroloftheEFflagbus.ItsEFflagwill inalatersectionofthedatasheet.
simplyupdatebetweenqueueswitchestoshowtherespectivequeuestatus.
SeeFigures 23and24forAlmostFullflagtimingandqueueswitching.
Themulti-queuedeviceplacesitsEFflagoutputintoHigh-Impedancebased
onthe1-3bitIDcode(1iftwomulti-queueareconfiguredwithamaximumtotal ALMOSTEMPTYFLAG
of256queues,2iffourdevicesareusedtotallingamaximumof256queues,
As previously mentioned the multi-queue flow-control device provides a
and3ifthereareuptoeightdeviceswithamaximumtotalof256queues)found single Programmable Almost Empty flag output, PAE. The PAE flag output
inthe3mostsignificantbitsofthereadqueueaddressbus,RDADD.Ifthe3most providesastatusofthealmostemptyconditionfortheactivequeuecurrently
significantbitsofRDADDmatchthe1-3bitIDcodesetuponthestaticinputs,ID0, selectedonthereadportforreadoperations.Internallythemulti-queueflow-
ID1andID2thenthe EF flagoutputofthe respective device willbe ina Low- controldevicemonitorsandmaintainsastatusofthealmostemptyconditionof
Impedancestate.Iftheydonotmatch,thentheEFflagoutputoftherespective allqueueswithinit,howeveronlythequeuethatisselectedforreadoperations
devicewillbeinaHigh-Impedancestate.SeeFigure51,OutputReadyFlag hasitsemptystatusoutputtothePAEflag.Thisdedicatedflagisoftenreferred
Timing for details of flag operation, including when more than one device is toasthe“activequeuealmostemptyflag”.ThepositionofthePAEflagboundary
connectedinexpansion.
withinaqueuecanbeatanypointwithinthatqueuesdepth.Thislocationcan
beuserprogrammedviatheserialportoroneofthedefaultvalues(8or128)
canbeselectediftheuserhasperformeddefaultprogramming.
ALMOST FULL FLAG
As previously mentioned the multi-queue flow-control device provides a
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost
singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia
astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti-
writeportforwriteoperations.Internallythemulti-queueflow-controldevice queuedeviceprogramming(alongwiththenumberofqueues,queuedepths
monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe
it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice
almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe canbedifferentvalues.
atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed
viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
userhasperformeddefaultprogramming. onthethirdcycleafteranewqueueselectionismade,onthesameRCLKcycle
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost thatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.That
fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe is,anewqueuecanbeselectedonthereadportviatheRDADDbus,RADEN
PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue enableandarisingedgeofRCLK.OnthethirdrisingedgeofRCLKfollowing
device programming (along with the number of queues, queue depths and a queue selection, the data wordfromthe newqueue willbe available atthe
almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe outputregisterandthePAEflagoutputwillshowtheemptystatusofthenewly
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory selectedqueue.ThePAEisflagoutputisdoubleregisterbuffered,sowhena
depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice readoperationoccursatthealmostemptyboundarycausingtheselectedqueue
canbedifferentvalues.
statustogoalmostemptythePAEwillgoLOW2RCLKcyclesaftertheread.
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput Thesameistruewhenawriteoccurs,therewillbea3RCLKcycledelayafter
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus, thewriteoperation.
onthethirdcycleafteranewqueueselectionismade,onthesameWCLKcycle
thatdata canactuallybe writtentothe newqueue. Thatis, a newqueue can tRAE.ThedelayfromawriteoperationtoPAEflagHIGHis tSKEW2 +RCLK+
beselectedonthewriteportviatheWRADDbus,WADENenableandarising tRAE.
SothePAEflagdelayfromareadoperationtoPAEflagLOWis2RCLK+
edgeofWCLK.OnthethirdrisingedgeofWCLKfollowingaqueueselection,
Note, if tSKEW is violated there will be one added RCLK cycle delay.
thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue.ThePAF
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag
isflagoutputisdoubleregisterbuffered,sowhenawriteoperationoccursat occur based on a rising edge of RCLK. Internally the multi-queue device
thealmostfullboundarycausingtheselectedqueuestatustogoalmostfullthe monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
PAFwillgoLOW2WCLKcyclesafterthewrite.Thesameistruewhenaread thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis
occurs, there will be a 2 WCLK cycle delay after the read operation.
nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe
AUGUST4,2005
43
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased synchronizetothePAFnbus,FSYNCisalwaysHIGHfortheWCLKcyclethat
on write operations. The multi-queue flow-control device also provides a the firststatus wordofa device is presentonthe PAFnbus.
duplicateofthePAEflagonthePAE[7:0]flagbus,thiswillbediscussedindetail
inalatersectionofthedatasheet.
Whendevicesareconnectedinexpansionconfiguration,onlyonedevice
willbesetastheMaster(ID='000'),MASTinputtiedHIGH,allotherdevices
SeeFigures25and26forAlmostEmptyflagtimingandqueueswitching. willhaveMASTtiedLOW.Themasterdeviceisthefirstdevicetotakecontrol
ofthePAFnbusandwillplaceitsfirststatuswordonthebusontherisingedge
ofWCLK. ForthenextnWCLKcycles(n=numberofqueuesdividedby8with
PAFn - DIRECT BUS
IfFMisLOWatmasterresetthenthePAFnbusoperatesinDirect(addressed) nbeingincreasedbyone foranyremainder)the masterdevice willmaintain
mode. In direct mode the user can address the status word of queues they controlofthePAFnbusandcycleitsstatuswordsthroughit,allotherdevices
require and it will be placed on to the PAFn bus. For example, consider the holdtheirPAFnoutputsinHigh-Impedance.Whenthemasterdevicehascycled
operationofthePAFnbuswhen26queueshavebeensetup.Tooutputstatus allofitsstatuswordsitpassesatokentothenextdeviceinthechainandthat
ofthefirststatusword,Queue[0:7]theWRADDbusisusedinconjunctionwith deviceassumescontrolofthePAFnbusandthencyclesitsstatuswordsand
the FSTR (PAF flag strobe) input and WCLK. The address present on the 4 soon,thePAFnbuscontroltokenbeingpassedonfromdevicetodevice.This
leastsignificantbitsoftheWRADDbuswithFSTRHIGHwillbeselectedasthe tokenpassingisdoneviatheFXOoutputsandFXIinputsofthedevices(“PAF
status word address on a rising edge of WCLK. To address status word 0, ExpansionOut”and“PAFExpansionIn”).TheFXOoutputofthemasterdevice
Queue[0:7]theWRADDbusshouldbeloadedwith“0010000”,thePAFnbus connectstotheFXIoftheseconddeviceinthechainandtheFXOofthesecond
willchangestatustoshowthenewstatuswordselected1WCLKcycleafterstatus connectstotheFXIofthethirdandsoon.ThefinaldeviceinachainhasitsFXO
wordselection.PAFn[0:7]getsstatusofqueues,Queue[0:7]respectively.
connectedtotheFXIofthefirstdevice,sothatoncethePAFnbushascycled
Toaddressstatusword1,Queue[8:15],theWRADDaddressis“00100001”. throughallstatuswordsofalldevices,controlofthePAFnwillpasstothemaster
PAFn[0:7]getsstatusofqueues,Queue[8:15]respectively.Toaddressthe2nd device again and so on. The FSYNC of each respective device will operate
statusword,Queue[16:23],theWRADDaddressis“00100010”.PAF[0:7]gets independentlyandsimplyindicatewhenthatrespectivedevicehastakencontrol
statusofqueues,Queue[16:23]respectively.Toaddressthe3rdstatusword, ofthebus andis placingits firststatus wordontothePAFnbus.
Queue[24:31], the WRADD address is “00100011”. PAF[0:1] gets status of
WhenoperatinginsingledevicemodetheFXIinputmustbeconnectedto
queues,Queue[24:25]respectively.Remember,only26queuesweresetup, theFXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
sowhenstatusword4isselectedtheunusedoutputsPAF[2:7]willbedon'tcare tobe passedintothe device foraccessingthePAFnbus.
states.
Note, that if a read or write operation is occurring to a specific queue, say
queue‘x’onthesamecycleasastatuswordswitchwhichwillincludethequeue PAEn/PRn FLAG BUS OPERATION
PleaserefertoFigure66,PAFnBus–PolledModefortiminginformation.
‘x’,thentheremaybeanextraWCLKcycledelaybeforethatqueuesstatusis
TheIDT72P51339/72P51349/72P51359/72P51369multi-queueflow-con-
correctlyshownontherespectiveoutputofthePAFnbus.However,theactive trol device can be configured for up to 8 queues, each queue having its own
PAFflagwillshowcorrectstatusatalltimes.
almostempty/packetreadystatus.Anactivequeuehasitsflagstatusoutputto
Statuswordscanbeselectedonconsecutiveclockcycles,thatisthestatus the discrete flags, OR, PAE and PR, on the read port. Queues that are not
wordonthePAFnbuscanchangeeveryWCLKcycle.Also,datapresenton selectedforareadoperationcanhavetheirPAE/PRstatusmonitoredviathe
theinputbus,Din,canbewrittenintoaQueueonthesameWCLKrisingedge PAEn/PRnbus. The PAEn/PRnflagbus is 8bits wide, sothat8queues ata
thatastatuswordisbeingselected,theonlyrestrictionbeingthatawritequeue timecanhavetheirstatusoutputtothebus.If9ormorequeuesaresetupwithin
selectionandPAFnstatuswordselectioncannotbemadeonthesamecycle. a device then there are 2 methods by which the device can share the bus
If8orlessqueuesaresetupthenqueues,Queue[0:7]havetheirPAFstatus betweenqueues,"Direct"modeand"Polled"modedependingonthestateof
outputonPAF[0:7]constantly.
theFM(FlagMode)inputduringaMasterReset.If8orlessqueuesaresetup
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone withinadevicetheneachwillhaveitsowndedicatedoutputfromthebus.If8
devicethePAFnbussesofalldevicesareconnectedtogether,whenswitching orlessqueuesaresetupinsingledevicemode,itisrecommendedtoconfigure
betweenstatus words ofdifferentdevices the usermustutilize the 1-3most the PAFn bus to polled mode as it does not require using the write address
significantbitsoftheWRADDaddressbus(aswellasthe2LSB’s).These1- (WRADD).
3MSb’scorrespondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1
& ID2.
Please refer to Figure 63 PAFn - Direct Mode Status Word Selection for
PAEn/PRn - DIRECT BUS
If FM is LOW at master reset then the PAEn/PRn bus operates in Direct
(addressed) mode. In direct mode the user can address the status word of
queues they require to be placed on to the PAEn/PRn bus. For example,
considertheoperationofthePAEn/PRnbuswhen26queueshavebeensetup.
timinginformation.AlsorefertoTable4,WriteAddressBus,WRADD.
PAFn – POLLED BUS
IfFMisHIGHatmasterresetthenthePAFnbusoperatesinPolled(looped) Tooutputstatusofthefirststatusword,Queue[0:7]theRDADDbusisusedin
mode.InpolledmodethePAFnbusonlycyclesthroughthenumberofstatus conjunctionwiththeESTR(PAE/PRflagstrobe)inputandRCLK.Theaddress
words requiredtodisplaythestatus ofthenumberofqueues thathavebeen presentonthe2leastsignificantbitsoftheRDADDbuswithESTRHIGHwill
setupinthepart.EveryrisingedgeoftheWCLKcausesthenextstatusword beselectedasthestatuswordaddressonarisingedgeofRCLK.Sotoaddress
to be loaded on the PAFn bus. The device configured as the master (MAST statusword1,Queue[0:7]theRDADDbusshouldbeloadedwith“xxxx0000”,
inputtiedHIGH),willtakecontrolofthePAFnafterMRSgoesLOW.Forthewhole thePAEn/PRnbuswillchangestatustoshowthenewstatuswordselected1
WCLKcyclethatthefirststatuswordisonPAFntheFSYNC(PAFnbussync) RCLK cycle after status word selection. PAEn[0:7] gets status of queues,
outputwillbeHIGH,forallotherstatuswords,thisFSYNCoutputwillbeLOW. Queue[0:7]respectively.
This FSYNC output provides the user with a mark with which they can
Toaddress thesecondstatus word,Queue[8:15],theRDADDaddress is
“xxxx0001”. PAEn[0:7]gets status ofqueues,Queue[8:15]respectively.To
AUGUST4,2005
44
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 9 — FLAG OPERATION BOUNDARIES & TIMING
Output Ready, EF Flag Boundary
Full Flag, FF Boundary
FF Boundary Condition
I/O Set-Up
EF Boundary Condition
I/O Set-Up
In36 to out36
In36 to out36 (Almost Empty Mode)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
EF Goes LOWafterLastRead
FF Goes LOW after D+1 Writes
(Bothportsselectedforsamequeue
(seenotebelowfortiming)
when the 1st Word is written in)
In36 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
In36toout36(PacketMode)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
EF Goes LOWafterLastRead
EF Goes LOWafterLastRead
EF Goes LOWafterLastRead
EF Goes LOWafterLastRead
EF Goes LOWafterLastRead
(seenotebelowfortiming)
In36 to out18
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In36 to out18
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36 to out9
(Writeportonlyselectedforqueue
(Bothportsselectedforsamequeue
when the 1st Word is written in)
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(seenotebelowfortiming)
In18 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(seenotebelowfortiming)
In9 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
(Writeportonlyselectedforqueue
when the 1st Word is written in)
In18 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 2) Writes
(seenotebelowfortiming)
In18 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
(seenotebelowfortiming)
In9 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 4) Writes
(seenotebelowfortiming)
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up PAF & PAFn Boundary
In9 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 4) Writes
(seenotebelowfortiming)
in36 to out36
PAF/PAFn Goes LOW after
(Bothportsselectedforsamequeuewhenthe1st D+1-mWrites
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
NOTE:
in36 to out36
PAF/PAFn Goes LOW after
(Writeportonlyselectedforsamequeuewhenthe D-mWrites
D = Queue Depth
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
in36 to out18
in36 to out9
in18 to out36
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(seenotebelowfortiming)
in9 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 4) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
AUGUST4,2005
45
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 9 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary
I/O Set-Up PAE Assertion
PAE Goes HIGH after n+2
(Bothportsselectedforsamequeuewhenthe1st Writes
Programmable Almost Empty Flag Bus, PAEn Boundary
I/O Set-Up PAEn Boundary Condition
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st n+2Writes
in36 to out36
in36 to out36
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in36 to out36
PAEn Goes HIGH after
in36 to out18
PAE Goes HIGH after n+1
(Bothportsselectedforsamequeuewhenthe1st Writes
(Writeportonlyselectedforsamequeuewhenthe n+1Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in36 to out18
in36 to out9
in18 to out36
PAEn Goes HIGH after n+1
in36 to out9
PAE Goes HIGH after n+1
Writes (seebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st Writes
PAEn Goes HIGH after n+1
Writes(seebelowfortiming)
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
in18 to out36
PAE Goes HIGH after
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
PAE Goes HIGH after
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in9 to out36
in18 to out36
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 4) Writes
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
NOTE:
in9 to out36
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 4) Writes
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
PAEn Goes HIGH after
in9 to out36
PAE Timing
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 4) Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
NOTE:
Assertion:
Read Operation to PAE LOW: 2 RCLK + tRAE
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
Read Operation to PAEn LOW: 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
PACKETREADYFLAG,PRBOUNDARY
Assertion:
PACKET READY FLAG BUS, PRn BOUNDARY
Assertion:
Both the rising and falling edges of PR are synchronous to RCLK.
Both the rising and falling edges of PRn are synchronous to RCLK.
PR Falling Edge occurs upon writing the first TEOP marker, on input D35, PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a (assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a
completepacketisavailablewithinaqueue.
completepacketisavailablewithinaqueue.
Timing:
Timing:
FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4 FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4
+ 2 RCLK + tPR
+ 2 RCLK* + tPAE
IftSKEW4isviolated:
PR goes LOW after tSKEW4 + 3 RCLK + tPR
De-assertion:
If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionthere
may be one additional RCLK clock cycle delay.
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34. De-assertion:
i.e.therearenomorecompletepacketsavailablewithinthequeue.
Timing:
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e.therearenomorecompletepacketsavailablewithinthequeue.
From RCLK rising edge Reading the RSOP word the PR goes HIGH after: Timing:
3 RCLK + tPR
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
(PleaserefertoFigure57,DataOutput(Receive)PacketModeofOperation 3 RCLK* + tPAE
fortimingdiagram).
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionor
de-assertionthere maybe one additionalRCLKclockcycle delay.
AUGUST4,2005
46
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
addressthethirdstatusword,Queue[16:23],theRDADDaddressis“xxxx0010”. independentlyandsimplyindicatewhenthatrespectivedevicehastakencontrol
PAE[0:7]gets status ofqueues, Queue[16:23]respectively. Toaddress the ofthebus andis placingits firststatus wordontothePAEn/PRnbus.
fourth status word, Queue[24:31], the RDADD address is “xxxx0011”.
WhenoperatinginsingledevicemodetheEXIinputmustbeconnectedto
PAE[0:1]getsstatusofqueues,Queue[24:25]respectively.Remember,only theEXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
26queuesweresetup,sowhenstatusword4isselectedtheunusedoutputs tobepassedintothedeviceforaccessingthePAEnbus.
PAE[2:7]willbedon'tcarestates.
Note, that if a read or write operation is occurring to a specific queue, say PACKETREADYFLAG
queue‘x’onthesamecycleasastatuswordswitchwhichwillincludethequeue
‘x’,thentheremaybeanextraRCLKcycledelaybeforethatqueuesstatusis Readyfeature.DuringaMasterResetPacketModeisselectedbyPKT=HIGH.
correctlyshownontherespectiveoutputofthePAEn/PRnbus. ThePRdiscreteflag,providesapacketreadystatusoftheactivequeueselected
The36-bitmulti-queueflow-controldeviceprovidestheuserwithaPacket
Statuswordscanbeselectedonconsecutiveclockcycles,thatisthestatus onthereadport.Apacketreadystatusisindividuallymaintainedonallqueues;
wordonthePAEn/PRnbuscanchangeeveryRCLKcycle.Also,datacanbe howeveronlythequeueselectedonthereadporthasitspacketreadystatus
readoutofaQueueonthesameRCLKrisingedgethatastatuswordisbeing indicatedonthePRoutputflag.Apacketisavailableontheoutputforreading
selected,theonlyrestrictionbeingthatareadqueueselectionandPAEn/PRn whenbothPRandORareassertedLOW.Iflessthanafullpacketisavailable,
statuswordselectioncannotbemadeonthesameRCLKcycle.
If8orless queues aresetupthenqueues,Queue[0:7]havetheirPAE/PR readfroma queue untila complete packethas beenwrittenintothatqueue,
statusoutputonPAE[0:7]constantly.
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone
thePRflagwillbeHIGH(packetnotready).Inpacketmode,nowordscanbe
regardless ofREN.
WhenpacketmodeisselectedtheProgrammableAlmostEmptybus,PAEn,
device the PAEn/PRn busses of all devices are connected together, when becomes thePacketReadybus,PRn.WhenconfiguredinDirectBus (FM=
switchingbetweenstatuswordsofdifferentdevicestheusermustutilizethe3 LOW during a master reset), the PRn bus provides packet ready status in 8
mostsignificantbitsoftheRDADDaddressbus(aswellasthe2LSB’s).These queue increments. The PRn bus supports either Polled or Direct modes of
3MSb’scorrespondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1 operation. The PRnmode ofoperationis configuredthroughthe FlagMode
& ID2.
PleaserefertoFigure62,PAEn/PRn-DirectModeStatusWordSelection
(FM) bit during a Master Reset.
Whenthemulti-queueisconfiguredforpacketmodeoperation,the twomost
significantbitsofthe36-bitdatabusareusedas“packetmarkers”.Onthewrite
portthesearebitsD34(TransmitStartofPacket,)D35(TransmitEndofPacket)
andonthereadportQ34,Q35.Allfourbitsaremonitoredbythepacketcontrol
fortiminginformation.AlsorefertoTable5,ReadAddress Bus,RDADD.
PAEn – POLLED BUS
If FM is HIGH at master reset then the PAEn/PRn bus operates in Polled logicasdataiswrittenintoandreadoutfromthequeues.Thepacketreadystatus
(looped)mode.InpolledmodethePAEn/PRnbusautomaticallycyclesthrough forindividualqueues is thendeterminedbythepacketreadylogic.
the4statuswordswithinthedeviceregardlessofhowmanyqueueshavebeen
OnthewriteportD34is usedto“mark”thefirstwordbeingwrittenintothe
setupinthepart.EveryrisingedgeoftheRCLKcauses thenextstatus word selectedqueueasthe“TransmitStartofPacket”,TSOP.Tofurtherclarify,when
tobeloadedonthePAEn/PRnbus.Thedeviceconfiguredasthemaster(MAST theuserrequiresawordbeingwrittentobemarkedasthestartofapacket,the
inputtiedHIGH),willtakecontrolofthePAEn/PRnafterMRSgoesLOW.For TSOPinput(D34)mustbeHIGHforthesameWCLKrisingedgeastheword
the whole RCLKcycle thatthe firststatus wordis onPAEn/PRnthe ESYNC thatiswritten.TheTSOPmarkerisstoredinthequeuealongwiththedataitwas
(PAEn/PRnbussync)outputwillbeHIGH,forallotherstatuswords,thisESYNC written in until the word is read out of the queue via the read port.
outputwillbeLOW.ThisESYNCoutputprovidestheuserwithamarkwithwhich
OnthewriteportD35isusedto“mark”thelastwordofthepacketcurrently
theycan synchronize tothe PAEn/PRnbus, ESYNCis always HIGHforthe beingwrittenintotheselectedqueueasthe“TransmitEndofPacket”TEOP.
RCLKcyclethatthefirststatuswordofadeviceispresentonthePAEn/PRn Whentheuserrequiresawordbeingwrittentobemarkedastheendofapacket,
bus.
theTEOPinputmustbeHIGHforthesameWCLKrisingedgeasthewordthat
Whendevicesareconnectedinexpansionconfiguration,onlyonedevice iswrittenin.TheTEOPmarkerisstoredinthequeuealongwiththedataitwas
willbe setas the Master(ID='000'), MASTinputtiedHIGH, allotherdevices written in until the word is read out of the queue via the read port.
willhaveMASTtiedLOW.Themasterdeviceisthefirstdevicetotakecontrol
Thepacketreadylogicmonitorsallstartandendofpacketmarkersbothas
ofthePAEn/PRnbusandwillplaceitsfirststatuswordonthebusontherising theyenterrespectivequeuesviathewriteportandastheyexitqueuesviathe
edge of RCLK after the MRS input goes LOW. For the next n RCLK cycles readport.Themulti-queueinternallogicincrementsanddecrementsapacket
(n=numberofqueuesdividedby8withnincrementingbyoneshouldtherebe counter,whichisprovidedforeachqueue.Thefunctionalityofthepacketready
aremainder) themasterdevicewillmaintaincontrolofthePAEn/PRnbusand logicprovidesstatusastowhetheratleastonefullpacketofdataisavailable
cycleitsstatuswordsthroughit,allotherdevicesholdtheirPAEn/PRnoutputs withintheselectedqueue.Apartialpacketinaqueueisregardedasapacket
inHigh-Impedance.Whenthemasterdevicehascycledallofitsstatuswords notreadyandPR (activeLOW)willbeHIGH.InPacketmode,nowords can
itpassesatokentothenextdeviceinthechainandthatdeviceassumescontrol bereadfromaqueueuntilatleastonecompletepackethasbeenwritteninto
ofthePAEn/PRnbusandthencyclesitsstatuswordsandsoon,thePAEn/PRn thequeue,regardless ofREN.Forexample,ifaTSOPhas beenwrittenand
buscontroltokenbeingpassedonfromdevicetodevice.Thistokenpassing somenumberofwordslateraTEOPiswrittenafullpacketofdataisdeemed
isdoneviatheEXOoutputsandEXIinputsofthedevices(“PAEExpansionOut” tobeavailable,andthePRflagandORwillgoactiveLOW.Consequentlyifreads
and“PAEExpansionIn”).TheEXOoutputofthemasterdeviceconnectstothe beginfromaqueuethathasonlyonecompletepacketandtheRSOPisdetected
EXIoftheseconddeviceinthechainandtheEXOofthesecondconnectsto ontheoutputportasdataisbeingreadout,PRwillgoinactiveHIGH.ORwill
theEXIofthethirdandsoon.ThefinaldeviceinachainhasitsEXOconnected remainLOWindicatingthereisstillvaliddatabeingreadoutofthatqueueuntil
totheEXIofthefirstdevice,sothatoncethePAEn/PRnbushascycledthrough theREOPisread.Theusermayproceedwiththereadingoperationuntilthe
allstatuswordsofalldevices,controlofthePAEn/PRnwillpasstothemaster currentpackethasbeenreadoutandnofurthercompletepacketsareavailable.
device again and so on. The ESYNC of each respective device will operate Ifduringthattimeanothercompletepackethasbeenwrittenintothequeueand
AUGUST4,2005
47
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
thePRflagwillagaingoneactive,thenreadsfromthenewpacketmayfollow
afterthecurrentpackethasbeencompletelyreadout.
See Figure 55, Reading in Packet Mode during a Queue Change, Figure
57, Data Output (Receive) Packet Mode of Operation.
Thepacketcountersthereforelookforstartofpacketmarkersfollowedbyend
ofpacketmarkers andregarddatainbetweentheTSOPandTEOPas afull PACKETMODE–MODULOOPERATION
packetofdata.Thepacketmonitoringhasnolimitationastohowmanypackets
The internal packet ready control logic performs no operation on these
arewrittenintoaqueue,theonlyconstraintisthedepthofthequeue.Note,there modulobits,theyareonlyinformationalbitsthatarepassedthroughwiththe
isaminimumallowablepacketsizeoffourwords,inclusiveoftheTSOPmarker respectivedatabyte(s).
andTEOPmarker. Whenutilizingthemulti-queueflow-controldeviceinpacketmode,theuser
The packet logic does expect a TSOP marker to be followed by a TEOP mayalsowanttoconsidertheimplementationof“Modulo”operationor“valid
marker.
byte marking”. Modulo operation may be useful when the packets being
If a second TSOP marker is written after a first, it is ignored and the logic transferredthroughaqueueareinaspecificbytearrangementeventhough
regardsdatabetweenthefirstTSOPandthefirstsubsequentTEOPasthefull thedatabuswidthis36bits.InModulooperationtheusercanconcatenatebytes
packet.ThesameistrueforTEOP;asecondconsecutiveTEOPmarkisignored. toformaspecificdatastringthroughthemulti-queuedevice.Apossiblescenario
On the read side the user should regard a packet as being between the first is where a limited number of bytes are extracted from the packet for either
RSOP and the first subsequent REOP and disregard consecutive RSOP analysisorfilteredforsecurityprotection.Thiswillonlyoccurwhenthefirst36
markersand/orREOPmarkers.ThisiswhyaTEOPmaybewrittentwice,using bitwordofapacketiswritteninandthelast36bitwordofpacketiswrittenin.
the secondTEOPas the “filler”word.
Themodulooperationisameansbywhichtheusercanmarkandidentifyspecific
Asanexample,theusermayalsowishtoimplementtheuseofan“Almost datawithintheQueue.
EndofPacket”(AEOP)marker. Forexample, the AEOPcanbe assignedto
Onthewriteportdatainputbits,D32(transmitmodulobit2,TMOD2)andD33
datainputbitD33.ThepurposeofthisAEOPmarkeristoprovideanindicator (transmitmodulobit1,TMOD1)canbeusedasdatamarkers.Anexampleof
thatthe endofpacketis a fixed(known)numberofreads awayfromthe end thiscouldbetouseD32andD33tocodewhichbytesofawordarepartofthe
of packet. This is a useful feature when due to latencies within the system, packetthatis alsobeingmarkedas the “StartofMarker”or“EndofMarker”.
monitoringtheREOPmarkeralonedoesnotprevent“overreading”ofthedata Conversely on the read port when reading out these marked words, data
fromthequeueselected.Forexample,anAEOPmarkerset4writesbeforethe outputs Q32(receive modulobit2, RMOD2)andQ33(receive modulobit1,
TEOPmarkerprovidesthedeviceconnectedtothereadportwithand“almost RMOD1)willpassonthebytevalidityinformationforthatword.RefertoTable
endofpacket”indication4cyclesbeforetheendofpacket.
10foroneexampleofhowthemodulobitsmaybesetupandused.SeeFigure
The AEOP can be set any number of words before the end of packet 57, Data Output (Receive) Packet Mode of Operation.
determinedbyuserrequirementsorlatenciesinvolvedinthesystem.
TABLE 10 — PACKET MODE VALID BYTE FOR x36 BIT WORD CONFIGURATION
BYTE A
BYTE D
BYTE C
BYTE B
TMOD1 (D33)
RMOD1 (Q33)
TMOD2 (D32)
RMOD2 (Q32)
VALID BYTES
0
0
1
1
0
1
0
1
A, B, C, D
A
A, B
A, B, C
6716 drw19
AUGUST4,2005
48
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PACKETMODEDEMARCATIONBITS
Duringpacketmodebusmatching,whichistheabilitytosetthewriteinterface
TheIDT72P51339/72P51349/72P51359/72P51369canbeconfiguredfor andreadinterfacetoindependentwordlengths(i.e.9bitword,18bitword,36
packetmodeoperation.InpacketmodetheIDT72P51339/72P51349/72P51359/ bitword),thedemarcationbitsarelocatedwithintheirrespectivewordlength.
72P51369providesthefunctionalitytodemarcatepacketswithinaqueue.The Forexamplewithina36bitto36bitwordbusmatchingconfigurationbit35is
demarcation functionality is only available in packet mode and is used to designatedastheEndofPacket(EOP)andbit34isStartofPacket(SOP).In
generate the PacketReady(PR)flag.
an18bitto18bitwordbusmatchingconfigurationbit17isdesignatedEndof
Thedemarcationofpackets/informationisaccomplishedwiththedemarcation Packet(EOP)andbit16isStartofPacket.Theminimumpacketwordlength
bits[35:32].Thedemarcationbitassignmentsare;bit35EndofPacket(EOP), requiredbytheIDT72P51339/72P51349/72P51359/72P51369isfour(4)of
bit34StartofPacket(SOP),bit33AlmostEndofPacket(AEOP)andbit32Almost thelargestwordsspecifiedwithinabusmatchingconfiguration.RefertoFigure
StartofPacket(ASOP).
27-35fordesignatedlocations ofthedemarcationbits withinaspecificword
configuration.
35
0
6716 drw20
NOTES:
1. A Start of Packet (SOP) and End of Packet (EOP) may not occur within a same word.
2. The x36 bit words locate SOP and EOP as follows;
a. bit 35 is EOP
b. bit 34 is SOP.
Figure 27. 36bit to 36bit word configuration
8
0
A
34
32
33
35
<7:0>
B
17
0
(even word)
<15:8>
<23:16>
<31:24>
C
32, 34
17
<15:0>
0
D
(odd word)
35,33
<31:16>
6716 drw21
6716 drw22
NOTES:
1. In a 36 bit word to 9 bit word configuration the 36 bit word is converted into four (4)
9 bit words.
NOTES:
1. In a 36 bit word to 18 bit word configuration the 36 bit word is converted to two (2)
18 bit words.
2. An SOP and EOP may not occur within a same word.
2. An SOP and EOP may not occur within a same word.
3. The x9 bit words contain the demarcation bits as follows;
a. Bit 8 in Word “A” is the Start of Packet (SOP)
3. The x18 bit even words (0,2,4, etc.) contain demarcation bits 32 (ASOP) and 34
(SOP).
4. The x18 bit odd words (1,3,5, etc.) contain demarcation bits 33 (AEOP) and 35
(EOP).
b. Bit 8 in Word “B” is the Almost Start of Packet (ASOP).
c. Bit 8 in Word “C” is the Almost End of Packet (AEOP).
d. Bit 8 in Word “D” is the End of Packet (EOP).
Figure 28. 36bit to 18bit word configuration
Figure 29. 36bit to 9bit word configuration
AUGUST4,2005
49
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
35 34 33 32
0
6716 drw23
2nd <15:0>, 1st <15:0>
NOTES:
1. In a 18bit word to 36 bit word configuration two (2) eighteen bit words are concatenated to form one x36
bit word.
2. The x36 bit words contain demarcation bits as follows;
a. Bit 35 is End of Packet (EOP)
b. Bit 34 is Start of Packet (SOP).
c. Bit 33 Almost End of Packet (AEOP).
d. Bit 32 Almost Start of Packet (ASOP).
Figure 30. 18bit to 36bit word configuration
17 16
0
6716 drw24
NOTES:
1. An SOP and EOP may not occur within a same word.
2. The x18 bit words contain the demarcation bits as follows;
a. Bit 17 is the End of Packet (EOP).
b. Bit 16 is the Start of Packet (SOP).
3. In this configuration there is no ASOP or AEOP demarcation bits.
Figure 31. 18bit to 18bit word configuration
8
0
9
A
B
17
17
<7:0>
<15:8>
6716 drw24a
NOTES:
1. In a 18 bit word to 9 bit word configuration a single eighteen bit word is converted into two (2) nine bit words.
2. The x9 bit words contain demarcation bits as follows;
a. Bit 17 is End of Packet (EOP)
b. Bit 16 is Start of Packet (SOP).
3. An SOP and EOP may not occur within the same word.
4. In this configuration there is no ASOP or AEOP demarcation bits.
Figure 32. 18bit to 9bit word configuration
AUGUST4,2005
50
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
35 34 33 32
0
4th<7:0>, 3rd<7:0>, 2nd<7:0>, 1st<7:0>
6716 drw25
NOTES:
1. In a 9 bit word to 36 bit word configuration four (4), nine bit words are concatenated
to form one x36 bit word.
2. The x36 bit words contain demarcation bits as follows;
a. Bit 35 is End of Packet (EOP)
b. Bit 34 is Start of Packet (SOP).
c. Bit 33 Almost End of Packet (AEOP).
d. Bit 32 Almost Start of Packet (ASOP).
Figure 33. 9bit to 36bit word configuration
17 16
0
6716 drw26
NOTES:
1. In a 9 bit word to 18 bit word configuration two (2), nine bit words are concatenated
to form one x18 bit word.
2. The x18 bit words contain demarcation bits as follows;
a. Bit 17 is End of Packet (EOP)
b. Bit 16 is Start of Packet (SOP).
3. An SOP and EOP may not occur within the same word.
Figure 34. 9bit to 18bit word configuration
8
0
6716 drw27
NOTES:
1. An SOP and EOP may not occur within the same word.
2. Bit 8 of the x9 bit even words (0,2,4, etc.) is checked for a Start of Packet (SOP).
3. Bit 8 of the x9bit odd words (1,3,5, etc.) is checked for End of Packet (EOP).
4. The minimum packet word length is 4 words.
Figure 35. 9bit to 9bit word configuration
AUGUST4,2005
51
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
BUS MATCHING OPERATION
TABLE 11 — BUS-MATCHING SET-UP
BusMatchingoperationbetweentheinputportandoutputportisavailable.
Duringamasterresetofthemulti-queuethestateofthethreesetuppins,BM
[3:0](BusMatching),determinetheinputandoutputportbuswidthsasshown
inTable11,“BusMatchingSet-Up”.9bitwords,18bitwordsand36bitwords
canbewrittenintoandreadfromthequeues.Whenwritingtoorreadingfrom
the multi-queue in a bus matching mode, the device orders data in a “Little
Endian”format. See Figure 36, Bus MatchingByte Arrangementfordetails.
TheFullflagandAlmostFullflagoperationis always basedonwrites and
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput
portisx36andtheoutputportisx9,thenfourdatareadsfromafullqueuewill
berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the
EmptyflagandAlmostEmptyflagoperationsarealwaysbasedonwritesand
readsofdatawidthsdeterminedbythereadport.Forexample,iftheinputport
isx18andtheoutputportisx36,twowriteoperationswillberequiredtocause
the Empty flag (EF) of an empty queue to go HIGH (queue is not empty).
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput
port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe
outputportsize).
BM3
BM2
BM1
BM0
Write Port Read Port
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
1
0
0
1
1
x36
x36
x36
x18
x18
x18
x9
x36
x18
x9
x36
x18
x9
x36
x18
x9
x9
x9
AUGUST4,2005
52
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
Write to Queue
A
B
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
L
A
B
C
D
Read from Queue
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM
H
1st: Read from Queue
2nd: Read from Queue
C
D
Q26-Q18
Q17-Q9
Q8-Q0
A
B
(b) x36 INPUT to x18 OUTPUT
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM
H
D
1st: Read from Queue
2nd: Read from Queue
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q8-Q0
C
Q8-Q0
B
3rd: Read from Queue
4th: Read from Queue
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
(c) x36 INPUT to x9 OUTPUT
D35-D27
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to Queue
2nd: Write to Queue
B
D26-D18
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
H
D
B
C
A
Read from Queue
(d) x18 INPUT to x36 OUTPUT
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
D35-D27
D35-D27
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D8-D0
A
1st: Write to Queue
2nd: Write to Queue
D8-D0
B
D8-D0
C
3rd: Write to Queue
4th: Write to Queue
D8-D0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
H
D
C
B
A
Read from Queue
6716 drw28
(e) x9 INPUT to x36 OUTPUT
NOTE:
1. Please refer to Table 11, Bus-Matching set-up for details.
Figure 36. Bus-Matching Byte Arrangement
AUGUST4,2005
53
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
t
RSS
RSS
WEN
REN
t
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
t
RSS
RSS
RSS
ID0, ID1,
ID2
t
BM
FM
t
HIGH = Polled mode
LOW = Strobed (Direct)
tRSS
HIGH = Master Device
LOW = Slave Device
MAST
PKT
t
RSS
RSS
HIGH = Packet Ready Mode
t
HIGH = Queue Programming
LOW = Serial Programming
DFM
t
RSS
RSS
QSEL [1:0]
See Table 2, for setting the Queue Programming
t
HIGH = Offset Value is 128
LOW = Offset value is 8
DF
FF/IR
t
RSF
RSF
HIGH-Z if Slave Device
LOGIC "0" if Master Device
t
HIGH-Z if Slave Device
EF/OR
LOGIC "0" if Master Device
t
RSF
RSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAF
PAE
t
HIGH-Z if Slave Device
LOGIC "0" if Master Device
tRSF
tRSF
tRSF
tRSF
tRSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
PR
HIGH-Z if Slave Device
LOGIC "0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PRn
LOGIC "1" if OE is LOW and device is Master
Qn
HIGH-Z if OE is HIGH or Device is Slave
NOTE:
1. OE can toggle during this period.
6716 drw46
Figure 37. Master Reset
AUGUST4,2005
54
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
55
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
56
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tQH
tQS
WADEN
WEN
tENS
tENS
tAS
tAH
WRADD
Qx
tWFF
FF
tWAF
PAF
tPAF
Active Bus
PAF-Qx
6716 drw48
Figure 40. Queue Programming via Write Address Bus
RCLK
tENS
tENS
REN
tQS
tQH
RADEN
tAS
tAH
RDADD
Qx
tREF
OR
tRAE
PAE
tPAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
r+4
6716 drw49
Figure 41. Queue Programming via Read Address Bus
Master Reset
Default Mode
DFM = 0
MRS
MRS
MRS
DFM
DFM
DFM
MQ2
MQ1
MQn
SENI MasterSENO
Serial Loading
Complete
SENI
SENO
SO
SENI
SENO
SO
Serial Enable
ID=‘OOO’ SO
SI
SI
SI
Serial Input
SCLK
SCLK
SCLK
6716 drw50
Serial Clock
Figure 42. Serial Port Connection for Serial Programming
AUGUST4,2005
57
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
58
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
59
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
60
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
tDH
tDS
tDH
W3
W1
W2
Dn
tSKEW1
1
2
RCLK
REN
t
A
t
tA
Last Word Read Out of Queue
W1 Qy
W2 Qy
W3 Qy
Qout
REF
tREF
OR
6716 drw54
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 46. Write Operations in First Word Fall Through mode
AUGUST4,2005
61
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
62
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
63
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
64
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
65
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
*K*
RCLK
REN
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
Q30
Q15
tQS
tQH
tQH
tQS
Qout
Q30 WD Last Word
PQ
PQ
PQ
PQ
Q15
Q15
tREF
OR
WCLK
WEN
tENH
tENS
tAS
tAH
WRADD
Q15
tQS
tQH
WADEN
Din
tDS
tDH
Q15
6716 drw59
Cycle:
*A* Queue 30 is selected for read operations. It requires 4 clock cycles to switch queues.
*B* Reads are now enabled. A word from the previously selected queue will be read out.
*C* Another word from Present Queue (PQ) is read.
*D* Another word from PQ is read.
*E* Wd is read from Q30 of D1. This happens to be the last word of Q30, therefore OR goes HIGH to indicate that the data on the Qout is not valid (Q30 was read to empty).
Word, Wd remains on the output bus. Queue 15 is selected for read operations.
*F* The last word of Q30 remains on the Qout bus, OR is HIGH, indicating that this word has been previously read.
*G* The last word of queue 30 remains on the Qout bus.
*H* The last word of queue 30 remains on the Qout bus.
*I* The next word, available from the newly selected queue, Q15 is now read out. This will occur regardless of REN, due to FWFT mode.
*J* A word, is read from Q15.
*K* The OR flag stays LOW to indicate that Q15 has additional words available for reading.
Figure 51. Output Ready Flag Timing (In FWFT Mode)
AUGUST4,2005
66
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
67
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EO
AUGUST4,2005
68
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
69
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
70
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
71
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AUGUST4,2005
72
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
WCLK
WEN
2
1
tENH
tENS
tAS
tAH
tAS
tAH
WRADD
D1
Q5
D1 Q9
tQS
tQH
tQH
tQS
WADEN
Din
tDS
tDH
WD-m
D1 Q5
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
6716 drw66
Cycle:
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs, WEN is HIGH.
*C* No write occurs, WEN is HIGH.
*D* No write occurs, WEN is HIGH.
*E* Word, Wd-m is written into Q5 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + tWAF.
*F* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.
*G* The PAF flag goes LOW based on the write 2 cycles earlier.
*H* No write occurs, WEN is HIGH.
*I* The PAF flag goes HIGH due to the queue switch to Q9.
Figure 58. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
WEN
PAF
tENS
tENH
tWAF
tWAF
D - (m+1) words in Queue(2)
D-(m+1) words
in Queue
D - m words in Queue
tSKEW2
RCLK
tENS
tENH
6716 drw67
REN
NOTE:
1. The waveform shows the PAF flag operation when no queue switch occurs and a queue is selected on both the write and read ports is being written to then read
from at the almost full boundary.
2. Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
3. If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 59. Almost Full Flag Timing
AUGUST4,2005
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IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
REN
tAS
tAH
tAS
tAH
RDADD
D1
Q30
D1 Q15
tQS
tQH
tQH
tQS
RADEN
Qout
t
A
tA
t
A
tA
tOLZ
HIGH-Z
HIGH-Z
D1
Q30
Wn
D
1
Q30
Wn+1
D1
Q15
W0
D1 Q15 W1
tRAE
t
RAE
tAELZ
PAE
(Device 1)
tAEHZ
PAE
(Device 2)
HIGH-Z
6716 drw68
Cycle:
*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs, REN is HIGH.
*C* No read occurs, REN is HIGH.
*D* No read occurs, REN is HIGH
*E* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*F* Q15 of device 1 is selected.
*G* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*H* Word, W0 is read from Q15 due to the FWFT operation.
*I* The PAE flag goes HIGH to show that Q15 is not almost empty.
Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode)
tCLKL
tCLKH
WCLK
tENH
tENS
WEN
PAE
n+1 words in Queue
SKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
t
tRAE
RCLK
1
2
tENS
tENH
6716 drw69
REN
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
2. Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
3. If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 61. Almost Empty Flag Timing
AUGUST4,2005
74
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
RCLK
tQS
tQH
t
QS
tQS
Status Word 0
t
QH
tQH
Device 1
Device 1
Device 1
Status Word 2
Status Word 3
001xxx10
001xxx11
001xxx00
RDADD
ESTR
tSTS
tSTH
tSTS
tSTH
tPAE
tPAE
tPAE
PAEn/
PRn
Device 1 Status Word 2
ENH
Device 1 Status Word 3 Device 1 Status Word
0
tENS
tENH
tENS
t
RADEN
6716 drw70
NOTES:
1. Status words can be selected on consecutive cycles.
2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW.
3. There is a latency of 2 RCLK for the PAEn bus to switch.
Figure 62. PAEn/PRn - Direct Mode - Status Word Selection
WCLK
tQS
tQH
t
QS
tQS
Status Word 2
t
QH
tQH
Device 1
Device 1
Device 1
Status Word 1
Status Word 3
001xxx01
001xxx11
001xxx10
WRADD
FSTR
tSTS
tSTH
tSTS
tSTH
tPAF
tPAF
tPAF
PAFn
Device 1 Status Word 1
ENH
Device 1 Status Word 3
Device 1 Status Word
2
tENS
tENH
tENS
t
WADEN
6716 drw71
NOTES:
1. Status words can be selected on consecutive cycles.
2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW.
3. There is a latency of 2 WCLK for the PAFn bus to switch.
Figure 63. PAFn - Direct Mode - Status Word Selection
AUGUST4,2005
75
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
1
*C*
2
*D*
3
*E*
*F*
*G*
*H*
WCLK
WADEN
FSTR
tQS
tQH
tQS
tQH
tSTS
tSTH
tENS
tENH
WEN
tAS
tAH
tAH
tAS
tAS
tAH
D4 SW 2
D3Q8
011 01000
WRADD
Dn
D5Q24
101 11000
tDH
100 00100
t
DH
tDH
t
DS
t
DS
tDS
Wp+3
Wp
Wp+1
Wp+2
Wn
D5Q24
Writes to Previous Q
tSKEW3
RCLK
RADEN
ESTR
tQS
tQH
tSTS
t
STH
t
ENS
tENH
REN
tAH
tAS
tAS
tAH
RDADD
D5 SW 3
D5Q24
101 11000
101 00011
tA
t
A
tA
t
A
tA
Wy+1
D5 Q24
Wy
D5 Q24
Wy+2
D5 Q24
Wy+3
D5 Q24
Device 5 -Qn
Wa
D5 Q17
Wa+1
D5 Q17
Previous value loaded on to PAE bus
Prev PAEn
tPAEHZ
tPAE
tPAEZL
xxxx xxx0
D5 SW 3
xxxx xxx1
D5 SW 3
Device 5 PAEn
xxxx xxx0
D5 SW 3
xxxx xxx1
D5 SW 3
Previous value loaded on to PAE bus
D5 Q17 Status
Bus PAEn
t
RAE
tRAE
tRAE
D5 Q24
status
Device 5 PAE
6716 drw72
*FF*
*AA*
*BB*
*CC*
*DD*
*GG*
*EE*
Cycle:
*A* Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 24 of Device 5 is selected for read operations.
A status word from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Current Word is kept on the output bus since REN is HIGH.
*C* Word Wp+2 is written into the previously selected queue.
*CC* Word Wa+1 of D5 Q17 is read due to FWFT.
*D* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).
*DD* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.
Status word 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before
the PAEn bus changes to the new selection.
*E* Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
*EE* Word, Wy+1 is read from Q24 of D5.
*F* No writes occur.
*FF* Word, Wy+2 is read from Q24 of D5.
The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and status word 4 is placed onto the outputs. The device of the previously selected
status word now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].
*G* Status word 3 of device 4 is selected on the write port for the PAFn bus.
*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
Figure 64. PAEn - Direct Mode, Flag Operation
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
tQH
tQS
tQS
tQH
RADEN
tSTH
tSTS
ESTR
REN
tAS
tAH
tAH
tAH
tAS
tAS
D7 SW 0
RDADD
D6Q2
D0Q31
110 00010
111 00000
000 11111
OE
t
A
tA
tA
tA
tOLZ
Qout
WX
WX +1
WD - M + 2
W0
WD-M+1
D0 Q31
D0 Q31
D6 Q2
tSKEW3
WCLK
FSTR
1
2
3
tSTS
tSTH
tAS
tAH
tAS
tAH
WRADD
D0 quad3
000 00011
D0 Q31
tENS
tENH
WEN
tQS
tQH
WADEN
Din
t
DS
t
DH
tDS
t
DH
tDS
tDH
W
y+1
Wy+2
Word W
y
D0 Q31
D0 Q31
D0 Q31
tPAFLZ
tPAF
tPAF
Device 0 PAFn
0xxx xxxx
0xxx xxxx
1xxx xxxx
1xxx xxxx
0xxx xxxx
0xxx xxxx
D0SW3
D0SW3
D0SW3
D0SW3
D0SW3
HIGH-Z
DXSW y
D0SW3
Bus PAFn
tPAFHZ
HIGH-Z
DXSW y
Prev.
PAFn
tPAFLZ
tWAF
Device 0
HIGH - Z
6716 drw73
PAF
*AA*
*BB*
*CC*
*DD*
*EE*
*FF*
*GG*
Cycle:
*A* Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Status word 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected status word, Quad Y of device X.
*B* No read operation.
*BB* Queue 31 of device 0 is selected on the write port.
*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*CC* PAFn continues to show status of Quad4 D0.
The PAFn bus is updated with the status word selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*D* A new status word, Quad 0 of Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*DD* No write operation.
*E* No read operations occur, REN is HIGH.
*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
*F* Queue 2 of Device 6 is selected for read operations.
*FF* Word, Wy+1 is written into D0 Q31.
*G* Word, Wd-m+2 is read out due to FWFT operation.
*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q31.
*H* No read operation.
*I* Word, W0 is read from Q0 of D6, selected on cycle *F*, due to FWFT.
Figure 65. PAFn - Direct Mode, Flag Operation
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
APF
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Read Clock
Data Bus
Q
-Q
35
D
-D
35
0
0
Write Clock
Write Enable
RCLK
REN
RCS
WCLK
WEN
WCS
Read Enable
Read Queue Select
Read Address
Write Queue Select
Write Address
RDADD
RADEN
WRADD
WADEN
DEVICE
1
Empty Strobe
Full Strobe
ESTR
FSTR
PAFn
Programmable Almost Full
Programmable Almost Empty
PAEn
Empty Sync 1
Empty/Output Ready Flag
Almost Empty Flag
Full Sync1
ESYNC
FSYNC
Full Flag
EF
FF
Almost Full Flag
Serial Clock
PAF
PAE
PR
Packet Reads
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q
-Q
35
D
-D
35
0
0
RCLK
REN
RCS
WCLK
WEN
WCS
WRADD
WADEN
RDADD
RADEN
DEVICE
2
FSTR
PAFn
ESTR
PAEn
Empty Sync 2
Full Sync2
FSYNC
ESYNC
FF
EF
PAF
PAE
SCLK
PR
SO FXO EXO
SENO
SENI SI FXI EXI
Q
-Q
35
D
-D
35
0
0
WCLK
WEN
WCS
RCLK
REN
RCS
WRADD
WADEN
RDADD
RADEN
DEVICE
n
(Master, ID = ‘000')
FSTR
PAFn
ESTR
PAEn
Full Sync n
Empty Sync n
FSYNC
ESYNC
FF
EF
PAF
PAE
PR
SCLK
SENO
FXO EXO
DONE
6716 drw75
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 67. Expansion using ID codes
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Data Bus
Q -Q
D -D
0
35
0
35
Write Clock
Read Clock
WCLK
RCLK
REN
RCS
Write Enable
Read Enable
WEN
WCS
RCS1
WCS1
SLAVE
DEVICE
1
Read Queue Select
Read Address
Write Queue Select
Write Address
RDADD
RADEN
WRADD
WADEN
Empty Strobe
Full Strobe
ESTR
FSTR
PAFn
Programmable Almost Full
Programmable Almost Empty
PAEn
Empty Sync 1
Empty/Output Ready Flag
Almost Empty Flag
Full Sync1
ESYNC
FSYNC
Full Flag
EF
FF
ID = 001
Almost Full Flag
Serial Clock
PAF
PAE
PR
Packet Reads
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q -Q
D -D
0
35
0
35
WCLK
RCLK
REN
RCS
SLAVE
DEVICE
2
WEN
WCS2
RCS2
WCS
WRADD
RDADD
RADEN
WADEN
FSTR
PAFn
ESTR
PAEn
ESYNC
Empty Sync 2
Full Sync2
FSYNC
ID = 010
FF
EF
PAF
PAE
SCLK
PR
SO FXO EXO
SENO
SENI SI FXI EXI
Q -Q
D -D
0
35
0
35
WCLK
RCLK
MASTER
DEVICE
0
REN
RCS
RDADD
WEN
WCS
WRADD
WADEN
WCS0
RCS0
RADEN
FSTR
PAFn
FSYNC
ESTR
PAEn
Full Sync n
Empty Sync n
ESYNC
ID = 000
FF
EF
PAF
PAE
PR
SCLK
SENO
FXO EXO
DONE
6716 drw75a
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 68. Expansion using WCS/RCS
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IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
A
B
C
D
E
F
G
H
I
J
RCLK
tENH
tENS
tENH
tENS
REN
tENS
tENH
tENS
RCS1
Q1_A
Q1_B
Q1_C
Q1_D
Q1_E
Qout1
RCS2
Qout2
tENS
t
ENH
tENS
t
ENH
Q2_A
Q2_B
t
t
ENS
ENS
tENH
tENH
RCS3
Qout3
Q3_C
Q1_A
Q1_B
Q1_C
Q2_A
Q1_D
Q2_B
Q3_C
Q1_E
Q_Bus
6716 drwA
NOTE:
1. RCS signals are mutually exclusive, (i.e.. only one RCS signal can be asserted (low) at a time).
Figure 69. Expansion Connection Read Chip Select (RCS)
A
B
C
D
E
F
G
H
I
J
WCLK
tENS
WEN
tENS
tENS
tENH
tENH
tENH
tENS
WCS1
t
ENS ENH
t
tENS
tENH
WCS2
WCS3
tENS
tENH
tENS
tENH
tDS
tDH
Din
Device 1
Device 2
Device 1
No write
Device 1 No write Device 2 Device 3
Device 1
6716 drwB
Figure 70. Expansion Connection Write Chip Select (WCS)
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72P51339/72P51349/
72P51359/72P51369incorporatesthenecessarytapcontrollerandmodified
padcellstoimplementtheJTAGfacility.
Thefollowingsections provideabriefdescriptionofeachelement.Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
6716 drw76
Figure 71. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor.Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
Exit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
6716 drw77
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 72. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IR This state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-Scan This is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
JTAG INSTRUCTION REGISTER
THE INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth.Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current.Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata.Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions.Instructionsaredecodedasfollows.
TESTDATAREGISTER
Hex
Value
00
01
02
03
0F
Instruction
Function
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsections provideabriefdescriptionofeachelement.Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
JTAG
SelectBypassRegister
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO.Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
Thefollowingsectionsprovideabriefdescriptionofeachinstruction.For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports.TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
THE DEVICE IDENTIFICATION REGISTER
IDCODE
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDTJEDECIDnumberis0xB3.Thistranslatesto0x33whentheparityis
droppedinthe11-bitManufacturerIDfield.
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containinginformationregardingtheICmanufacturer,devicetype,andversion
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise
movingtotheTest-Logic-Resetstate.
FortheIDT72P51339/72P51349/72P51359/72P51369,thePartNumber
fieldcontainsthefollowingvalues:
Device
Part# Field (HEX)
0474
IDT72P51339
IDT72P51349
IDT72P51359
IDT72P51369
0475
0476
0477.
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSb)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
6716 drw78
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 73. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(VDD = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
IDT72P51339
IDT72P51349
IDT72P51359
IDT72P51369
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
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86
ORDERINGINFORMATION
IDT XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type Power Speed
Package
G
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Green
G
Plastic Ball Grid Array (PBGA, BB256-1)
BB
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
5
6
Commercial Only
Commercial and Industrial
Low Power
L
72P51339 589,824 bits 1.8V Multi-Queue Flow-Control Device
72P51349 1,179,648 bits 1.8V Multi-Queue Flow-Control Device
72P51359 2,359,296 bits 1.8V Multi-Queue Flow-Control Device
72P51369 4,718,592 bits 1.8V Multi-Queue Flow-Control Device
6716 drw79
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Green parts are available. For specific speeds contact your sales office.
DATASHEETDOCUMENTHISTORY
02/04/2005
08/01/2005
pg. 11.
pgs. 1, 3, 7, 9, 11, 13, 15, 17, 18, 20, 21, 25-28, 30-32, 45, 54-56, 58-66, 73, 74, 78, 80 and 87.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
87
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