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72T36135ML5BB [IDT]

PBGA-240, Tray;
72T36135ML5BB
型号： 72T36135ML5BB
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

PBGA-240, Tray

时钟 先进先出芯片 内存集成电路
文件： 总49页 (文件大小：508K)
中文：  中文翻译
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2.5V 18M-BIT HIGH-SPEED TeraSyncTM  
FIFO36-BITCONFIGURATIONS  
524,288 x 36  
IDT72T36135M  
• Separate SCLK input for Serial programming of flag offsets  
• Auto power down minimizes standby power consumption  
• Master Reset clears entire FIFO  
• Partial Reset clears data, but retains programmable settings  
• Empty and Full flags signal FIFO status  
• Select IDT Standard timing (using EF[1:2] and FF[1:2] flags) or First  
Word Fall Through timing (using OR[1:2] and IR[1:2] flags)  
• Output enable puts data outputs into high impedance state  
• JTAG port, provided for Boundary Scan function  
• Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)  
50% more space saving than the leading 9M-bit FIFOs  
• Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
FEATURES:  
• Industry’s largest FIFO memory organization:  
IDT72T36135  
• Up to 200 MHz Operation of Clocks  
• Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync  
devices  
⎯
524,288 x 36 - 18M-bits  
• User selectable HSTL/LVTTL Input and/or Output  
• User selectable Asynchronous read and/or write port timing  
• Mark & Retransmit, resets read pointer to user marked position  
• Write Chip Select (WCS) input disables Write Port  
• Read Chip Select (RCS) synchronous to RCLK  
• Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
• Program programmable flags by either serial or parallel means  
• Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
• High-performance submicron CMOS technology  
• Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
FUNCTIONALBLOCKDIAGRAM  
D0 -Dn (x36)  
LD SEN  
SCLK  
WEN  
WCLK/WR  
WCS  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR[1:2]  
PAF[1:2]  
EF/OR[1:2]  
PAE[1:2]  
WRITE CONTROL  
LOGIC  
ASYW  
FLAG  
LOGIC  
FWFT/SI  
PFM  
WRITE POINTER  
RAM ARRAY  
524,288 x 36  
FSEL0  
FSEL1  
MRS  
PRS  
READ POINTER  
RESET  
LOGIC  
TCK  
TRST  
TMS  
TDO  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
RT  
MARK  
READ  
CONTROL  
LOGIC  
OUTPUT REGISTER  
ASYR  
TDI  
Vref  
WHSTL  
RHSTL  
SHSTL  
HSTL I/0  
CONTROL  
RCLK/RD  
REN  
RCS  
6723 drw01  
OE  
Q0 -Qn (x36)  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.  
FEBRUARY 2009  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6723/4  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PINCONFIGURATION  
A1 BALL PAD CORNER  
A
B
C
D
E
F
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ VDDQ  
VCC  
VCC  
VCC  
VCC  
WCLK  
WEN  
WCS  
GND  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
ASYR  
FF1  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
RCLK  
PRS  
MRS  
LD  
FF2  
EF1  
OE  
VCC  
VCC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
PAF1  
REN  
MARK  
EF2  
RCS  
RT  
VCC  
PAF2 PAE1  
VDDQ  
PFM  
GND  
FSEL0 SHSTL FSEL1 GND  
GND  
RHSTL  
VCC FWFT/SI  
PAE2  
DNC  
VCC  
VCC  
GND  
GND  
GND  
GND  
G
H
J
SCLK  
VCC  
VCC  
VCC  
D35  
D32  
D29  
D26  
VCC  
VCC  
VCC  
VCC  
D33  
D30  
D27  
D24  
WHSTL  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
SEN  
VCC  
VCC  
GND  
GND  
VDDQ VDDQ  
VDDQ VDDQ  
ASYW  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VREF  
K
L
GND  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
Q33  
VDDQ  
Q35  
Q32  
Q29  
Q26  
VCC  
D34  
D31  
D28  
D25  
DNC  
GND  
GND  
GND  
GND  
VDDQ  
Q34  
Q31  
Q28  
Q25  
M
N
P
R
T
Q30  
Q27  
D21  
D19  
D18  
D22  
D20  
D17  
D23  
D13  
GND  
D10  
D11  
GND  
D5  
GND  
D4  
GND  
D1  
GND  
TMS  
GND  
TDO  
TDI  
GND  
GND  
GND  
GND  
Q0  
GND  
Q2  
GND  
Q3  
GND  
Q8  
GND  
Q11  
Q12  
Q24  
Q14  
Q15  
Q23  
Q21  
Q18  
Q22  
Q20  
U
V
Q6  
Q5  
Q9  
D14  
D7  
D8  
D2  
TRST  
Q1  
Q19  
VCC  
D16  
D15  
Q7  
Q10  
Q13  
Q17  
D0  
DNC  
Q4  
VDDQ  
D12  
D9  
D6  
D3  
Q16  
TCK  
GND  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
6723 drw02  
NOTE:  
1. DNC - Do Not Connect.  
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)  
TOP VIEW  
FEBRUARY04,2009  
2
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO  
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs  
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding  
data inputs of the next). No external logic is required.  
DESCRIPTION:  
The IDT72T36135M is an exceptionally deep, extrememly high speed,  
CMOSFirst-In-First-Out(FIFO)memoriywithclockedreadandwritecontrols  
and a wide extended x36 bus to allow ample data flow. These FIFOs offer  
severalkeyuserbenefits:  
The 18M-bitTeraSyncFIFO has 8flagpins, EF/OR[1:2] (EmptyFlagor  
Output Ready), FF/IR[1:2] (Full Flag or Input Ready), PAE[1:2] (Program-  
mableAlmost-Emptyflag)andPAF[1:2](ProgrammableAlmost-Fullflag). The  
EF[1:2]andFF[1:2]functionsareselectedinIDTStandardmode. TheIR[1:2]  
andOR[1:2]functionsareselectedinFWFTmode.PAE[1:2]andPAF[1:2]are  
alwaysavailableforuse,irrespectiveoftimingmode. Each flaghasadouble  
becausethe18MFIFOwas designedas aMulti-chipModule,soeachsetof  
flagssupportsitsrespectiveinternal9MFIFO. Someextraexternalgatinglogic  
willhavetobeusedtoaccuratelyreadeachflagoutput. Thiswillbecovered  
intheflaggingsectionofthedatasheet.  
PAE[1:2]andPAF[1:2]canbeprogrammedindependentlytoswitchatany  
pointinmemory. Programmableoffsetsdeterminetheflagswitchingthreshold  
andcanbeloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettings  
arealsoprovided,sothatPAE[1:2]canbesettoswitchatapredefinednumber  
oflocationsfromtheemptyboundaryandthePAF[1:2]thresholdcanalsobe  
setatsimilarpredefinedvaluesfromthefullboundary. Thedefaultoffsetvalues  
are setduringMasterResetbythe state ofthe FSEL0, FSEL1, andLD pins.  
For serial programming, SEN together with LD on each rising edge of  
SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel  
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused  
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge  
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether  
serialorparalleloffsetloadinghasbeenselected.  
•
•
•
•
•
•
Highdensityofferingof18Mbit  
200MHzR/WClockssupporting7.2Gbpsofdatathroughput  
UserselectableMARKlocationforretransmit  
User selectable I/O structure for HSTL or LVTTL  
Asynchronous/Synchronoustranslationonthereadorwriteports  
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswritten  
to an empty FIFO to the time it can be read, is fixed and short.  
TeraSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-  
munications,datacommunicationsandotherapplicationsthatneedtobuffer  
largeamounts ofdataatveryhighperformance.  
Theinput portcanbeselectedaseitheraSynchronous(clocked)interface,  
or Asynchronous interface. During Synchronous operation the input port is  
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data  
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof  
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR  
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,  
theWENinputshouldbetiedtoitsactivestate,(LOW).  
The inputportcanbe selectedforeither2.5VLVTTLorHSTLoperation,  
thisoperationisselectedbythestateoftheWHSTLinputduringamasterreset.  
AWrite ChipSelectinput(WCS)is providedforuse whenthe write portis in  
bothLVTTLandHSTLmodes.DuringoperationtheWCS inputcanbeused  
todisablewriteportinputs (dataonly).  
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,  
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis  
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data  
is read from the FIFO on every rising edge of RCLK when REN is asserted.  
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe  
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits  
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport  
theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe  
tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.  
Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation,  
thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.  
AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.  
AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized  
tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.  
When RCS is disabled, the data outputs will be high impedance. During  
Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.  
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0  
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency  
oftheoneclockinputwithrespecttotheother.  
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite  
pointers are set to the first location of the FIFO. The FWFT pin selects IDT  
Standardmode orFWFTmode.  
The Partial Reset (PRS) also sets the read and write pointers to the first  
location of the memory. However, the timing mode, programmable flag  
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore  
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming  
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,  
whenreprogrammingprogrammableflagswouldbeundesirable.  
Itisalsopossibletoselectthetimingmode of thePAE[1:2](Programmable  
Almost-Emptyflag)andPAF[1:2](ProgrammableAlmost-Fullflag)outputs.The  
timing modes can be set to be either asynchronous or synchronous for the  
PAE[1:2]andPAF[1:2]flags.  
IfasynchronousPAE/PAF[1:2]configurationisselected, thePAE[1:2]is  
assertedLOWontheLOW-to-HIGHtransitionofRCLK.PAE[1:2]isresetto  
HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF[1:2] is  
assertedLOWontheLOW-to-HIGHtransitionofWCLKandPAF[1:2]isreset  
toHIGHontheLOW-to-HIGHtransitionofRCLK.  
If synchronous PAE/PAF[1:2] configuration is selected , the PAE[1:2] is  
assertedandupdatedontherisingedgeofRCLKonlyandnotWCLK.Similarly,  
PAF[1:2] is asserted and updated on the rising edge of WCLK only and not  
RCLK.ThemodedesiredisconfiguredduringMasterResetbythestateofthe  
Programmable Flag Mode (PFM) pin.  
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol  
inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect  
totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any  
subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto  
this‘marked’location.  
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT  
Standard mode and First Word Fall Through (FWFT) mode.  
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear  
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread  
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,  
willshiftthewordfrominternalmemorytothedataoutputlines.  
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly  
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes  
not have to be asserted for accessing the first word. However, subsequent  
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof  
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.  
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill  
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply  
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol  
FEBRUARY04,2009  
3
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
DESCRIPTION (CONTINUED)  
accountforJTAGtestingsincethedeviceisaMCM.PleaseseeJTAGsection  
forfurtherdetails.  
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.  
Both an Asynchronous Output Enable pin (OE) and Synchronous Read  
ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip  
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect  
control the output buffer of the FIFO, causing the buffer to be either HIGH  
impedanceorLOWimpedance.  
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary  
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and  
Boundary Scan Architecture. Special consideration should be taken into  
TheTeraSyncFIFOhas thecapabilityofoperatingits ports (writeand/or  
read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe  
other.ThewriteportselectionismadeviaWHSTLandthereadportselection  
viaRHSTL.AnadditionalinputHSTLisalsoprovided,thisallowstheuserto  
selectHSTLoperationforotherpinsonthedevice(notassociatedwiththewrite  
or read ports).  
TheIDT72T36135MisfabricatedusingIDT’shighspeedsubmicronCMOS  
technology.  
FEBRUARY04,2009  
4
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PARTIAL RESET (PRS) MASTER RESET (MRS)  
WRITE CLOCK (WCLK/WR)  
READ CLOCK (RCLK/RD)  
WRITE ENABLE (WEN)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE)  
WRITE CHIP SELECT (WCS)  
LOAD (LD)  
READ CHIP SELECT (RCS)  
(x36) DATA IN (D  
0
- D  
n)  
(x36) DATA OUT (Q0 - Qn)  
IDT  
72T36135M  
RCLK  
SERIAL CLOCK (SCLK)  
REN  
SERIAL ENABLE(SEN)  
MARK  
FIRST WORD FALL THROUGH/  
SERIAL INPUT (FWFT/SI)  
RETRANSMIT (RT)  
EMPTY FLAG/OUTPUT READY (EF/OR[1:2])  
PROGRAMMABLE ALMOST-EMPTY (PAE[1:2])  
FULL FLAG/INPUT READY (FF/IR[1:2])  
PROGRAMMABLE ALMOST-FULL (PAF[1:2])  
6723 drw03  
Figure 1. Single Device Configuration Signal Flow Diagram  
FEBRUARY04,2009  
5
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PINDESCRIPTION  
Symbol  
Name  
I/OTYPE  
Description  
(1)  
ASYR Asynchronous  
LVTTL  
INPUT  
AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW  
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.  
ReadPort  
(1)  
ASYW Asynchronous  
LVTTL  
INPUT  
AHIGHonthisinputduringMasterResetwillselectSynchronouswriteoperationfortheinputport.ALOW  
willselectAsynchronousoperation.  
WritePort  
D0–D35 DataInputs  
HSTL-LVTTL Datainputs fora36-bitbus.  
INPUT  
EF/OR Empty Flag/  
HSTL-LVTTL IntheIDTStandardmode,theEF[1:2]functionisselected.EF[1:2]indicateswhetherornottheFIFOmemory  
OUTPUT isempty.InFWFTmode,theOR[1:2]functionisselected.OR[1:2]indicateswhetherornotthereisvaliddata  
available atthe outputs. Please see Flaggingsectionforexternalgatinginstructions ofthese flags.  
[1:2]  
OutputReady  
FF/IR  
[1:2]  
Full Flag/  
Input Ready  
HSTL-LVTTL IntheIDTStandardmode,theFF[1:2]functionisselected.FF[1:2]indicateswhetherornottheFIFOmemory  
OUTPUT isfull.IntheFWFTmode,theIR[1:2]functionisselected. IR[1:2]indicateswhetherornotthereisspaceavailable  
for writing to the FIFO memory. Please see Flagging section for external gating instructions of  
these flags.  
FSEL0(1) FlagSelectBit0  
FSEL1(1) FlagSelectBit1  
FWFT/ FirstWordFall  
LVTTL  
INPUT  
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe  
programmableflagsPAE[1:2]andPAF[1:2].Thereareuptoeightpossiblesettingsavailable.  
LVTTL  
INPUT  
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe  
programmableflagsPAE[1:2]andPAF[1:2].Thereareuptoeightpossiblesettingsavailable.  
HSTL-LVTTL DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,this pin  
SI  
Through/Serial In  
INPUT  
functionsasaserialinputforloadingoffsetregisters.IfAsynchronousoperationofthereadporthasbeen  
selectedthentheFIFOmustbeset-upinIDTStandardmode.  
LD  
Load  
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,  
INPUT  
determinesoneofeightdefaultoffsetvaluesforthePAE[1:2]andPAF[1:2]flags,alongwiththemethodbywhich  
theseoffsetregisterscanbeprogrammed,parallelorserial(seeTable1).AfterMasterReset,thispinenables  
writingtoandreadingfromtheoffsetregisters.  
MARK MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit  
INPUT operationwillresetthereadpointertothisposition.  
HSTL-LVTTL MRSinitializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes.DuringMaster  
MRS  
MasterReset  
INPUT  
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Synchronous/Asynchronousoperation  
ofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,serialorparallelprogrammingof  
theoffsetsettings,zerolatencytimingmode,andsynchronousversusasynchronousprogrammableflag  
timingmodes.  
OE  
OutputEnable  
HSTL-LVTTL OEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn.DuringaMasterorPartialResetthe  
INPUT OEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.  
PAE  
[1:2]  
Programmable  
Almost-EmptyFlag  
HSTL-LVTTL PAE[1:2] goes LOWifthenumberofwords intheFIFOmemoryis less thanoffsetn,whichis storedinthe  
OUTPUT EmptyOffsetregister. PAE[1:2] goes HIGHifthenumberofwords intheFIFOmemoryis greaterthanor  
equal to offset n. Please see Flagging section for external gating instructions of these flags.  
PAF  
[1:2]  
Programmable  
Almost-FullFlag  
HSTL-LVTTL PAF[1:2]goesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstored  
OUTPUT intheFullOffsetregister.PAF[1:2]goesLOWifthenumberoffreelocationsintheFIFOmemoryislessthan  
or equal to m. Please see Flagging section for external gating instructions of these flags.  
(1)  
PFM  
Programmable  
Flag Mode  
LVTTL DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon  
INPUT  
PFMwillselectSynchronousProgrammableflagtimingmode.  
PRS  
PartialReset  
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,  
INPUT  
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings  
are allretained.  
Q0–Q35 DataOutputs  
RCLK/ ReadClock/  
HSTL-LVTTL Dataoutputsforan36-bitbus.  
OUTPUT  
HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,whenenabledbyREN,therisingedgeofRCLK  
RD  
ReadStobe  
INPUT  
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevalues  
loadedintotheoffsetregistersisoutputonarisingedgeofRCLK.IfAsynchronousoperationoftheread  
FEBRUARY04,2009  
6
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PINDESCRIPTION(CONTINUED)  
Symbol  
Name  
I/OTYPE  
HSTL-LVTTL port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.  
INPUT RENshouldbetiedLOW.  
ReadChipSelect HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During  
Description  
RCLK/ ReadClock/  
RD  
ReadStrobe  
RCS  
INPUT  
aMasterResetorPartialResettheRCSinputis don’tcare,ifOE is LOWthedataoutputs willbe  
Low-ImpedanceregardlessofRCS.  
REN  
ReadEnable  
HSTL-LVTTL IfSynchronous operationofthereadporthas beenselected,RENenablesRCLKforreadingdatafromthe  
INPUT  
FIFOmemoryandoffsetregisters.IfAsynchronousoperationofthereadporthasbeenselected,theREN  
inputshouldbetiedLOW.  
(1)  
RHSTL Read Port HSTL  
Select  
LVTTL  
INPUT  
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL inputs are required, this input  
mustbetiedHIGH.OtherwiseitshouldbetiedLOW.  
RT  
Retransmit  
HSTL-LVTTL RT assertedontherisingedgeofRCLKinitializes theREADpointertozero,sets theEF[1:2]flagtoLOW  
INPUT  
(OR[1:2]toHIGHinFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtiming  
modeorprogrammableflagsettings.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwill  
jumptothe‘mark’location.  
SCLK  
SerialClock  
SerialEnable  
HSTL-LVTTL ArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovidingthat  
INPUT SEN is enabled.  
SEN  
HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets.  
INPUT  
SHSTL SystemHSTL  
LVTTL  
INPUT  
AllinputsnotassociatedwiththewriteorreadportcanbeselectedforHSTLoperationviatheSHSTLinput.  
Select  
(2)  
TCK  
TRST  
TMS  
TDI  
JTAGClock  
JTAGReset  
HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on  
INPUT TDOonthe fallingedge.  
(2)  
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller.  
INPUT  
JTAGMode  
Select  
HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of  
INPUT  
HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.  
INPUT ThisisalsothedatafortheInstructionRegister,IDRegisterandBypassRegister.  
operationforthe JTAGboundaryscan.  
TestDataInput  
TDO  
WEN  
TestDataOutput HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.  
OUTPUT This outputis inHigh-Zexceptwhenshifting, while inSHIFT-DRandSHIFT-IRcontrollerstates.  
WriteEnable  
HSTL-LVTTL WhenSynchronousoperationofthewriteporthasbeenselected,WENenablesWCLKforwritingdatainto  
INPUT  
theFIFOmemoryandoffsetregisters.IfAsynchronousoperationofthewriteporthasbeenselected,the  
WENinputshouldbetiedLOW.  
WCS  
WriteChipSelect HSTL-LVTTL This pindisables the write portdata inputs whenthe device write portis configuredforHSTLmode. This  
INPUT provides added power savings.  
WCLK/ WriteClock/  
WR WriteStrobe  
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of  
INPUT  
WCLKwritesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwrites  
data into the FIFO on a rising edge in an Asynchronous manner, (WEN shouldbe tiedtoits active state).  
(1)  
WHSTL WritePortHSTL  
Select  
LVTTL  
INPUT  
ThispinisusedtoselectHSTLor2.5VLVTTLinputsfortheFIFO.IfHSTLinputsarerequired,thisinputmust  
betiedHIGH.OtherwiseitshouldbetiedLOW.  
Vcc  
+2.5v Supply  
GroundPin  
Power  
GND  
I
These are Vccsupplyinputs andmustbe connectedtothe 2.5Vsupplyrail.  
These are Ground pins an dmust be connected to the GND rail.  
GND  
Vref  
Reference  
Voltage  
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable,  
“RecommendedDCOperatingConditions”.This provides thereferencevoltagewhenusingHSTLclass  
inputs.IfHSTLclass inputs arenotbeingused,this pinshouldbetiedLOW.  
VDDQ  
O/PRailVoltage  
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.  
NOTES:  
1. Inputs should not change state after Master Reset.  
2. If the JTAG feature is not being used, TCK and TRST should be tied LOW.  
FEBRUARY04,2009  
7
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
ABSOLUTEMAXIMUMRATINGS  
CAPACITANCE(TA = +25°C, f = 1.0MHz)  
Parameter(1)  
Conditions  
Max.  
Unit  
Symbol  
Rating  
Commercial  
Unit  
Symbol  
VTERM  
TerminalVoltage  
with respect to GND  
–0.5to+3.6(2)  
V
(2,3)  
CIN  
Input  
Capacitance  
VIN = 0V  
15(3)  
pF  
(1,2)  
TSTG  
IOUT  
StorageTemperature  
DCOutputCurrent  
–55 to +125  
–50 to +50  
°C  
mA  
COUT  
Output  
Capacitance  
VOUT = 0V  
10.5  
pF  
NOTES:  
NOTES:  
1. With output deselected, (OE ≥ VIH).  
2. Characterized values, not currently tested.  
3. CIN for Vref is 40pF.  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. Compliant with JEDEC JESD8-5. VCC terminal only.  
RECOMMENDED DC OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min.  
2.375  
0
Typ.  
2.5  
0
Max.  
2.625  
0
Unit  
V
SupplyVoltage  
SupplyVoltage  
GND  
V
VIH  
InputHighVoltage  
⎯ LVTTL  
⎯ eHSTL  
⎯ HSTL  
1.7  
VREF+0.2  
VREF+0.2  
—
—
—
3.45  
VDDQ+0.3  
VDDQ+0.3  
V
V
V
VIL  
InputLowVoltage  
⎯ LVTTL  
⎯ eHSTL  
⎯ HSTL  
-0.3  
-0.3  
-0.3  
—
—
—
0.7  
VREF-0.2  
VREF-0.2  
V
V
V
VREF(1)  
TA  
VoltageReferenceInput ⎯ eHSTL  
⎯ HSTL  
0.8  
0.68  
0.9  
0.75  
1.0  
0.9  
V
V
OperatingTemperatureCommercial  
OperatingTemperatureIndustrial  
0
—
—
70  
85  
°C  
°C  
TA  
-40  
NOTE:  
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.  
2. Outputs are not 3.3V tolerant.  
FEBRUARY04,2009  
8
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
DCELECTRICALCHARACTERISTICS  
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)  
Symbol  
ILI  
Parameter  
Min.  
–10  
Max.  
10  
Unit  
µA  
µA  
V
V
V
InputLeakageCurrent  
ILO  
OutputLeakageCurrent  
OutputLogic“1”Voltage,  
–10  
10  
(5)  
VOH  
IOH = –8 mA @VDDQ = 2.5V 0.125V (LVTTL)  
IOH = –8 mA @VDDQ = 1.8V 0.1V (eHSTL)  
IOH = –8 mA @VDDQ = 1.5V 0.1V (HSTL)  
VDDQ-0.4  
VDDQ-0.4  
VDDQ-0.4  
—
—
—
VOL  
OutputLogic“0”Voltage,  
IOL = 8 mA @VDDQ = 2.5V 0.125V (LVTTL)  
IOL = 8 mA @VDDQ = 1.8V 0.1V (eHSTL)  
IOL = 8 mA @VDDQ = 1.5V 0.1V (HSTL)  
—
—
—
0.4V  
0.4V  
0.4V  
V
V
V
ICC1(1,2)  
ICC2(1)  
Active VCC Current (VCC = 2.5V)  
I/O = LVTTL  
I/O = HSTL  
I/O = eHSTL  
—
—
—
120  
180  
180  
mA  
mA  
mA  
Standby VCC Current (VCC = 2.5V) I/O = LVTTL  
—
—
—
40  
140  
140  
mA  
mA  
mA  
I/O = HSTL  
I/O = eHSTL  
NOTES:  
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.  
2. For the IDT72T36105/72T36115/72T36135M, typical ICC1 calculation (with data outputs in Low-Impedance):  
-3.For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)  
with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000  
fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,  
N = Number of outputs switching.  
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).  
5. Outputs are not 3.3V tolerant.  
FEBRUARY04,2009  
9
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
ACELECTRICALCHARACTERISTICS(1)—SYNCHRONOUSTIMING  
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)  
Commercial  
Com’l & Ind’l  
IDT72T36135ML6  
IDT72T36135ML5  
Symbol  
fC  
Parameter  
Clock Cycle Frequency (Synchronous)  
DataAccessTime  
Min.  
—
0.6  
5
Max.  
200  
3.6  
—
—
—
—
—
—
—
—
—
—
—
10  
Min.  
—
0.6  
6
Max.  
166  
3.8  
—
—
—
—
—
—
—
—
—
—
—
10  
Unit  
MHz  
ns  
tA  
tCLK  
tCLKH  
tCLKL  
tDS  
Clock Cycle Time  
ns  
Clock High Time  
2.5  
2.5  
1.5  
0.5  
1.5  
0.5  
1.5  
0.5  
1.5  
0.5  
—
100  
45  
3.0  
3.0  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
—
100  
45  
ns  
Clock Low Time  
ns  
DataSetupTime  
ns  
tDH  
DataHoldTime  
ns  
tENS  
EnableSetupTime  
EnableHoldTime  
ns  
tENH  
tLDS  
ns  
LoadSetupTime  
ns  
tLDH  
LoadHoldTime  
ns  
tWCSS  
tWCSH  
fS  
WCSsetuptime  
WCSholdtime  
Clock Cycle Frequency (SCLK)  
Serial Clock Cycle  
Serial Clock High  
ns  
ns  
MHz  
ns  
tSCLK  
tSCKH  
tSCKL  
tSDS  
—
—
—
—
—
—
—
—
—
—
—
15  
—
—
—
—
—
—
—
—
—
—
—
15  
ns  
Serial Clock Low  
45  
45  
ns  
SerialDataInSetup  
Serial Data In Hold  
SerialEnableSetup  
SerialEnable Hold  
15  
15  
ns  
tSDH  
tSENS  
tSENH  
tRS  
5
5
ns  
5
5
ns  
5
5
ns  
(3)  
ResetPulseWidth  
10  
10  
ns  
tRSS  
ResetSetupTime  
15  
15  
ns  
tHRSS  
tRSR  
tRSF  
tWFF  
tREF  
tPAFS  
tPAES  
tRCSLZ  
HSTLResetSetupTime  
4
4
µs  
ns  
ResetRecoveryTime  
10  
10  
ResettoFlagandOutputTime  
Write Clock to FF[1:2] or IR[1:2]  
Read Clock to EF[1:2] or OR[1:2]  
Write Clock to Synchronous PAF[1:2]  
Read Clock to Synchronous PAE[1:2]  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
4
3.7  
3.7  
3.7  
3.7  
3.7  
3.7  
5
ns  
ns  
ns  
ns  
(3)  
RCLK to Active from High-Z  
ns  
(3)  
tRCSHZ RCLK to High-Z  
ns  
tSKEW1 Skew time between RCLK and WCLK for EF[1:2] and FF[1:2]  
tSKEW2 Skew time between RCLK and WCLK for PAE[1:2] and PAF[1:2]  
ns  
5
6
ns  
NOTES:  
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.  
2. Pulse widths less than minimum values are not allowed.  
3. Values guaranteed by design, not currently tested.  
4. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order.  
FEBRUARY04,2009  
10  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
ACELECTRICALCHARACTERISTICS⎯ ASYNCHRONOUSTIMING  
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)  
Commercial  
Com’l & Ind’l  
IDT72T36135ML6  
IDT72T36135ML5  
Symbol  
fA  
Parameter  
Cycle Frequency (Asynchronous)  
DataAccessTime  
Min.  
—
0.6  
12  
5
Max.  
83  
Min.  
—
0.6  
15  
7
Max.  
66  
Unit  
MHz  
ns  
tAA  
10  
12  
tCYC  
Cycle Time  
—
—
—
—
10  
—
—
—
—
12  
ns  
tCYH  
Cycle HIGH Time  
ns  
tCYL  
Cycle LOW Time  
5
7
ns  
tRPE  
Read Pulse after EF[1:2] HIGH  
Clock to Asynchronous FF[1:2]  
Clock to Asynchronous EF[1:2]  
ClocktoAsynchronousProgrammableAlmost-FullFlag  
ClocktoAsynchronousProgrammableAlmost-EmptyFlag  
10  
—
—
—
—
0
12  
—
—
—
—
0
ns  
tFFA  
tEFA  
tPAFA  
tPAEA  
tOLZ  
ns  
10  
12  
ns  
10  
12  
ns  
10  
12  
ns  
(3)  
OutputEnabletoOutputinLowZ  
—
3.6  
3.6  
10  
—
3.8  
3.8  
12  
ns  
tOE  
OutputEnabletoOutputValid  
—
—
—
—
—
—
ns  
(3)  
tOHZ  
tHF  
OutputEnabletoOutputinHighZ  
ns  
Clock to HF  
ns  
NOTES:  
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.  
2. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order.  
3. Values guaranteed by design, not currently tested.  
FEBRUARY04,2009  
11  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
HSTL  
AC TEST LOADS  
1.5V AC TEST CONDITIONS  
VDDQ/2  
InputPulseLevels  
0.25to1.25V  
0.4ns  
50Ω  
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
0.75  
Z0 = 50Ω  
I/O  
10pF  
VDDQ/2  
6723 drw04  
NOTE:  
1. VDDQ = 1.5V±.  
Figure 2a. AC Test Load  
EXTENDEDHSTL  
1.8V AC TEST CONDITIONS  
6
5
4
3
2
1
InputPulseLevels  
0.4 to 1.4V  
0.4ns  
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
0.9  
VDDQ/2  
NOTE:  
1. VDDQ = 1.8V±.  
20 30 50 80 100  
Capacitance (pF)  
200  
6723 drw04a  
Figure 2b. Lumped Capacitive Load, Typical Derating  
2.5VLVTTL  
2.5V AC TEST CONDITIONS  
InputPulseLevels  
GND to 2.5V  
1ns  
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
VCC/2  
VDDQ/2  
NOTE:  
1. For LVTTL VCC = VDDQ.  
FEBRUARY04,2009  
12  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
OUTPUT ENABLE & DISABLE TIMING  
Output  
Enable  
Output  
Disable  
VIH  
OE  
VIL  
tOE &  
tOLZ  
tOHZ  
V
2
CC  
Output  
Normally  
LOW  
V
2
CC  
100mV  
100mV  
100mV  
V
OL  
V
OH  
Output  
Normally  
HIGH  
VCC  
100mV  
VCC  
2
2
6723 drw05  
NOTES:  
1. REN is HIGH.  
2. RCS is LOW.  
READ CHIP SELECT ENABLE & DISABLE TIMING  
VIH  
tENH  
RCS  
VIL  
tENS  
RCLK  
tRCSHZ  
tRCSLZ  
Output  
Normally  
LOW  
VCC  
2
V
2
CC  
100mV  
100mV  
100mV  
VOL  
VOH  
Output  
Normally  
HIGH  
VCC  
100mV  
VCC  
2
2
6723 drw06  
NOTES:  
1. REN is HIGH.  
2. OE is LOW.  
FEBRUARY04,2009  
13  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
WhentheFIFOisfull,theFullFlag(FF[1:2])willgoLOW,inhibitingfurther  
writeoperations.Ifnoreadsareperformedafterareset,FF[1:2]willgoLOW  
afterDwrites tothe FIFO.  
FUNCTIONALDESCRIPTION  
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH  
(FWFT) MODE  
TheIDT72T36135Msupporttwodifferenttimingmodesofoperation:IDT  
Standardmode orFirstWordFallThrough(FWFT)mode. The selectionof  
whichmodewilloperateisdeterminedduringMasterReset,bythestateofthe  
FWFT/SIinput.  
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode  
willbeselected.ThismodeusestheEmptyFlag(EF[1:2])toindicatewhether  
ornotthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction  
(FF[1:2])toindicatewhetherornottheFIFOhasanyfreespaceforwriting.In  
IDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must  
be requested using the Read Enable (REN) and RCLK.  
If the FIFO is full, the first read operation will cause FF[1:2] to go HIGH.  
SubsequentreadoperationswillcausePAF[1:2]togoHIGHattheconditions  
describedinTable2.Iffurtherreadoperationsoccur,withoutwriteoperations,  
PAE[1:2]willgoLOWwhentherearenwordsintheFIFO,wherenistheempty  
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.  
When the last word has been read from the FIFO, the EF[1:2] will go LOW  
inhibitingfurtherreadoperations. REN is ignoredwhenthe FIFOis empty.  
WhenconfiguredinIDTStandardmode,theEF[1:2]andFF[1:2]outputs  
aredoubleregister-bufferedoutputs.  
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure  
10, 11, 12 and 17.  
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe  
selected.ThismodeusesOutputReady(OR[1:2])toindicatewhetherornot  
there is validdata atthe data outputs (Qn). Italsouses InputReady(IR[1:2])  
toindicatewhetherornottheFIFOhasanyfreespaceforwriting.IntheFWFT  
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK  
rising edges, REN = LOW is not necessary. Subsequent words must be  
accessed using the Read Enable (REN) and RCLK.  
FIRST WORD FALL THROUGH MODE (FWFT)  
In this mode, the status flags, IR[1:2], PAF[1:2], PAE[1:2], and OR[1:2]  
operateinthemanneroutlinedinTable3.TowritedataintototheFIFO,WEN  
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO  
onsubsequenttransitionsofWCLK.Afterthefirstwriteisperformed,theOutput  
Ready(OR[1:2])flagwillgoLOW.Subsequentwriteswillcontinuetofillupthe  
FIFO.PAE[1:2]willgoHIGHaftern + 2wordshavebeenloadedintotheFIFO,  
wherenistheemptyoffsetvalue.Thedefaultsettingforthesevaluesarestated  
inthefootnoteofTable1.Thisparameterisalsouserprogrammable.Seesection  
onProgrammableFlagOffsetLoading.  
WhentheFIFOisfull,theInputReady(IR[1:2])flagwillgoHIGH,inhibiting  
furtherwriteoperations.Ifnoreadsareperformedafterareset,IR[1:2]willgo  
HIGHafterDwritestotheFIFO.NotethattheadditionalwordinFWFTmode  
isduetothecapacityofthememoryplusoutputregister.  
IftheFIFOisfull,thefirstreadoperationwillcausetheIR[1:2]flagtogoLOW.  
SubsequentreadoperationswillcausethePAF[1:2]togoHIGHattheconditions  
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,  
the PAE[1:2] willgoLOWwhenthere are n+1words inthe FIFO, where nis  
the empty offset value. Continuing read operations will cause the FIFO to  
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,OR[1:2]will  
goHIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOis  
empty.  
WhenconfiguredinFWFTmode,theOR[1:2]flagoutputistripleregister-  
buffered,andtheIR[1:2]flagoutputisdoubleregister-buffered.  
Relevanttimingdiagrams forFWFTmodecanbefoundinFigure13,14,  
15 and 18.  
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending  
onwhichtimingmodeisineffect.  
IDT STANDARD MODE  
In this mode, the status flags, FF[1:2], PAF[1:2], PAE[1:2], and EF[1:2]  
operateinthemanneroutlinedinTable2.TowritedataintototheFIFO,Write  
Enable(WEN)mustbeLOW.DatapresentedtotheDATAINlineswillbeclocked  
intotheFIFOonsubsequenttransitionsoftheWriteClock(WCLK).Afterthefirst  
writeisperformed,theEmptyFlag(EF[1:2])willgoHIGH.Subsequentwrites  
willcontinuetofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE[1:2])  
willgoHIGHaftern + 1wordshavebeenloadedintotheFIFO,wherenisthe  
emptyoffsetvalue.Thedefaultsettingforthesevaluesarestatedinthefootnote  
of Table 1. This parameter is also user programmable. See section on  
ProgrammableFlagOffsetLoading.  
ContinuingtowritedataintotheFIFOwillcausetheProgrammableAlmost-  
Fullflag(PAF[1:2])togoLOW.Again,ifnoreadsareperformed,thePAF[1:2]  
willgoLOW.Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthese  
values are stated in the footnote of Table 1. This parameter is also user  
programmable.SeesectiononProgrammableFlagOffsetLoading.  
FEBRUARY04,2009  
14  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PROGRAMMING FLAG OFFSETS  
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG  
TIMING SELECTION  
TheIDT72T36135McanbeconfiguredduringtheMasterResetcyclewith  
eithersynchronousorasynchronoustimingforPAF[1:2]andPAE[1:2]flagsby  
use of the PFM pin.  
IfsynchronousPAF/PAE[1:2]configurationisselected(PFM,HIGHduring  
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand  
notRCLK. Similarly, PAE[1:2] is assertedandupdatedonthe risingedge of  
RCLK only and not WCLK. For detail timing diagrams, see Figure 22 for  
synchronousPAF[1:2]timingandFigure23forsynchronousPAE[1:2]timing.  
IfasynchronousPAF/PAE[1:2]configurationisselected(PFM,LOWduring  
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand  
PAF[1:2]isresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,  
PAE[1:2]isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAE[1:2]  
is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing  
diagrams,seeFigure24forasynchronousPAF[1:2]timingandFigure25for  
asynchronousPAE[1:2]timing.  
Full and Empty Flag offset values are user programmable. The  
IDT72T36135Mhaveinternalregistersfortheseoffsets.Thereareeightdefault  
offsetvaluesselectableduringMasterReset.Theseoffsetvaluesareshown  
inTable1.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwo  
ways;serialorparallelloadingmethod.Theselectionoftheloadingmethodis  
doneusingtheLD (Load)pin.DuringMasterReset,thestateoftheLD input  
determineswhetherserialorparallelflagoffsetprogrammingisenabled.AHIGH  
onLDduringMasterResetselectsserialloadingofoffsetvalues.ALOWonLD  
duringMasterResetselectsparallelloadingofoffsetvalues.  
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread  
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport  
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis  
notpossibletoreadtheoffsetvaluesinserialfashion.  
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries  
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.  
Foramoredetaileddescription,seediscussionthatfollows.  
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter  
MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen  
selected.Validprogrammingranges arefrom0toD-1.  
TABLE 1 — DEFAULT PROGRAMMABLE TABLE 2 — STATUS FLAGS FOR IDT  
FLAG OFFSETS STANDARD MODE  
IDT72T36135M  
IDT72T36135M  
FF PAF PAE EF  
0
H
H
H
H
H
H
L
L
H
L
*LD  
H
L
L
L
FSEL1  
FSEL0  
Offsets n,m  
Number of  
Words in  
FIFO  
1 to n (1)  
H
H
L
H
L
L
L
H
L
H
L
H
H
1,023  
511  
255  
127  
63  
31  
15  
7
n + 1 to (524,288-(m+1))  
H
L
L
L
H
H
H
H
(524,288-m) to 524,287  
524,288  
L
NOTE:  
L
H
H
L
1. See Table 1 for values for n, m.  
H
H
H
H
TABLE 3 — STATUS FLAGS FOR FWFT  
MODE  
*LD  
H
L
FSEL1  
FSEL0  
Program Mode  
(3)  
IDT72T36135M  
IR  
PAF PAE OR  
X
X
X
X
Serial  
Parallel  
(4)  
0
L
L
L
H
H
H
L
L
H
H
L
L
Number of  
Words in  
FIFO  
1 to n+1  
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE  
OR READ DATATO/FROM THE FIFO MEMORY.  
n + 1 to (524,289-(m+1))  
L
L
L
H
H
L
(524,289-m) to 524,288  
524,289  
H
L
NOTES:  
6723 drw07  
NOTE:  
1. n = empty offset for PAE[1:2].  
2. m = full offset for PAF[1:2].  
1. See Table 1 for values for n, m.  
3. As well as selecting serial programming mode, one of the default values will also  
be loaded depending on the state of FSEL0 & FSEL1.  
4. As well as selecting parallel programming mode, one of the default values will  
also be loaded depending on the state of FSEL0 & FSEL1.  
FEBRUARY04,2009  
15  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
IDT72T36135M  
WCLK RCLK  
X
SCLK  
LD  
WEN  
REN  
SEN  
Parallel write to registers:  
Empty Offset (LSB)  
Empty Offset (MSB)  
Full Offset (LSB)  
X
0
0
1
1
Full Offset (MSB)  
Parallel read from registers:  
Empty Offset (LSB)  
Empty Offset (MSB)  
Full Offset (LSB)  
X
X
0
1
0
1
X
Full Offset (MSB)  
Serial shift into registers:  
0
1
1
1
1
0
1
X
38 bits for the IDT72T36135M  
1 bit for each rising SCLK edge  
Starting with Empty Offset (LSB)  
Ending with Full Offset (MSB)  
X
X
X
X
X
No Operation  
Write Memory  
X
1
1
1
0
X
1
X
0
1
X
X
X
X
X
X
X
Read Memory  
X
No Operation  
6723 drw08  
NOTES:  
1. The programming method can only be selected at Master Reset.  
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.  
3. The programming sequence applies to both IDT Standard and FWFT modes.  
1st Parallel Offset Write/Read Cycle  
D/Q17  
Data Inputs/Outputs  
D/Q16  
D/Q0  
1
EMPTY OFFSET (LSB) REGISTER  
16 15 14 13 12 11 10  
9 8 7 6 5 4 3 2  
# of Bits Used  
2nd Parallel Offset Write/Read Cycle  
D/Q17  
Data Inputs/Outputs  
D/Q0  
D/Q16  
EMPTY OFFSET (MSB) REGISTER  
19 18 17  
3rd Parallel Offset Write/Read Cycle  
D/Q17  
D/Q16  
Data Inputs/Outputs  
FULL OFFSET (LSB) REGISTER  
D/Q  
0
16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
4th Parallel Offset Write/Read Cycle  
D/Q17  
Data Inputs/Outputs  
D/Q  
0
D/Q16  
FULL OFFSET (MSB) REGISTER  
19 18 17  
6723 drw09  
NOTE:  
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of  
one RCLK cycle in between offset register accesses. (Please refer to Figure 21, Parallel Read of Programmable  
Flag Registers (IDT Standard and FWFT Modes) for more details).  
Figure 3. Programmable Flag Offset Programming Sequence  
FEBRUARY04,2009  
16  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
SERIAL PROGRAMMING MODE  
writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT  
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then standardandFWFTmodes.  
programming of PAE[1:2] and PAF[1:2] values can be achieved by using a  
DuringIDTstandardmodetheFIFOisputintoretransmitmodebyaLow-  
combinationoftheLD,SEN,SCLKandSIinputpins.ProgrammingPAE[1:2] to-HightransitiononRCLKwhenthe‘MARK’inputisHIGHandEF[1:2]isHIGH.  
andPAF[1:2] proceeds as follows:whenLD and SEN are setLOW, data on TherisingRCLKedge‘marks’thedatapresentintheFIFOoutputregisteras  
theSIinputarewritten,onebitforeachSCLKrisingedge,startingwiththeEmpty thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge  
OffsetLSBandendingwiththeFullOffsetMSB.38bitstotalrequired.SeeFigure on RCLK occurs while MARK is LOW.  
19,SerialLoadingofProgrammableFlagRegisters,forthetimingdiagramfor  
thismode.  
Oncea‘marked’locationhasbeenset(andthedeviceisstillinretransmit  
mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingedgeonRCLK  
Using the serial method, individual registers cannot be programmed whiletheretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)  
selectively. PAE[1:2] and PAF[1:2] can show a valid status only after the beforebringingRTLOW.Thedeviceindicatesthestartofretransmitsetupby  
completesetofbits(foralloffsetregisters)hasbeenentered.Theregisterscan setting EF[1:2] LOW, also preventing reads. When EF[1:2] goes HIGH,  
bereprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When retransmitsetupiscompleteandreadoperationsmaybeginstartingwiththefirst  
LD is LOW and SEN is HIGH, no serial write to the registers can occur.  
dataattheMARKlocation.SinceIDTstandardmodeisselected,everyword  
Write operations to the FIFO are allowed before and during the serial readincludingthefirst‘marked’wordfollowingaretransmitsetuprequiresaLOW  
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot on REN (read enabled).  
havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand  
Note, write operations may continue as normal during all retransmit  
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia functions,howeverwriteoperationstothe‘marked’locationwillbeprevented.  
DnbytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored See Figure 17, Retransmit from Mark (IDT standard mode), for the relevant  
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan timingdiagram.  
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW  
anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN edge whenthe ‘MARK’inputis HIGHandOR[1:2] is LOW. The risingRCLK  
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues. edge‘marks’thedatapresentintheFIFOoutputregisterasthefirstretransmit  
DuringFWFTmodetheFIFOisputintoretransmitmodebyarisingRCLK  
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag data. The FIFOremains inretransmitmode untila risingRCLKedge occurs  
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen whileMARKisLOW.  
written. MeasuringfromtherisingSCLKedgethatachievestheabovecriteria;  
PAF[1:2]willbevalidafterthreemorerisingWCLKedgesplustPAF,PAE[1:2] mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhile  
will be valid after the next three rising RCLK edges plus tPAE. theretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)before  
Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmit  
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn. bringingRTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting  
OR[1:2] HIGH.  
PARALLELMODE  
WhenOR[1:2]goesLOW,retransmitsetupiscompleteandonthenextrising  
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then RCLKedgeafterretransmitsetupiscomplete,(RTgoesHIGH),thecontents  
programming of PAE[1:2] and PAF[1:2] values can be achieved by using a ofthefirstretransmitlocationareloadedontotheoutputregister.SinceFWFT  
combinationoftheLD, WCLK,WENandDninputpins. ProgrammingPAE[1:2] modeisselected,thefirstwordappearsontheoutputsregardlessofREN,a  
and PAF[1:2] proceeds as follows: LD and WEN must be set LOW. When LOWonRENisnotrequiredforthefirstword.Readingallsubsequentwords  
programming the Offset Registers of the TeraSync FIFO’s the number of requires a LOW on REN to enable the rising RCLK edge. See Figure 18,  
programmingcycleswillbebasedonthebuswidth,thefollowingrulesapply: RetransmitfromMarktiming(FWFTmode),fortherelevanttimingdiagram.  
4enabledwritecyclesarerequiredtoprogramtheoffsetregisters,(2per  
Note,theremustbeaminimumof128wordsofdatabetweenthewritepointer  
offset).DataontheinputsDnarewrittenintotheEmptyOffsetRegisteronthe andreadpointerwhentheMARKisasserted.Also,oncetheMARKisset,the  
firsttwoLOW-to-HIGHtransitionofWCLK.UponthethirdandfourthLOW-to- write pointer will not increment past the “marked” location until the MARK is  
HIGHtransitionofWCLK,dataarewrittenintotheFullOffsetRegister.SeeFigure deasserted.Thisprevents“overwriting”ofretransmitdata.  
3, Programmable Flag Offset Programming Sequence for more details.  
HSTL/LVTTL I/O  
RETRANSMITFROMMARKOPERATION  
Both the write port and read port are user selectable between HSTL or  
TheRetransmitfromMarkfeatureallowsFIFOdatatobereadrepeatedly LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other  
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat controlpins are selectable via SHSTL, see Table 4fordetails ofgroupings.  
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO  
writeoperationsfromover-writingretransmitdata.Theretransmitdatacanbe thepowerconsumption(instand-bymodebyutilizingtheWCSinput).  
readrepeatedlyanynumberoftimesfromthe‘marked’position.TheFIFOcan All“StaticPins”mustbe tiedtoVCC orGND. These pins are LVTTLonly,  
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce  
betakenoutofretransmitmodeatanytimetoallownormaldeviceoperation. andare purelydevice configurationpins.  
The‘mark’positioncanbeselectedanynumberoftimes,eachselectionover-  
FEBRUARY04,2009  
17  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
TABLE 4 — I/O CONFIGURATION  
WHSTL SELECT  
RHSTL SELECT  
SHSTL SELECT  
STATIC PINS  
WHSTL: HIGH = HSTL  
LOW = LVTTL  
RHSTL: HIGH = HSTL  
LOW = LVTTL  
SHSTL: HIGH = HSTL  
LOW = LVTTL  
LVTTL ONLY  
Dn (I/P)  
RCLK/RD (I/P)  
RCS (I/P)  
MARK (I/P)  
REN (I/P)  
OE (I/P)  
EF/OR[1:2] (O/P)  
SCLK (I/P)  
LD (I/P)  
MRS (I/P)  
TCK (I/P)  
TMS (I/P)  
SEN (I/P)  
FWFT/SI (I/P)  
PRS (I/P)  
ASYR (I/P)  
FSEL1 (I/P)  
SHSTL (I/P)  
RHSTL (I/P)  
ASYW (I/P)  
FSEL0 (I/P)  
PFM (I/P)  
WCLK/WR (I/P)  
WEN (I/P)  
WCS (I/P)  
PAF[1:2] (O/P)  
PAE[1:2] (O/P)  
FF/IR[1:2] (O/P)  
TDO (O/P)  
TRST (I/P)  
TDI (I/P)  
WHSTL (I/P)  
RT (I/P)  
Qn (O/P)  
FEBRUARY04,2009  
18  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
ASYNCHRONOUS READ (ASYR)  
SIGNALDESCRIPTION  
INPUTS:  
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous  
mode of operation. If during a Master Reset the ASYR input is LOW, then  
Asynchronous operationofthereadportwillbeselected.DuringAsynchro-  
nousoperationofthereadporttheRCLKinputbecomesRDinput,thisisthe  
Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe  
FIFO via the output register and Qn port. (REN must be tied LOW during  
Asynchronous operationofthe readport).  
DATA IN (D0 - Dn)  
Data inputs for 36-bit wide data (D0 - D35).  
CONTROLS:  
The OE input provides three-state control of the Qn output bus, in an  
asynchronousmanner.(RCS,providesthree-statecontrolofthereadportin  
Synchronousmode).  
WhenthereadportisconfiguredforAsynchronousoperationthedevice  
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe  
read port is Asynchronous. The Empty Flag (EF[1:2]) operates in an  
Asynchronousmanner,thatis,theemptyflagwillbeupdatedbasedonboth  
areadoperationandawriteoperation.Refertofigures 32,33,34and35for  
relevanttimingandoperationalwaveforms.  
MASTER RESET ( MRS )  
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW  
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation  
of the RAM array. PAE[1:2] will go LOW, PAF[1:2] will go HIGH.  
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,  
alongwithEF[1:2]andFF[1:2]areselected.EF[1:2]willgoLOWandFF[1:2]  
will go HIGH. If FWFT/SI is HIGH, then the First Word Fall Through mode  
(FWFT),alongwithIR[1:2]andOR[1:2],areselected. OR[1:2]willgoHIGH  
and IR[1:2] will go LOW.  
AllcontrolsettingssuchasRMandPFMaredefinedduringtheMasterReset  
cycle.  
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster  
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS  
isasynchronous.  
RETRANSMIT (RT)  
The Retransmit (RT) input is used in conjunction with the MARK input,  
togethertheyprovideameansbywhichdatapreviouslyreadoutoftheFIFO  
canberereadanynumberoftimes.Ifretransmitoperationhasbeenselected  
(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhileRTisLOWwillreset  
thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.  
IfIDTstandardmodehasbeenselectedtheEF[1:2]flagwillgoLOWand  
remain LOW for the time that RT is held LOW. RT can be held LOW for any  
numberofRCLKcycles,thereadpointerbeingresettothemarkedlocation.  
ThenextrisingedgeofRCLKafterRThasreturnedHIGH,willcauseEF[1:2]  
togoHIGH,allowingreadoperationstobeperformedontheFIFO.Thenext  
readoperationwillaccessdatafromthe‘marked’memorylocation.  
Subsequentretransmitoperationsmaybeperformed,eachtimetheread  
pointerreturningtothe‘marked’location.SeeFigure17,RetransmitfromMark  
(IDTStandardmode)forthe relevanttimingdiagram.  
IfFWFTmodehasbeenselectedtheOR[1:2]flagwillgoHIGHandremain  
HIGHforthetimethatRTis heldLOW.RTcanbeheldLOWforanynumber  
ofRCLK cycles,thereadpointerbeingresettothe‘marked’location.Thenext  
RCLKrisingedgeafterRThasreturnedHIGH,willcauseOR[1:2]togoLOW  
andduetoFWFToperation,thecontentsofthemarkedmemorylocationwill  
be loaded onto the output register, a read operation being required for all  
subsequentdatareads.  
See Figure 8, Master Reset Timing, forthe relevanttimingdiagram.  
PARTIAL RESET (PRS)  
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW  
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers  
are settothe firstlocationofthe RAMarray,PAE[1:2] goes LOW, PAF[1:2]  
goes HIGH.  
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode  
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard  
modeisactive,thenFF[1:2]willgoHIGHandEF[1:2]willgoLOW. IftheFirst  
WordFallThroughmodeisactive,thenOR[1:2]willgoHIGH,andIR[1:2]will  
goLOW.  
Following Partial Reset, all values held in the offset registers remain  
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat  
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall  
zeroes. PRS is asynchronous.  
A Partial Reset is useful for resetting the device during the course of  
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe  
convenient.  
Subsequentretransmitoperationsmaybeperformedeachtimetheread  
pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark  
(FWFTmode)forthe relevanttimingdiagram.  
See Figure 9, PartialResetTiming, forthe relevanttimingdiagram.  
ASYNCHRONOUS WRITE (ASYW)  
MARK  
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous  
mode of operation. If during Master Reset the ASYW input is LOW, then  
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchro-  
nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe  
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent  
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite  
portinAsynchronous mode).  
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag  
(FF[1:2]) operates in an asynchronous manner, that is, the full flag will be  
updatedbasedinbothawriteoperationandreadoperation.Note,ifAsynchro-  
nousmodeisselected,FWFTisnotpermissable.RefertoFigures30,31,34  
and35forrelevanttimingandoperationalwaveforms.  
TheMARKinputisusedtoselectRetransmitmodeofoperation.AnRCLK  
rising edge while MARK is HIGH will mark the memory location of the data  
currently present on the output register, the device will also be placed into  
retransmitmode.FortheIDT72T36135Maminimumof128words(x36).Also,  
once the MARKis set, the write pointerwillnotincrementpastthe “marked”  
locationuntiltheMARKisdeasserted.Thisprevents“overwriting”ofretransmit  
data.  
TheMARKinputmustremainHIGHduringthewholeperiodofretransmit  
mode,afallingedgeofRCLKwhileMARKis LOWwilltakethedeviceoutof  
retransmitmodeandintonormalmode.AnynumberofMARKlocationscanbe  
setduringFIFOoperation,onlythelastmarkedlocationtakingeffect.Oncea  
FEBRUARY04,2009  
19  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
marklocationhasbeensetthewritepointercannotbeincrementedpastthis READ STROBE & READ CLOCK (RD/RCLK)  
markedlocation.Duringretransmitmodewriteoperationstothedevicemay  
continuewithouthindrance.  
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this  
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK  
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.  
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR[1:2],  
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)  
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ and PAE[1:2] flags will not be updated. The Write and Read Clocks can be  
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor independentorcoincident.  
First Word Fall Through (FWFT) mode.  
IfAsynchronousoperationhasbeenselectedthisinputisRD(ReadStrobe)  
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode .DataisAsynchronouslyreadfromtheFIFOviatheoutputregisterwhenever  
willbeselected. ThismodeusestheEmptyFlag(EF[1:2])toindicatewhether there is a rising edge on RD. In this mode the REN and RCS inputs must be  
ornotthereareanywordspresentintheFIFOmemory. ItalsousestheFull tiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthethree-  
Flagfunction(FF[1:2])toindicatewhetherornottheFIFOmemoryhas any stateQnoutputs.  
freespaceforwriting. InIDTStandardmode,everywordreadfromtheFIFO,  
includingthe first, mustbe requestedusingthe ReadEnable (REN)and WRITE CHIP SELECT (WCS)  
RCLK.  
The WCS disables all Write Port inputs (data only) if it is held HIGH. To  
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe performnormaloperationsonthewriteport,theWCSmustbeenabled,heldLOW.  
selected. ThismodeusesOutputReady(OR[1:2])toindicatewhetherornot  
thereis validdataatthedataoutputs (Qn). Italsouses InputReady(IR[1:2]) READ ENABLE (REN)  
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting. In  
When Read Enable is LOW, data is loaded from the RAM array into the  
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafter outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.  
threeRCLKrisingedges,REN=LOWis notnecessary. Subsequentwords  
must be accessed using the Read Enable (REN) and RCLK.  
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata  
and no new data is loaded into the output register. The data outputs Q0-Qn  
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAE[1:2]and maintainthepreviousdatavalue.  
PAF[1:2]offsetsintotheprogrammableregisters. Theserialinputfunctioncan  
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst  
onlybeusedwhentheserialloadingmethodhasbeenselectedduringMaster wordwrittentoanemptyFIFO, mustbe requestedusingREN providedthat  
Reset.SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayin RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag  
both IDT Standard and FWFT modes.  
(EF[1:2])willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhen  
the FIFOis empty. Once a write is performed, EF[1:2] willgoHIGHallowing  
areadtooccur. TheEF[1:2]flagisupdatedbytwoRCLKcycles+tSKEW after  
WRITE STROBE & WRITE CLOCK (WR/WCLK)  
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this thevalidWCLKcycle.BothRCSandRENmustbeactive,LOWfordatatobe  
inputbehavesasWCLK.  
read out on the rising edge of RCLK.  
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup  
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes  
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW  
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ afterthefirstwrite. RENandRCSdonotneedtobeassertedLOW fortheFirst  
IR[1:2],andPAF[1:2]flagswillnotbeupdated.TheWriteandReadClockscan Wordtofallthroughtotheoutputregister.Inordertoaccess allotherwords,  
eitherbe independentorcoincident.  
a read must be executed using REN and RCS. The RCLK LOW-to-HIGH  
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). transition after the last word has been read from the FIFO, Output Ready  
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere (OR[1:2])willgoHIGHwithatrueread(RCLKwithREN=LOW;RCS=LOW),  
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.  
inhibiting furtherreadoperations. REN is ignoredwhenthe FIFOis empty.  
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN  
mustbeheldactive,(tiedLOW).  
WRITE ENABLE (WEN)  
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray  
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored  
in the RAM array sequentially and independently of any ongoing read  
operation.  
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK  
cycle.  
Topreventdataoverflow intheIDTStandardmode,FF[1:2]willgoLOW,  
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,  
FF[1:2]willgoHIGHallowingawritetooccur. TheFF[1:2]isupdatedbytwo  
WCLKcycles +tSKEW aftertheRCLKcycle.  
SERIAL ENABLE ( SEN )  
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset  
registers. The serialprogrammingmethodmustbe selectedduringMaster  
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth  
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach  
LOW-to-HIGHtransitionofSCLK.  
When SEN is HIGH, the programmable registers retains the previous  
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT  
StandardandFWFTmodes.  
Topreventdataoverflow intheFWFTmode, IR[1:2] willgoHIGH,inhibiting  
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IR[1:2]will  
go LOW allowing a write to occur. The IR[1:2] flag is updated by two WCLK  
cycles +tSKEW afterthe validRCLKcycle.  
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.  
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN  
mustbeheldactive,(tiedLOW).  
OUTPUT ENABLE ( OE )  
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive  
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes  
intoahighimpedancestate.DuringMasteroraPartialResettheOEistheonly  
inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe  
RCS inputcanbe HIGHorLOW, ithas noeffectonthe Qnoutputs.  
FEBRUARY04,2009  
20  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
READ CHIP SELECT ( RCS )  
registers can be programmed, parallel or serial (see Table 1). After Master  
The Read Chip Select input provides synchronous control of the Read Reset, LD enables write operations to and read operations from the offset  
outputport. WhenRCSgoesLOW,thenextrisingedgeofRCLKcausesthe registers.Onlytheoffsetloadingmethodcurrentlyselectedcanbeusedtowrite  
QnoutputstogototheLow-Impedancestate. WhenRCSgoesHIGH,thenext totheregisters. Offsetregisters canbereadonlyinparallel.  
RCLKrisingedgecausestheQnoutputstoreturntoHIGHZ.DuringaMaster  
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess  
orPartialResettheRCSinputhasnoeffectontheQnoutputbus,OEistheonly oftheflagoffsetvaluesPAE[1:2]andPAF[1:2].PullingLDLOWwillbeginaserial  
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.IfOEisLOWthe loadingorparallelloadorreadoftheseoffsetvalues. THISPINMUSTBEHIGH  
QndataoutputswillbeLow-ImpedanceregardlessofRCSuntilthefirstrising AFTERMASTERRESETTOWRITEORREADDATATO/FROMTHEFIFO  
edgeofRCLKafteraResetiscomplete.ThenifRCSisHIGHthedataoutputs MEMORY.  
willgotoHigh-Impedance.  
TheRCSinputdoesnoteffecttheoperationoftheflags. Forexample,when PROGRAMMABLEFLAGMODE(PFM)  
thefirstwordiswrittentoanemptyFIFO,theEF[1:2]willstillgofromLOWto  
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-  
HIGHbasedonarisingedgeofRCLK,regardlessofthestateoftheRCSinput. mable flagtimingmode. AHIGHonPFMwillselectSynchronous Program-  
Also,whenoperatingtheFIFOinFWFTmodethefirstwordwrittentoan mableflagtimingmode.IfasynchronousPAF/PAE[1:2]configurationisselected  
emptyFIFOwillstillbeclockedthroughtotheoutputregisterbasedonRCLK, (PFM,LOWduringMRS),thePAE[1:2]isassertedLOWontheLOW-to-HIGH  
regardlessofthestateofRCS.Forthisreasontheusermusttakecarewhen transitionofRCLK.PAE[1:2]isresettoHIGHontheLOW-to-HIGHtransition  
adatawordiswrittentoanemptyFIFOinFWFTmode.IfRCSisdisabledwhen of WCLK. Similarly, the PAF[1:2] is asserted LOW on the LOW-to-HIGH  
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister, transitionofWCLKandPAF[1:2]isresettoHIGHontheLOW-to-HIGHtransition  
butwillnotbeavailableontheQnoutputswhichareinHIGH-Z.Theusermust ofRCLK.  
takeRCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.  
IfsynchronousPAE/PAF[1:2]configurationisselected(PFM,HIGHduring  
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW. MRS),thePAE[1:2]isassertedandupdatedontherisingedgeofRCLKonly  
ArisingedgeofRCLKwithRCSandRENactiveLOW,willreadoutthenext andnotWCLK.Similarly,PAF[1:2]isassertedandupdatedontherisingedge  
word. Care mustbe takensoas nottolose the firstwordwrittentoanempty ofWCLKonlyandnotRCLK.Themodedesiredisconfiguredduringmaster  
FIFOwhenRCSisHIGH.RefertoFigure16,RCSandRENReadOperation resetbythe state ofthe Programmable FlagMode (PFM)pin.  
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform  
aRetransmit. SeeFigure12forReadCycleandReadChipSelectTiming(IDT  
StandardMode). SeeFigure15forReadCycleandReadChipSelectTiming  
OUTPUTS:  
FULL FLAG ( FF/IR[1:2] )  
(First Word Fall Through Mode).  
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF[1:2])  
IfAsynchronousoperationoftheReadporthasbeenselected,thenRCS  
functionisselected.WhentheFIFOisfull,FF[1:2]willgoLOW,inhibitingfurther  
mustbeheldactive,(tiedLOW).OEprovidesthree-statecontrolofQn.  
write operations. WhenFF[1:2] is HIGH, the FIFO is not full. If no reads are  
performedafterareset(eitherMRSorPRS),FF[1:2]willgoLOWafterDwrites  
WRITE PORT HSTL SELECT (WHSTL)  
totheFIFO(D = 524,288fortheIDT72T36135M).SeeFigure10,WriteCycle  
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport  
andFullFlagTiming(IDTStandardMode),fortherelevanttiminginformation.  
canbesetuptobeeitherHSTLorLVTTL.IfWHSTLisHIGHduringtheMaster  
PleaseseeFlaggingsectionforexternalgatinginstructionsoftheseflags.  
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW  
InFWFTmode,theInputReady(IR[1:2])functionisselected.IR[1:2]goes  
atMasterReset,thenLVTTLwillbeselected.  
LOW when memory space is available for writing in data. When there is no  
TheinputsandoutputsassociatedwiththewriteportarelistedinTable4,  
longeranyfreespaceleft,IR[1:2]goesHIGH,inhibitingfurtherwriteoperations.  
I/OConfiguration.  
Ifnoreadsareperformedafterareset(eitherMRSorPRS),IR[1:2]willgoHIGH  
afterD writestotheFIFO(D = 524,288fortheIDT72T36135M).SeeFigure  
READ PORT HSTL SELECT (RHSTL)  
13, WriteTiming(FWFTMode),fortherelevanttiminginformation.  
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport  
TheIR[1:2]statusnotonlymeasuresthecontentsoftheFIFOmemory,but  
canbesetuptobeeitherHSTLorLVTTL.IfRHSTLisHIGHduringtheMaster  
alsocountsthepresenceofawordintheoutputregister. Thus,inFWFTmode,  
Reset,thenHSTLoperationofthereadportwillbeselected.IfRHSTLisLOW  
the total number of writes necessary to deassertIR[1:2] is one greater than  
atMasterReset, thenLVTTLwillbe selectedforthe readport.  
needed to assert FF[1:2] in IDT Standard mode.  
TheinputsandoutputsassociatedwiththereadportarelistedinTable4,  
FF/IR[1:2]issynchronousandupdatedontherisingedgeofWCLK.FF/  
I/OConfiguration.  
IR[1:2]aredoubleregister-bufferedoutputs.  
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonof  
SYSTEM HSTL SELECT (SHSTL)  
thewritepointertothe‘marked’location.Thisdiffersfromnormalmodewhere  
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither  
thisflagisacomparisonofthewritepointertothereadpointer.  
HSTLorLVTTL.IfSHSTLisHIGHduringMasterReset,thenHSTLoperation  
ofalltheinputsnotassociatedwiththewriteandreadportwillbeselected.If  
EMPTY FLAG ( EF/OR[1:2] )  
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs  
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag  
associatedwithSHSTLarelistedinTable4,I/OConfiguration.  
(EF[1:2])functionisselected. WhentheFIFOisempty,EF[1:2]willgoLOW,  
inhibitingfurtherreadoperations. WhenEF[1:2]isHIGH,theFIFOisnotempty.  
LOAD (LD)  
SeeFigure11,ReadCycle,EmptyFlagandFirstWordLatencyTiming(IDT  
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,  
Standard Mode), for the relevant timing information. Please see Flagging  
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor  
sectionforexternalgatinginstructionsoftheseflags.  
thePAE[1:2]andPAF[1:2]flags,alongwiththemethodbywhichtheseoffset  
FEBRUARY04,2009  
21  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
InFWFTmode,theOutputReady(OR[1:2])functionisselected.OR[1:2]  
IfasynchronousPAF[1:2]configurationisselected,thePAF[1:2]isasserted  
goesLOWatthesametimethatthefirstwordwrittentoanemptyFIFOappears LOWontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAF[1:2]is  
validontheoutputs. OR[1:2]staysLOWaftertheRCLKLOWtoHIGHtransition reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If  
thatshiftsthelastwordfromtheFIFOmemorytotheoutputs. OR[1:2]goesHIGH synchronousPAF[1:2]configurationisselected,thePAF[1:2]isupdatedonthe  
onlywithatrueread(RCLKwithREN=LOW). Thepreviousdatastaysatthe risingedgeofWCLK. SeeFigure24,AsynchronousAlmost-FullFlagTiming  
outputs,indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil (IDT Standard and FWFT Mode).  
OR[1:2]goesLOWagain.SeeFigure14,ReadTiming(FWFTMode),forthe  
relevanttiminginformation.  
EF/OR[1:2] is synchronous and updated on the rising edge of RCLK.  
In IDT Standard mode, EF[1:2] is a double register-buffered output. In  
FWFTmode,OR[1:2]isatripleregister-bufferedoutput.  
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe  
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis  
flagis acomparisonofthewritepointertothereadpointer.  
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE[1:2])  
TheProgrammableAlmost-Emptyflag(PAE[1:2])willgoLOWwhenthe  
FIFOreachesthealmost-emptycondition.InIDTStandardmode,PAE[1:2]will  
PROGRAMMABLE ALMOST-FULL FLAG ( PAF[1:2] )  
TheProgrammableAlmost-Fullflag(PAF[1:2])willgoLOWwhentheFIFO goLOWwhentherearenwordsorlessintheFIFO.Theoffset“n”istheempty  
reaches the almost-full condition. In IDT Standard mode, if no reads are offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.  
performed after reset (MRS), PAF[1:2] will go LOW after (D - m)words are PleaseseeFlaggingsectionforexternalgatinginstructionsoftheseflags.  
writtentotheFIFO.ThePAF[1:2]willgoLOWafter(524,288-m)writesforthe  
In FWFT mode, the PAE[1:2] will go LOW when there are n+1 words or  
IDT72T36135M.Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthis less intheFIFO.Thedefaultsettingforthis valueis statedinTable1.  
valueisstatedinthefootnoteofTable2,StatusFlagsforIDTStandardMode.  
PleaseseeFlaggingsectionforexternalgatinginstructionsoftheseflags.  
InFWFTmode,thePAF[1:2]willgoLOWafter(524,289-m)writesforthe  
SeeFigure23, Synchronous ProgrammableAlmost-EmptyFlagTiming  
(IDTStandardandFWFTMode), forthe relevanttiminginformation.  
IfasynchronousPAE[1:2]configurationisselected,thePAE[1:2]isasserted  
IDT72T36135M,wheremisthefulloffsetvalue.Thedefaultsettingforthisvalue LOWontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAE[1:2]is  
is statedinTable 3, Status Flags forFWFTMode. resettoHIGHonthe LOW-to-HIGHtransitionofthe Write Clock(WCLK). If  
SeeFigure22,SynchronousProgrammableAlmost-FullFlagTiming(IDT synchronousPAE[1:2]configurationisselected,thePAE[1:2]isupdatedonthe  
StandardandFWFTMode),fortherelevanttiminginformation.  
risingedgeofRCLK. SeeFigure25,AsynchronousProgrammableAlmost-  
Empty Flag Timing (IDT Standard and FWFT Mode).  
FEBRUARY04,2009  
22  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
CONSIDERATIONS FOR READING FLAG OUTPUTS  
gateisusedforFWFTmodeandanANDgateisusedforIDTmode. Thismust  
Onthisdevice,therearetwosetsofflaggingoutputsfortheemptyflag(EF1 bedonetoavoidtimingskewproblemsbetweenthetwosetsofflags.Forthe  
& EF2), full flag (FF1 & FF2), Programmable Almost Empty Flag (PAE1 & PAE[1:2]andPAF[1:2]activelowoutputflags,theuserhastheoptiontoleave  
PAE2),andProgrammableAlmostFullFlag(PAF1&PAF2)theusermustwork thePAE[1:2]andPAF[1:2]asisandusebothpinsatdifferentprogrammable  
withinordertobeabletocorrectlyreadthestatusofeachflag. Sincethisdevice watermarks formeasuringbufferstatus. Please see the sectiononParallel  
isamulti-chipmodule(MCM),bothdie’sflagsmustbereadaccordinglytoavoid ProgrammingModetounderstandhowtoprogramthesetwosetsofflagsas  
skewingproblemsbetweenthetwointernaldie.  
differentwatermarksinFunctionalDescriptionsectionofthedatasheet. This  
Toremedythis function,theusermusttietogetherFF1 &FF2,andEF1& givesaddedflexibilityforqueuemanagement.Belowisanexamplediagram  
EF2flagoutputstoanexternalgatefromaneighboringprogrammabledevice forhowthisisaccomplished.  
suchasanFPGAorPLDandreadfromtheoutputofthelogicalgate. AnOR  
IDT72T36135M  
EF1  
EF2  
FF1  
FF2  
PAE1  
PAE2  
PAF1  
PAF2  
OPTIONAL  
GATE  
(1)  
GATE  
(1)  
AND  
GATE  
AND  
GATE  
EF  
FF  
PAE  
PAF  
6723 drw10  
NOTE:  
1. An “OR” Gate is used for FWFT mode, and an “AND” Gate is used for IDT Standard mode.  
Figure 4. Output Flag Gating Considerations  
interspersedparity. Fromthesechanges,the18MFIFOhasremovedspecific  
PINCOMPATIBILITYWITH9MTERASYNC(IDT72T36125)CONSIDER-  
ATIONS  
inputssuchasIW,OW,BM,BE,IP,whilealsogaininganothersetofoutputflags  
as specified in Considerations for Reading Flag Outputs which are EF2,  
FF2, PAE2, and PAF2.  
Tomaintaindrop-inreplacementcompatibilityforthe18MTeraSync,thepin  
changesonthepindiagramforthe18MTeraSyncFIFOfromthe9MTeraSync  
FIFOhave beenidentified, andlistedinthe table below.  
TheIDT72T36135Mcanbeadropandreplacementforthe9MTeraSync  
(IDT72T36125)ifspecificpinchangesaremadetothe18MFIFO. Sincethe  
18MTeraSyncisaMulti-ChipModule(MCM),containingtwo9MTeraSyncs  
(IDT72T18125) in width expansion mode, certain functionality can not be  
offered in the 18M TeraSync such as bus matching, single flag outputs and  
TABLE 5 — PIN CHANGES BETWEEN 9M TERASYNC AND 18M TERASYNC  
9M TeraSync FIFO (IDT72T36125)  
18M TeraSync FIFO (IDT72T36135M)  
pins changed  
new pins  
BM  
IP  
EF2  
PAE2  
IW  
NC (No Connect)  
NC (No Connect)  
PAF2  
OW  
HF  
EREN  
ERCLK  
BE  
FF2  
NC (No Connect)  
GND  
NOTES:  
1. Internally, the 9M pins on the left side of the table will be tied to the GND or VDD plane, respectively in the 18M device.  
2. Please see IDT72T36125 TeraSync FIFO datasheet for additional features listed.  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
JTAG signaling must be provided serially to each array and utilize the  
information provided in the Scan Register Descriptions, JTATG Instruction  
Description.Specifically,commandsforArrayBmustprecedethoseArrayA  
in any JTAG operations sent to the IDT72T36135M. Please reference  
Application Note AN-411, “JTAG Testing of Multichip Modules” for specific  
instructions on performing JTAG testing on the IDT72T36135M. AN-411 is  
availableatwww.idt.com.  
JTAG FUNCTIONALITY AND CON-  
FIGURATION  
TheIDT72T36135Miscomposedoftwoindependentmemoryarrays,and  
thuscannotbetreatedasasingleJTAGdeviceinthescanchain.Thetwoarrays  
(AandB)eachhaveidenticalcharacteristicsandcommandsbutmustbetreated  
as separate entities in JTAG operations. Please refer to Figure 5, JTAG  
Configuration for IDT72T36135M.  
TDI  
TDOA  
TDIB  
TDO  
Array A  
Array B  
TCK  
TMS  
TRST  
6723 drw11  
Figure 5. JTAG Configuration for IDT72T36135M  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
JTAGTIMINGSPECIFICATION  
tTCK  
t4  
t1  
t2  
TCK  
t3  
TDI/  
TMS  
tDS  
tDH  
TDO  
TDO  
tDO  
t6  
TRST  
6723 drw12  
Notes to diagram:  
t1 = tTCKLOW  
t2 = tTCKHIGH  
t5  
t3 = tTCKFALL  
t4 = tTCKRISE  
t5 = tRST (reset pulse width)  
t6 = tRSR (reset recovery)  
JTAG  
ACELECTRICALCHARACTERISTICS  
(vcc = 2.5V 5%; Tcase = 0°C to +85°C)  
Parameter  
Symbol  
Test  
IDT72T36135M  
Conditions  
Min. Max. Units  
SYSTEMINTERFACEPARAMETERS  
JTAGClockInputPeriod tTCK  
-
-
-
-
-
-
-
100  
40  
40  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
JTAGClockHIGH  
JTAGClockLow  
tTCKHIGH  
IDT72T36135M  
tTCKLOW  
tTCKRISE  
tTCKFALL  
tRST  
-
Parameter  
Symbol Test Conditions Min. Max. Units  
JTAGClockRiseTime  
JTAGClockFallTime  
JTAGReset  
5(1)  
5(1)  
-
(1)  
DataOutput  
tDO  
-
20  
-
ns  
ns  
ns  
(1)  
-
DataOutputHold tDOH  
0
50  
50  
DataInput  
tDS  
tDH  
trise=3ns  
tfall=3ns  
10  
10  
-
-
JTAG Reset Recovery  
tRSR  
-
NOTE:  
1. 50pf loading on external output signals.  
NOTE:  
1. Guaranteed by design.  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
•
•
•
TAPcontroller  
Instruction Register (IR)  
Data Register Port (DR)  
JTAGINTERFACE  
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to  
supporttheJTAGboundaryscaninterface.TheIDT72T36135Mincorporates  
thenecessarytapcontrollerandmodifiedpadcellstoimplementtheJTAG facility.  
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage  
programfilesforthesedevices.  
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora  
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification  
(IEEEStd. 1149.1-1990).  
TheStandardJTAGinterfaceconsistsoffourbasicelements:  
The Figure belowshows the standardBoundary-ScanArchitecture  
•
Test Access Port (TAP)  
Mux  
DeviceID Reg.  
Boundary Scan Reg.  
Bypass Reg.  
TDO  
TDI  
T
A
P
clkDR, ShiftDR  
UpdateDR  
TMS  
TAP  
TCLK  
Cont-  
roller  
TRST  
Instruction Decode  
clklR, ShiftlR  
UpdatelR  
Instruction Register  
Control Signals  
6723 drw13  
Figure 6. Boundary Scan Architecture  
THETAPCONTROLLER  
TEST ACCESS PORT (TAP)  
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto  
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction  
andDataRegisters forcaptureandupdateofdata.  
The Tap interface is a general-purpose port that provides access to the  
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)  
and one output port (TDO).  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
1
Test-Logic  
Reset  
0
1
0
1
1
Run-Test/  
Idle  
Select-  
DR-Scan  
Select-  
IR-Scan  
0
0
1
1
Capture-DR  
Capture-IR  
0
0
0
0
Shift-IR  
Shift-DR  
1
1
1
1
Input = TMS  
Exit1-IR  
Exit1-DR  
0
0
0
0
Pause-IR  
Pause-DR  
1
1
Exit2-IR  
Exit2-DR  
0
0
1
1
Update-IR  
Update-DR  
1
0
1
0
6723 drw14  
NOTES:  
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.  
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).  
3. TAP controller must be reset before normal FIFO operations can begin.  
Figure 7. TAP Controller State Diagram  
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction  
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The  
lasttwosignificantbits arealways requiredtobe“01”.  
Shift-IR In this controller state, the instruction register gets connected  
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge  
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction  
register.  
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-  
IRstateorUpdate-IRstateismade.  
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction  
registertobetemporarilyhalted.  
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-  
IRstateorUpdate-IRstateismade.  
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris  
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof  
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.  
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata  
registersselectedbythecurrentinstructionontherisingedgeofTCK.  
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These  
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand  
Update-IRstatesintheInstructionpath.  
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.  
1149.1)forthefullstatediagram  
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe  
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression  
thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence  
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See  
TRSTdescriptionformoredetails onTAPcontrollerreset.  
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe  
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch  
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset  
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This  
is the reason why the Test Reset (TRST) pin is optional.  
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif  
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself  
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic  
intheICis idles otherwise.  
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe  
DataPathortheSelect-IR-Scanstateismade.  
Select-IR-Scan This is a controller state where the decision to enter the  
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate  
otherwise.  
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™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
JTAG INSTRUCTION REGISTER  
SCANREGISTERDESCRIPTIONS  
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice  
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto  
performthefollowing:  
THE INSTRUCTION REGISTER  
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe  
processor at the rising edge of TCLK.  
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata  
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched  
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-  
IRstate.  
Theinstructionregistermustcontain8bitinstructionregister-basedcells  
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe  
serialoutputstheyaretheleastsignificantbits.  
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis  
current. Theothertestdataregistersshouldnotinterferewithchip  
operationandtheselecteddataregister.  
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween  
TDI and TDO during data register scanning.  
•
The Instruction Register is a 8 bit field (i.e.IR3, IR2, IR1, IR0 per die) to  
decode32differentpossibleinstructions. Instructionsaredecodedasfollows.  
Please note:  
Again,sincethisdeviceisatwodieMCM,theJTAGinstructionsmustbeshifted  
intwiceduringJTAGtesting.Toaccountforeachdies4bitinstructionregisters  
foratotalof8bitsaltogether.  
TESTDATAREGISTER  
TheTestDataregistercontainsthreetestdataregisters:theBypass,the  
Boundary Scan register and Device ID register.  
Theseregistersareconnectedinparallelbetweenacommonserialinput  
andacommonserialdataoutput.  
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora  
completedescription,refertotheIEEEStandardTestAccessPortSpecification  
(IEEEStd. 1149.1-1990).  
JTAGINSTRUCTIONDESCRIPTION  
Hex  
Instruction  
Function  
Value  
0x00  
0x22  
0x11  
0x33  
0xFF  
EXTEST  
IDCODE  
SAMPLE/PRELOAD  
HIGH-IMPEDANCE  
BYPASS  
SelectBoundaryScanRegister  
SelectChipIdentificationdataregister  
SelectBoundaryScanRegister  
JTAG  
TEST BYPASS REGISTER  
SelectBypassRegister  
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI  
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.  
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage  
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in  
theCapture-DRstate.  
JTAG Instruction Register Decoding  
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For  
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification  
(IEEEStd. 1149.1-1990).  
The operation of the bypass register should not have any effect on the  
operationofthedeviceinresponsetotheBYPASSinstruction.  
EXTEST  
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-  
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI  
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto  
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip  
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof  
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts  
andoflogicclusterfunction.  
THE BOUNDARY-SCAN REGISTER  
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread  
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart  
oftheIEEE1149.1-1990StandardJTAGImplementation.  
THE DEVICE IDENTIFICATION REGISTER  
The Device IdentificationRegisteris a ReadOnly64-bitregisterusedto  
specify the manufacturer, part number and version of the processor to be  
determinedthroughtheTAPinresponsetotheIDCODEinstruction.  
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity  
is droppedinthe11-bitManufacturerIDfield.  
IDCODE  
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode  
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween  
TDIandTDO.Thedeviceidentificationregisterisa64-bitshiftregistercontaining  
information regarding the IC manufacturer, device type, and version code.  
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation  
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately  
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe  
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe  
Test-Logic-Resetstate.  
For the IDT72T36135M, the Part Number field contains the following  
values:  
Device  
IDT72T36135M  
Part# Field  
0417  
31(MSB)  
28 27  
12 11  
1 0(LSB)  
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)  
0X0  
0X33  
1
SAMPLE/PRELOAD  
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina  
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected  
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan  
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata  
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto  
theboundary-scanregisterbeforeloadinganEXTESTinstruction.  
IDT72T36135MJTAGDevice Identification Register  
Please note:  
The IDT72T36135Mdevice is a twodie MCMwhichmeans 64bits willbe  
shiftedoutofthedevicewhentheuserisinIDCODE.SincetheJTAGdevice  
identificationregisteris32bitsperdie.  
FEBRUARY04,2009  
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™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
BYPASS  
HIGH-IMPEDANCE  
The required BYPASS instruction allows the IC to remain in a normal  
functional mode and selects the one-bit bypass register to be connected  
betweenTDIandTDO.TheBYPASSinstructionallowsserialdatatobetransferred  
throughtheICfromTDItoTDOwithoutaffectingtheoperationoftheIC.  
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state  
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand  
selects the one-bit bypass register to be connected between TDI and TDO.  
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI  
toTDOwithoutaffectingtheconditionoftheICoutputs.  
FEBRUARY04,2009  
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COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
tRS  
MRS  
t
RSR  
RSR  
t
RSS  
RSS  
REN  
WEN  
t
t
tRSS  
tRSR  
FWFT/SI  
tRSS  
tRSR  
LD  
tRSS  
FSEL0,  
FSEL1  
t
t
t
HRSS  
WHSTL  
RHSTL  
SHSTL  
HRSS  
HRSS  
tRSS  
PFM  
tRSS  
RT  
tRSS  
SEN  
tRSF  
If FWFT = HIGH, OR = HIGH  
If FWFT = LOW, EF = LOW  
EF/OR[1:2]  
tRSF  
If FWFT = LOW, FF = HIGH  
If FWFT = HIGH, IR = LOW  
FF/IR[1:2]  
t
RSF  
RSF  
PAE[1:2]  
PAF[1:2]  
t
tRSF  
OE = HIGH  
OE = LOW  
Q0 - Qn  
6723 drw15  
NOTE:  
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK  
after Master Reset is complete.  
Figure 8. Master Reset Timing  
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524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
tRS  
PRS  
tRSS  
tRSR  
REN  
tRSS  
tRSR  
WEN  
RT  
tRSS  
tRSS  
SEN  
If FWFT = HIGH, OR = HIGH  
If FWFT = LOW, EF = LOW  
If FWFT = LOW, FF = HIGH  
If FWFT = HIGH, IR = LOW  
t
RSF  
EF/OR  
[1:2]  
tRSF  
FF/IR  
[1:2]  
tRSF  
PAE  
[1:2]  
tRSF  
PAF  
[1:2]  
tRSF  
OE = HIGH  
OE = LOW  
Q0 - Qn  
6723 drw16  
NOTE:  
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge  
of RCLK after Master Reset is complete.  
Figure 9. Partial Reset Timing  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™
                                                                                         
36-BIT FIFO  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
t
CLK  
tCLKH  
t
CLK  
NO WRITE  
NO WRITE  
L
WCLK  
2
1
(1)  
1
(1)  
2
t
SKEW1  
tDH  
t
SKEW1  
tDS  
tDH  
tDS  
D
X+1  
DX  
D0 - Dn  
tWFF  
tWFF  
tWFF  
tWFF  
FF[1:2]  
WEN  
RCLK  
tENS  
tENS  
tENS  
tENH  
tENH  
REN  
RCS  
tA  
tA  
Q0 - Qn  
NEXT DATA READ  
DATA READ  
6723 drw17  
tRCSLZ  
NOTES:  
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF[1:2] will go HIGH (after one WCLK cycle pus tWFF). If the time between  
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF[1:2] deassertion may be delayed one extra WCLK cycle.  
2. LD = HIGH, OE = LOW, EF[1:2] = HIGH.  
3. WCS = LOW.  
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)  
tCLK  
tCLKH  
tCLKL  
1
2
RCLK  
REN  
tENH  
tENS  
tENS  
tENH  
tENH  
tENS  
NO OPERATION  
NO OPERATION  
tREF  
tREF  
tREF  
EF[1:2]  
Q0 - Qn  
tA  
t
A
tA  
D0  
LAST WORD  
D1  
LAST WORD  
t
OLZ  
tOHZ  
tOLZ  
t
OE  
OE  
WCLK  
WEN  
(1)  
SKEW1  
t
tENS  
tENH  
tENH  
tENS  
tWCSS  
tWCSH  
WCS  
tDS  
tDH  
tDH  
tDS  
D0  
D1  
D0 - Dn  
6723 drw18  
NOTES:  
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF[1:2] will go HIGH (after one RCLK cycle plus tREF). If the time between  
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF[1:2] deassertion may be delayed one extra RCLK cycle.  
2. LD = HIGH.  
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.  
4. RCS is LOW.  
Figure 11. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)  
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™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
2
1
RCLK  
tENS  
REN  
RCS  
tENS  
tENS  
tENS  
tENH  
tREF  
tREF  
EF[1:2]  
tRCSHZ  
t
RCSH  
Z
tA  
tA  
tRCSLZ  
tRCSLZ  
LAST DATA-1  
LAST DATA  
Q0 - Qn  
t
SKEW1(1)  
WCLK  
tENS  
tENH  
WEN  
tDS  
tDH  
Dn  
Dx  
6723 drw19  
NOTES:  
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF[1:2] will go HIGH (after one RCLK cycle plus tREF). If the time between  
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF[1:2] deassertion may be delayed one extra RCLK cycle.  
2. LD = HIGH.  
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.  
4. OE is LOW.  
Figure 12. Read Cycle and Read Chip Select (IDT Standard Mode)  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
FEBRUARY04,2009  
34  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
FEBRUARY04,2009  
35  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
FEBRUARY04,2009  
36  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
RNE  
ERN RNE  
REN ERN  
RSC  
CRS RSC  
RCS CRS  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
FEBRUARY04,2009  
38  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
FEBRUARY04,2009  
39  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™
                                                                                         
36-BIT FIFO  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
t
SCLK  
tSCKH  
t
SCKL  
SCLK  
tSENH  
tSENS  
tENH  
SEN  
LD  
tLDS  
tLDS  
tLDH  
tSDH  
tSDS  
BIT 19  
BIT 19  
BIT 1  
BIT 1  
SI  
6723 drw26  
FULL OFFSET  
EMPTY OFFSET  
Figure 19. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)  
tCLK  
tCLKH  
tCLKL  
WCLK  
LD  
tLDH  
tLDS  
tLDH  
tENH  
tENS  
tENH  
WEN  
tDS  
tDH  
tDH  
PAF  
OFFSET  
PAE  
OFFSET  
D0 - Dn  
6723 drw27  
Figure 20. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)  
tCLK  
tCLKH  
tCLKL  
RCLK  
tLDH  
tLDH  
tLDH  
tLDS  
tLDS  
tLDS  
LD  
tENH  
tENH  
tENH  
tENS  
tENS  
tENS  
REN  
t
A
t
A
tA  
DATA IN OUTPUT REGISTER  
PAE OFFSET VALUE  
PAF OFFSET VALUE  
PAE OFFSET  
Q0 - Qn  
6723 drw28  
NOTES:  
1. OE = LOW.  
2. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.  
Figure 21. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™
                                                                                         
36-BIT FIFO  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
tCLKL  
tCLKL  
WCLK  
1
2
2
1
tENS  
tENH  
WEN  
tPAFS  
tPAFS  
D - m words in FIFO(2)  
D-(m+1) words  
in FIFO(2)  
D - (m +1) words in FIFO(2)  
PAF  
[1:2]  
t
SKEW2(3)  
RCLK  
tENH  
tENS  
6723 drw29  
REN  
NOTES:  
1. m = PAF[1:2] offset.  
2. D = maximum FIFO depth.  
In IDT Standard mode: D = 524,288 for the IDT72T36135M.  
In FWFT mode: D = 524,289 for the IDT72T36135M.  
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF[1:2] will go HIGH (after one WCLK cycle plus tPAFS). If the time between  
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF[1:2] deassertion time may be delayed one extra WCLK cycle.  
4. PAF[1:2] is asserted and updated on the rising edge of WCLK only.  
5. Select this mode by setting PFM HIGH during Master Reset.  
Figure 22. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)  
tCLKH  
tCLKL  
WCLK  
tENS  
tENH  
WEN  
n words in FIFO(2)  
n + 1 words in FIFO(3)  
,
n
words in FIFO(2)  
n + 1 words in FIFO(3)  
SKEW2(4)  
,
n + 1 words in FIFO(2)  
n + 2 words in FIFO(3)  
,
PAE  
[1:2]  
tPAES  
tPAES  
t
1
2
1
2
RCLK  
tENS  
tENH  
6723 drw30  
REN  
NOTES:  
1. n = PAE[1:2] offset.  
2. For IDT Standard mode  
3. For FWFT mode.  
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE[1:2] will go HIGH (after one RCLK cycle plus tPAES). If the time between  
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE[1:2] deassertion may be delayed one extra RCLK cycle.  
5. PAE[1:2] is asserted and updated on the rising edge of WCLK only.  
6. Select this mode by setting PFM HIGH during Master Reset.  
7. RCS = LOW.  
Figure 23. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
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™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
tCLKH  
tCLKL  
WCLK  
tENS  
tENH  
WEN  
tPAFA  
D - m words  
in FIFO  
D - (m + 1) words  
in FIFO  
D - (m + 1) words in FIFO  
PAF[1:2]  
RCLK  
REN  
tPAFA  
tENS  
6723 drw31  
NOTES:  
1. m = PAF[1:2] offset.  
2. D = maximum FIFO Depth.  
In IDT Standard Mode: D = 524,288 for the IDT72T36135M.  
In FWFT Mode: D = 524,289 for the IDT72T36135M.  
3. PAF[1:2] is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.  
4. Select this mode by setting PFM LOW during Master Reset.  
5. RCS = LOW.  
Figure 24. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)  
tCLKH  
tCLKL  
WCLK  
tENS  
tENH  
WEN  
(2)  
tPAEA  
(2)  
n words in FIFO  
,
n words in FIFO  
,
(2)  
n + 1 words in FIFO  
n + 2 words in FIFO  
,
(3)  
PAE[1:2]  
RCLK  
REN  
(3)  
n + 1 words in FIFO  
n + 1 words in FIFO  
(3)  
t
PAE  
A
tENS  
6723 drw22  
NOTES:  
1. n = PAE[1:2] offset.  
2. For IDT Standard Mode.  
3. For FWFT Mode.  
4. PAE[1:2] is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.  
5. Select this mode by setting PFM LOW during Master Reset.  
6. RCS = LOW.  
Figure 25. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)  
FEBRUARY04,2009  
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IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
RCLK  
tENS  
tENH  
tA  
REN  
Qn  
FF[1:2]  
WR  
W0  
W1  
tFFA  
tFFA  
tFFA  
tCYH  
tCYC  
tDS  
tDH  
WD  
Dn  
WD+1  
6723 drw23  
NOTE:  
1. OE = LOW, WEN = LOW and RCS = LOW.  
Figure 26. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)  
1
2
RCLK  
tENS  
tEN  
H
REN  
tA  
tA  
Last Word  
W1  
W0  
Qn  
tREF  
tREF  
EF[1:2]  
tCYL  
tSKEW  
tCYH  
WR  
tCYC  
tDH  
tDH  
tDS  
tDS  
W0  
W1  
Dn  
6723 drw34  
NOTE:  
1. OE = LOW, WEN = LOW and RCS = LOW.  
Figure 27. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)  
FEBRUARY04,2009  
43  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
No Write  
1
WCLK  
WEN  
Dn  
2
DF+1  
DF  
tWFF  
tWFF  
FF[1:2]  
tCYC  
tSKEW  
tCYL  
tCYH  
RD  
tAA  
tAA  
Qn  
Last Word  
WX  
WX+1  
6723 drw35  
NOTE:  
1. OE = LOW, RCS = LOW and REN = LOW.  
2. Asynchronous Read is available in IDT Standard Mode only.  
Figure 28. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)  
WCLK  
WEN  
Dn  
tENS  
tDS  
tENH  
tDH  
W0  
tEFA  
EF[1:2]  
tEFA  
tRPE  
RD  
tCYH  
tAA  
Qn  
Last Word in Output Register  
W0  
6723 drw36  
NOTE:  
1. OE = LOW, REN = LOW and RCS = LOW.  
2. Asynchronous Read is available in IDT Standard Mode only.  
Figure 29. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)  
FEBRUARY04,2009  
44  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
tCYC  
tCYH  
tCY  
L
WR  
Dn  
tDH  
tDH  
tDS  
W
0
W1  
RD  
Qn  
tAA  
tAA  
W
1
W
0
Last Word in O/P Register  
tRPE  
tEFA  
tEFA  
EF[1:2]  
6723 drw37  
NOTES:  
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW  
2. Asynchronous Read is available in IDT Standard Mode only.  
Figure 30. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)  
tCYC  
tCYH  
tCYL  
WR  
Dn  
tDH  
t
DH  
tDS  
tDS  
W
y+1  
Wy  
tCYC  
tCYH  
tCYL  
RD  
Qn  
tAA  
tAA  
Wx  
Wx+1  
Wx+2  
tFFA  
tFFA  
FF[1:2]  
6723 drw38  
NOTES:  
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.  
2. Asynchronous Read is available in IDT Standard Mode only.  
Figure 31. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)  
FEBRUARY04,2009  
45  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
flagsshouldbegatedusinglogicalgatestoremovethepossibilityofclockskew  
betweenthetwodevice(s)outputs.  
Figure 32 demonstrates a width expansion using two IDT72T36135M  
devices. D0 -D35 fromeachdevice forma 72-bitwide inputbus andQ0-Q35  
fromeachdeviceforma72-bitwideoutputbus.Anywordwidthcanbeattained  
byaddingadditionalIDT72T36135Mdevices.  
OPTIONALCONFIGURATIONS  
WIDTH EXPANSION CONFIGURATION  
Wordwidthmaybeincreasedbyconnectingtogetherthecontrolsignalsof  
multipledevicesplususingexternalgatinglogic.Statusflagscanbegatedand  
detectedfromthegateoutput.TheEF[1:2],FF[1:2],PAE[1:2],andPAF[1:2]  
FULL FLAG/INPUT READY  
PROGRAMMABLE ALMOST FULL  
FIFO#1  
FIFO#1  
SERIAL CLOCK  
(SCLK)  
AND  
GATE  
GATE  
(1)  
(PAF)  
(FF/IR)  
GATE  
(1)  
AND  
GATE  
PARTIAL RESET (PRS)  
GATE  
(1)  
FIFO#2  
AND  
FIFO#2  
GATE  
MASTER RESET (MRS)  
FIRST WORD FALL THROUGH/  
SERIAL INPUT (FWFT/SI)  
FIFO#1  
FIFO#1  
AND  
GATE  
GATE  
(1)  
(PAE)  
AND  
(EF/OR)  
GATE  
(1)  
GATE  
RETRANSMIT (RT)  
FIFO#2  
AND  
GATE  
FIFO#2  
GATE  
(1)  
D
m+1 - D  
n
EMPTY FLAG/OUTPUT READY  
PROGRAMMABLE ALMOST  
EMPTY  
m + n  
m
n
D0 - Dm  
DATA IN  
READ CLOCK (RCLK)  
READ CHIP SELECT (RCS)  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN)  
LOAD (LD)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE)  
FULL FLAG/INPUT READY (FF/IR) #1  
FULL FLAG/INPUT READY (FF/IR)) #2  
GATE  
(1)  
#1  
FULL FLAG/INPUT READY (FF/IR)  
GATE  
(1)  
IDT  
72T36135M  
IDT  
72T36135M  
FULL FLAG/INPUT READY (FF/IR) #2  
PROGRAMMABLE ALMOST FULL (PAF) #1  
PROGRAMMABLE ALMOST FULL (PAF) #2  
AND  
GATE  
FIFO  
#2  
FIFO  
#1  
PROGRAMMABLE ALMOST FULL (PAF) #1  
PROGRAMMABLE ALMOST FULL (PAF) #2  
AND  
GATE  
EMPTY FLAG/OUTPUT READY (EF/OR) #1  
EMPTY FLAG/OUTPUT READY (EF/OR) #2  
GATE  
(1)  
EMPTY FLAG/OUTPUT READY (EF/OR) #1  
EMPTY FLAG/OUTPUT READY (EF/OR) #2  
GATE  
(1)  
(4)  
PROGRAMMABLE ALMOST EMPTY (PAE) #1  
PROGRAMMABLE ALMOST EMPTY (PAE) #2  
AND  
GATE  
(4)  
PROGRAMMABLE ALMOST EMPTY (PAE) #1  
PROGRAMMABLE ALMOST EMPTY (PAE) #2  
AND  
GATE  
m + n  
m
Qm+1 - Qn  
n
DATA OUT  
Q0 - Qm  
6723 drw39  
NOTES:  
1. An OR gate is used for FWFT mode, AND gate for IDT mode.  
2. Do not connect any output control signals directly together.  
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.  
4. PAE/PAF[1:2] optional, see section of external gating of output flags.  
5. Recommend IDT74LVC32A 2-Input Positive OR Gate. Recommend IDT74LVC08A 2-Input AND Gate.  
Figure 32. Block Diagram of 524,288 x 72 Width Expansion  
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)  
outputOR[1:2]andIR[1:2]pins.Twosets ofORgates areusedinthis mode  
TheIDT72T36135Mcaneasilybeadaptedtoapplicationsrequiringdepths toderiveafeedbacklooptotheRENandWENpinstoavoidwritingorreading  
greaterthanand524,288withan36-bitbuswidth.InFWFTmode,theFIFOs to/from a device when the device is not ready to accept data. The 2nd row of  
canbeconnectedinseries(thedataoutputsofoneFIFOconnectedtothedata ORgatestakeintheIRorORpin’sstatusandallowfordatatobewritten/read  
inputsofthenext)withnoexternallogicnecessary. Theresultingconfiguration tothe nextFIFOinthe chain. Ifthe IR orOR pins are low, this willenable the  
providesatotaldepthequivalenttothesumofthedepthsassociatedwitheach devicetoacceptwritesorreadsfromthenextdeviceinline.Tousethismode,  
singleFIFO. Figure33shows adepthexpansionusingtwoIDT72T36135M theFIFOdevice’sclockspeeddependsontheaddedpropdelayofthe“OR”  
devices.  
gatesandsetuptimebetweenthetwoFIFOdevices.Example,ifthe“OR”gates  
Fordepthexpansionmode option#1, “logicalORgates”needtobe used beingusedhaveacombined10nspropagationdelay,a1nsjitterbudget,and  
todrivetheactivelowinputWENandRENpinsrespectivelyfromtheactivelow 1nsclockskewmargin,12nsmustbetakenintoaccountduringeachclockcycle.  
FEBRUARY04,2009  
46  
IDT72T36135M 2.5V 18M-BIT TeraSync  
524,288 x 36  
                                                                                         
™ 36-BIT FIFO  
                                                                                         
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
Forinstance,a25MHzclockhasarounda40nsclockcycle. Fora45%-55%  
clockdutycycle,18nsaccountfor45%ofthedutycyclewhentheclockishigh.  
Thismeans,18ns–12ns=6nsofsetuptimefordatatobeavailableatthe2nd  
IDTFIFOwhichisfineconsideringthesetuptimeforthisFIFOisaround1.5ns.  
Designersmustleaveanadequatetimingwindowtoallowdatatobecaptured  
bythe2nd IDTFIFO. Pleasetakethisintoconsiderationwhenusingthisdepth  
expansionmodetoavoiddatameta-stabilityissues. Forbufferinggreaterthan  
18Mbitsathigherfrequencies,IDTrecommendsusingtheIDTSequentialFlow  
Controller(SFC). PleaseseeIDTFlow-ControlManagement(FCM)product  
websiteformoreinformationontheSFC.  
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs  
in the depth expansion configuration. The first word written to an empty  
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally  
appears at the outputs of the last FIFO in the chain – no read operation is  
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata  
wordappearsattheoutputsofoneFIFO,thatdevice'sOR[1:2]linegoesLOW,  
enabling a write to the next FIFO in line. OR gates are used to take in the  
considerationsofthenextFIFOinthechainsIRpinstatus.IftheIRpinsareLow,  
thiswillenablethedevicetoacceptwritesfromupstreamdevices.  
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty  
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent  
wordswrittentotheconfiguration.  
The first free location created by reading from a full depth expansion  
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally  
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone  
FIFOofthechain,thatFIFO'sIR[1:2]linegoesLOW,enablingthepreceding  
FIFO to write a word to fill it.  
Forafullexpansionconfiguration,theamountoftimeittakesforIR[1:2]ofthe  
firstFIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO  
is thesumofthedelays foreachindividualFIFOandthesumoftheORgate  
prop delays:  
(N – 1)*(3*transfer clock) + 2 TWCLK + 2 *OR prop delay  
where N is the number of FIFOs in the expansion and TWCLK is the WCLK  
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1  
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer  
clock,fortheIR[1:2]flag.  
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever  
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe  
endofthechainandfreelocations tothebeginningofthechain.  
Depth Expansion Option #2 is depicted in Figure 34, Depth Expansion  
Option#2. OnedevicewillbeactiveatatimebytogglingtheWCSpins. Data  
willbewrittenintoFIFOinPingPongfashion.FirstdataiswrittenintoFIFO#1,  
seconddataiswrittenintoFIFO#2,thirddataiswrittenintoFIFO#1,fourthdata  
iswrittenintoFIFO#2,andsoon. Datacanthenbereadoutinthesamemanner  
on the read side by toggling the RCS1 and RCS2.  
Foranemptyexpansionconfiguration,theamountoftimeittakesforOR[1:2]  
ofthelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's  
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays  
for each individual FIFO and the sum of the OR gate prop delays:  
(N – 1)*(4*transfer clock) + 3*TRCLK + 2 *OR prop delay  
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.  
Note that extra cycles should be added for the possibility that the tSKEW1  
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer  
clock,fortheOR[1:2]flag.  
FWFT/SI  
TRANSFER CLOCK  
FWFT/SI  
FWFT/SI  
WRITE CLOCK  
READ CLOCK  
WCLK  
WEN  
IR  
RCLK  
WCLK  
RCLK  
RCS  
REN  
READ CHIP SELECT  
READ ENABLE  
OR1  
OR2  
OR  
GATE  
OR  
GATE  
WRITE ENABLE  
INPUT READY  
WEN  
IR1  
IDT  
72T36135M  
OR  
GATE  
IDT  
72T36135M  
OR  
GATE  
REN  
RCS  
OE  
IR2  
OUTPUT READY  
OR  
OE  
OUTPUT ENABLE  
GND  
n
DATA OUT  
n
n
Qn  
DATA IN  
Dn  
Dn  
Qn  
6723 drw40  
Figure 33. Depth Expansion Option #1  
FF1  
EF1  
WCS1  
IDT  
RCS1  
36  
72T36135M #1  
36  
REN  
RCS2  
IDT  
72T36135M #2  
WEN  
EF2  
WCS2  
FF2  
6723 drw41  
Figure 34. Depth Expansion Option #2  
FEBRUARY04,2009  
47  
ORDERINGINFORMATION  
XXXXX  
X
XX  
X
X
X
Process /  
Temperature  
Range  
Device Type Power Speed Package  
BLANK  
I(1)  
Commercial (0° C to +70° C)  
Industrial (-40° C to +85° C)  
Green  
G
Plastic Ball Grid Array (PBGA, BB240-1)  
BB  
5
6
Commercial Only  
Commercial and Industrial  
Clock Cycle Time (tCLK  
Speed in Nanoseconds  
)
L
Low Power  
72T36135M 524,288 x 36 ⎯ 2.5V 18M-Bit High-Speed TeraSync™ FIFO  
6723 drw42  
NOTES:  
1. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order.  
2. Green parts are available. For specific speeds and packages please contact your sales office.  
DATASHEETDOCUMENTHISTORY  
09/01/2005  
02/28/2006  
05/29/2006  
02/04/2009  
pg. 1.  
pg. 10.  
pgs.10, 21, and 23.  
pg. 48.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
408-360-1753  
email:FIFOhelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
48  

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