72T40118L5BBI [IDT]
PBGA-208, Tray;型号: | 72T40118L5BBI |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | PBGA-208, Tray |
文件: | 总52页 (文件大小:498K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2.5VOLTHIGH-SPEEDTeraSync™DDR/SDRFIFO40-BITCONFIGURATION
16,384 x 40, 32,768 x 40,
65,536 x 40, 131,072 x 40
IDT72T4088, IDT72T4098
IDT72T40108, IDT72T40118
can default to one of four preselected offsets
FEATURES
• Dedicated serial clock input for serial programming of flag offsets
• User selectable input and output port bus sizing
-x40 in to x40 out
-x40 in to x20 out
-x40 in to x10 out
-x20 in to x40 out
-x10 in to x40 out
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Choose among the following memory organizations:
IDT72T4088
IDT72T4098
IDT72T40108
IDT72T40118
16,384 x 40
32,768 x 40
65,536 x 40
131,072 x 40
• Up to 250MHz operating frequency or 10Gbps throughput in SDR mode
• Up to 110MHz operating frequency or 10Gbps throughput in DDR mode
• Users selectable input port to output port data rates, 500Mb/s
Data Rate
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into High-Impedance state
• JTAG port, provided for Boundary Scan function
• 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
• User selectable HSTL or LVTTL I/Os
• Read Enable & Read Clock Echo outputs aid high speed operation
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write
Operations
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x40, x20, x10)
SREN SEN
SCLK
WCLK
WSDR
WEN
WCS
SI
SO
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
WRITE CONTROL
LOGIC
FLAG
LOGIC
FWFT
FSEL0
FSEL1
RAM ARRAY
16,384 x 40,
32,768 x 40
65,536 x 40
131,072 x 40
WRITE POINTER
READ POINTER
BM
IW
OW
BUS
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
RSDR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK
REN
RCS
TDI
Vref
HSTL I/0
CONTROL
EREN
OE
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HSTL
Q0 -Qn (x40, x20, x10)
ERCLK
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.TheTeraSyncisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2004
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5995/10
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINCONFIGURATIONS
A1 BALL PAD CORNER
A
V
CC
V
CC
D38
D39
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
GND
GND
GND
GND
Q1
Q0
Q3
Q2
Q5
Q4
Q7
Q6
Q9
V
DDQ
VDDQ
B
C
D
E
F
D35
D34
D36
D37
D32
TDI
HSTL GND
Q8
Q22
Q21
Q26
Q29
RT
Q23
V
CC
CC
V
V
CC
CC
GND
GND
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
Q20
Q27
Q24
Q25
D33
D31
TRST
TDO
V
CC
V
CC
V
V
DDQ
V
V
DDQ
V
V
V
DDQ
D30
GND
DDQ MARK
Q28
RCS
REN
TCK
WCLK
V
DDQ
DDQ
DDQ
TMS
FWFT
WCS
G
H
J
V
GND
GND
GND
PAF
OE
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDQ
RCLK
SI
V
DDQ
WEN
MRS
FF/IR
GND
GND
GND
GND
GND
GND
GND
V
DDQ
DDQ
SCLK
SEN
SREN
FSEL1 FSEL0 GND
V
V
K
L
PRS
IW
BM
V
V
V
CC
GND
GND
DDQ
SO
PAE
Q30
Q33
Q36
Q38
EREN
ERCLK
Q31
WSDR RSDR
OW
D29
D26
D18
CC
CC
VDDQ
M
N
P
R
T
EF/OR
V
DDQ
D27
D23
D24
D25
D28
D20
D21
D22
V
V
CC
CC
GND
GND
V
CC
V
V
CC
CC
V
CC
CC
GND
GND
V
V
DDQ
DDQ
V
DDQ
V
V
DDQ
DDQ
V
DDQ
Q32
Q35
Q11
Q10
Q34
Q37
GND
V
V
DDQ
V
DDQ
D14
D15
5
Q19
Q17
Q16
11
Q15
Q14
12
Q13
Q12
D19
D16
D17
D12
D13
D10
D11
GND
GND
GND
GND
Q39
V
CC
V
CC
V
REF
VDDQ
Q18
V
DDQ
1
2
3
4
6
7
8
9
10
13
14
15
16
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PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
2
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
deasserted. Data willbe readoutofthe FIFOonbothrisingandfallingedge
of RCLK when and REN is asserted.
Boththeinputandoutput portcanbeselectedforeither2.5V LVTTLorHSTL
operation. ThiscanbeachievedbytyingtheHSTLsignalLOWforLVTTLor
HIGHforHSTLvoltageoperation. WhenthereadportissetupforHSTLmode,
theReadChipSelect(RCS)inputalsohasthebenefitofdisablingthereadport
inputs,providingadditionalpowersavings.
DESCRIPTION
TheIDT72T4088/72T4098/72T40108/72T40118areexceptionallydeep,
extremelyhighspeed,CMOSFirst-In-First-Out(FIFO)memorieswiththeability
toreadandwritedataonbothrisingandfallingedgesofclock.Thedevicehas
aflexiblex40/x20/x10Bus-Matchingmodeandtheoptiontoselectsingleor
doubledataratesforinputandoutputports.TheseFIFOsofferseveralkeyuser
benefits:
Thereistheoptionofselectingdifferentdataratesontheinputandoutputports
ofthedevice.Thereareatotaloffourcombinationstochoosefrom,DoubleData
Rate toDouble Data Rate (DDRtoDDR), DDRtoSingle Data Rate (DDRto
SDR),SDRtoDDR,andSDRtoSDR.TheratescanbesetupusingtheWSDR
andRSDRpins.Forexample,tosetuptheinputtooutputcombinationofDDR
toSDR,WSDRwillbeHIGHandRSDRwillbeLOW.Readandwriteoperations
areinitiatedontherisingedgeofRCLKandWCLKrespectively,neveronthe
fallingedge.IfRENorWENisassertedafterarisingedgeofclock,noreador
writeoperationswillbepossibleonthefallingedgeofthatsamepulse.
AnOutputEnable(OE)inputisprovidedforhigh-impedancecontrolofthe
outputs. A read Chip Select (RCS) input is also provided for synchronous
enable/disableofthereadportcontrolinput,REN.TheRCSinputissynchro-
nizedtothereadclock,andalsoprovideshigh-impedancecontrolstotheQn
dataoutputs.WhenRCSisdisabled, RENwillbedisabledinternallyandthe
data outputs will be in High-Impedance. Unlike the Read Chip Select signal
however, OE is not synchronous to RCLK. Outputs are high-impedanced
shortlyafteradelaytimewhentheOEtransitionsfromLOWtoHIGH.
The Echo Read Enable (EREN) and Echo Read Clock (ERCLK) outputs
areusedtoprovidetightersynchronizationbetweenthedatabeingtransmitted
from the Qn outputs and the data being received by the input device. These
outputsignalsfromthereadportarerequiredforhigh-speeddatacommuni-
cations.Datareadfromthereadportisavailableontheoutputbuswithrespect
toERENandERCLK,whichis usefulwhendatais beingreadathigh-speed
operationswheresynchronizationisimportant.
ThefrequenciesofboththeRCLKandWCLKsignalsmayvaryfrom0tofMAX
withcompleteindependence.Therearenorestrictionsonthefrequencyofone
clockinputwithrespecttoanother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.Beawarethat
in Double Data Rate (DDR) mode only the IDTStandard mode is available.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto
thedataoutputlinesafterthreetransitionsofRCLK.Areadoperationdoesnot
have to be performed to access the first word written to the FIFO. However,
subsequentwords writtentotheFIFOdorequireaLOWonRENforaccess.
ThestateoftheFWFTinputduringMasterResetdeterminesthetimingmode
inuse.
• Flexible x40/x20/x10 Bus-Matching on both read and write ports
• Abilitytoreadandwrite onbothrisingandfallingedges ofa clock
• UserselectableSingleorDoubleDataRateofinputandoutputports
• AuserselectableMARKlocationforretransmit
• User selectable I/O structure for HSTL or LVTTL
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento
an empty FIFO to the time it can be read, is fixed and short.
• Highdensityofferingsupto5Mbit
• 10Gbpsthroughput
Bus-Matching Double Data Rate FIFOs are particularly appropriate for
network,video,telecommunications,datacommunicationsandotherapplica-
tionsthatrequirefastdatatransferonbothrisingandfallingedgesoftheclock.
Thisisagreatalternativetoincreasingdataratewithoutextendingthewidthof
thebusorthespeedofthedevice.Theyarealsoeffectiveinapplicationsthat
needtobufferlargeamountsofdataandmatchbusesofunequalsizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
whichcanassumeeithera40-bit,20-bit,ora10-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input.DatapresentontheDndatainputscanbewrittenintotheFIFO
on every rising and falling edge of WCLK when WEN is asserted and Write
SingleDataRate(WSDR)pinheldHIGH.Datacanbeselectedtowriteonly
ontherisingedgesofWCLKifWSDRisasserted.Toguaranteefunctionality
ofthedevice,WENmustbeacontrolledsignalandnottiedtoground.Thisis
importantbecauseWENmustbeHIGHduringthetimewhentheMasterReset
(MRS)pulse is LOW. Inaddition, the WSDR pinmustbe tiedHIGHorLOW.
Itis nota controlledsignalandcannotbe changedduringFIFOoperation.
WriteoperationscanbeselectedforeitherSingleorDoubleDataRatemode.
ForSingleDataRateoperation,writingintotheFIFOrequirestheWriteSingle
DataRate(WSDR)pintobeasserted.DatawillbewrittenintotheFIFOonthe
risingedge ofWCLKwhenthe Write Enable (WEN)is asserted. ForDouble
DataRateoperations,writingintotheFIFOrequiresWSDRtobedeasserted.
DatawillbewrittenintotheFIFOonbothrisingandfallingedgeofWCLKwhen
WENisasserted.
The output port is controlled by a Read Clock (RCLK) input and a Read
Enable(REN)input.DataisreadfromtheFIFOoneveryrisingandfallingedge
ofRCLKwhenRENisassertedandReadSingleDataRate(RSDR)pinheld
HIGH.DatacanbeselectedtoreadonlyontherisingedgesofRCLKifRSDR
isasserted.Toguaranteefunctionalityofthedevice,RENmustbeacontrolled
signalandnottiedtoground. This is importantbecause REN mustbe HIGH
duringthetimewhentheMasterReset(MRS)pulseis LOW.Inaddition,the
RSDRpinmustbetiedHIGHorLOW.Itisnotacontrolledsignalandcannot
be changed during FIFO operation.
ReadoperationscanbeselectedforeitherSingleorDoubleDataRatemode.
Similartothewriteoperations,readingfromtheFIFOinsingledataraterequires
theReadSingleDataRate(RSDR)pintobeasserted.Datawillbereadfrom
theFIFOontherisingedgeofRCLKwhentheReadEnable(REN)isasserted.
ForDoubleDataRateoperations,readingintotheFIFOrequiresRSDRtobe
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan
provide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs ofthe next). Noexternallogicis required.
TheseFIFOshavefourflagpins,EF/OR(EmptyFlagorOutputReady),FF/
IR (FullFlagorInputReady), PAE(ProgrammableAlmost-Emptyflag),and
PAF(ProgrammableAlmost-Fullflag).TheEFandFFfunctionsareselected
inIDTStandardmode.TheIRandORfunctionsareselectedinFWFTmode.
PAEandPAF are always available foruse, irrespective oftimingmode.
3
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
not WCLK. Similarly the PAF is asserted and updated on the rising edge of
WCLK only and not RCLK.
DESCRIPTION(CONTINUED)
PAEandPAFflagscanbeprogrammedindependentlytoswitchatanypoint
inmemory.Programmableoffsetsmarkthelocationwithintheinternalmemory
thatactivatesthePAEandPAFflagsandcanonlybeprogrammedserially.To
programtheoffsets,setSENactiveanddatacanbeloadedviatheSerialInput
(SI)pinattherisingedgeofSCLK.Toreadouttheoffsetregistersserially,set
SRENactiveanddatacanbereadoutviatheSerialOutput(SO)pinattherising
edgeofSCLK.Fourdefaultoffsetsettingsarealsoprovided,sothatPAEcan
bemarkedatapredefinednumberoflocationsfromtheemptyboundaryand
thePAFthresholdcanalsobemarkedatsimilarpredefinedvaluesfromthefull
boundary.ThedefaultoffsetvaluesaresetduringMasterResetbythestate
of the FSEL0 and FSEL1 pins.
DuringMasterReset(MRS),thefollowingeventsoccur:thereadandwrite
pointersaresettothefirstlocationoftheinternalFIFOmemory,theFWFTpin
selectsIDTStandardmodeorFWFTmode,thebuswidthconfigurationofthe
readandwriteportisdeterminedbythestateofIWandOW,andthedefaultoffset
valuesfortheprogrammableflagsareset.
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs,MARKandRT(Retransmit).IftheMARKinputisenabledwithrespect
totheRCLK,thememorylocationbeingreadatthepointwillbemarked.Any
subsequent retransmit operation (when RT goes LOW), will reset the read
pointertothis“marked”location.
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
previouslystated. These rates are:x40tox40, x40tox20,x40tox10, x20to
x40, and x10 to x40.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
AJTAGtestportis provided, here the FIFOhas fullyfunctionalboundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
BoundaryScanArchitecture.
TheDoubleDataRateFIFOhasthecapabilityofoperatingineitherLVTTL
orHSTLmode.HSTLmodecanbeselectedbyenablingtheHSTLpin.Both
inputandoutputportswilloperateineitherHSTLorLVTTLmode,butcannot
beselectedindependentofoneanother.
The Partial Reset (PRS) also sets the read and write pointers to the first
locationofthememory.However,thetimingmodeandthevaluesstoredinthe
programmableoffsetregistersbeforePartialResetremainunchanged.The
flagsareupdatedaccordingtothetimingmodeandoffsetsineffect.PRSisuseful
forresettingadeviceinmid-operation,whenreprogrammingprogrammable
flagswouldbeundesirable.
The IDT72T4088/72T4098/72T40108/72T40118 are fabricated using
IDT’shigh-speedsubmicronCMOStechnology.
The timing of thePAE andPAF flags are synchronous to RCLK and WCLK,
respectively.The PAE flag is asserted upon the rising edge of RCLK only and
4
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
WRITE CHIP SELECT (WCS)
IDT
READ CHIP SELECT (RCS)
72T4088
72T4098
72T40108
72T40118
WRITE SINGLE DATA RATE (WSDR)
READ SINGLE DATA RATE (RSDR)
(x40, x20, x10) DATA IN (D
0
- Dn)
(x40, x20, x10) DATA OUT (Q0 - Qn)
RCLK ECHO (ERCLK)
REN ECHO (EREN)
MARK
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
SERIAL READ ENABLE(SREN)
FIRST WORD FALL THROUGH (FWFT)
SERIAL INPUT (SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
SERIAL OUTPUT (SO)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
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OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x40
x40
x40
x20
x10
x40
x20
x10
x40
x40
NOTE:
1. Pin status during Master Reset.
TABLE 2 — DATA RATE-MATCHING CONFIGURATION MODES
WSDR
RSDR
Write Port Width
Read Port Width
H
H
L
L
H
L
H
L
DoubleDataRate
DoubleDataRate
SingleDataRate
SingleDataRate
DoubleDataRate
SingleDataRate
DoubleDataRate
SingleDataRate
NOTE:
1. Pin status during Master Reset.
2. Data Rate Matching can be used in conjunction with Bus-Matching modes.
5
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION
Symbol &
Name
I/OTYPE
Description
Pin No.
(1)
BM
Bus-Matching
LVTTL
INPUT
DuringMasterReset,this pinalongwithIWandOWselects thebus sizes forbothwriteandread
ports.
(K2)
D0-D39
DataInputs
HSTL-LVTTL Datainputsfora40-,20-,or10-bitbus.Whenin20-or10-bitmode,theunusedinputpinsareinadon’t
(See Pin No.
tablefordetails)
INPUT
carestate.ThedatabusissampledonbothrisingandfallingedgesofWCLKwhenWENisenabledand
DDR Mode is enabled or on the rising edges of WCLK only in SDR Mode.
EF/OR
(M14)
EmptyFlag/
OutputReady
HSTL-LVTTL Inthe IDTStandardmode, the EF functionis selected. EFindicates whetherornotthe FIFOmemory
OUTPUT is empty.InFWFTmode,theOR functionis selected.OR indicates whetherornotthereis validdata
availableattheoutputs.
ERCLK
(L16)
Echo Read
Clock
HSTL-LVTTL ReadClockEchooutput,mustbeequaltoorfasterthantheQndataoutputs.
OUTPUT
EREN
(K16)
Echo Read
Enable
HSTL-LVTTL ReadEnableEchooutput,usedinconjunctionwithERCLK.
OUTPUT
FF/IR
(H3)
Full Flag/
Input Ready
HSTL-LVTTL IntheIDTStandardmode,theFFfunctionisselected.FFindicateswhetherornottheFIFOmemoryis
OUTPUT empty.InFWFTmode,theIRfunctionis selected.IRindicates whetherornotthereis spaceavailable
forwritingtotheFIFOmemory.
FSEL0(1)
(J3)
FSEL1(1)
(J2)
FlagSelectBit0
Flag Select Bit 1
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL1willselectthedefaultoffsetvaluesfortheprogrammable
flagsPAE andPAF.Therearefourpossiblesettings available.
LVTTL
INPUT
DuringMasterReset, thisinputalongwithFSEL0willselectthedefaultoffsetvaluesfortheprogrammable
flags PAE and PAF. There are four possible settings available.
FWFT
(G2)
FirstWordFall
Through
LVTTL
INPUT
During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in
DDR mode. In SDR mode, the first word will always fall through on the rising edge.
(1)
HSTL
(B7)
HSTLSelect
LVTTL
INPUT
This inputpinis usedtoselectHSTLor2.5VLVTTLdeviceoperation.IfHSTLinputs arerequired,this
inputmustbetiedHIGH,otherwiseitmustbetiedLOWandcannottoggleduringoperation.
(1)
IW
InputWidth
LVTTL
INPUT
DuringMasterReset, this pinalongwithOWandBM, selects the bus widthofthe readandwrite port.
(K1)
MARK
(E14)
Mark Read
Pointerfor
Retransmit
HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit
INPUT
operationwillresetthereadpointertothisposition.Thereisanunlimitednumbertotimestosetthemark
location,butonlythemostrecentlocationmarkedwillbeacknowledged.
MRS
(J1)
MasterReset
HSTL-LVTTL MRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros.DuringMaster
INPUT
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,and
programmableflagdefaultsettings.
OE
OutputEnable
OutputWidth
HSTL-LVTTL WhenHIGH,dataoutputsQ0-Q39areinhighimpedance.WhenLOW,thedataoutputsQ0-Q39areenabled.
(G15)
INPUT
NootheroutputsareaffectedbyOE.
(1)
OW
(L3)
LVTTL
INPUT
DuringMasterReset, this pinalongwithIWandBM, selects the bus widthofthe readandwrite port.
PAE
(L15)
Programmable HSTL-LVTTL PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn,whichis
Almost-Empty
Flag
OUTPUT storedintheEmptyOffsetregister.PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthan
offsetn.
PAF
Programmable HSTL-LVTTL PAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstored
(G3)
Almost-FullFlag
PartialReset
DataOutputs
OUTPUT intheFullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthan
or equal to m.
PRS
(K3)
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros.DuringPartial
INPUT
Reset,theexistingmode(IDTstandardorFWFT)andprogrammableflagsettingsarenotaffected.
Q0-Q39
(See Pin No.
tablefordetails)
HSTL-LVTTL Dataoutputsfora40-,20-,or10-bitbus.Whenin20-or10-bitmode,theunusedoutputpinsshouldnot
OUTPUT beconnected.TheoutputdataisclockedonbothrisingandfallingedgesofRCLKwhenRENisenabled
and DDR Mode is enabled or on the rising edges of RCLK only in SDR Mode.
RCLK
(G16)
ReadClock
HSTL-LVTTL InputclockwhenusedinconjunctionwithRENforreadingdatafromtheFIFOmemoryandoutputregister.
INPUT
6
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
RCS
(F14)
ReadChipSelect HSTL-LVTTL RCSprovidessynchronousenable/disablecontrolofthereadportandHigh-Impedancecontrolofthe
INPUT
Qndataoutputs,synchronoustoRCLK.WhenusingRCStheOEpinmustbetiedLOW.DuringMaster
orPartialResetthe RCSinputis don’tcare,ifOEis LOWthedataoutputs willbeLow-Impedance
regardless ofRCS.
REN
(F16)
ReadEnable
HSTL-LVTTL WhenLOWandinDDRmode, RENalongwitharisingandfallingedgeofRCLKwillsenddatainFIFO
INPUT
memorytotheoutputregisterandreadthecurrentdatainoutputregister.InSDRmodedatawillonlybe
read on the rising edge of RCLK only.
(1)
RSDR
(L2)
ReadSingleData
Rate
LVTTL
INPUT
WhenLOW,thisinputpinsetsthereadporttoSingleDataClockmode.WhenHIGH,thereadportwilloperate
inDoubleDataClockmode.ThispinmustbetiedeitherHIGHorLOWandcannottoggleduringoperation.
RT
(F15)
Retransmit
HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializesthereadpointertothefirstlocationinmemory.EFflag
INPUT
issettoLOW(ORtoHIGHinFWFTmode).Thewritepointer,offsetregisters,andflagsettingsarenot
affected.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwillinitializetothemarklocation
when RT is asserted.
SCLK
(H15)
SerialClock
LVTTL
INPUT
ArisingedgeofSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovided
thatSENisenabled.ArisingedgeofSCLKwillalsoreaddataoutoftheoffsetregistersprovidedthatSREN
isenabled.
SEN
(J15)
SerialInput
Enable
HSTL-LVTTL SENusedinconjunctionwithSIandSCLKenablesserialloadingoftheprogrammableflagoffsets.
INPUT
SREN
(J16)
Serial Read
Enable
HSTL-LVTTL SRENusedinconjunctionwithSOandSCLKenablesserialreadingoftheprogrammableflagoffsets.
INPUT
SI
(H16)
SerialInput
SerialOutput
JTAGClock
HSTL-LVTTL Thisinputpinisusedtoloadserialdataintotheprogrammableflagoffsets.UsedinconjunctionwithSEN
INPUT
and SCLK.
SO
(K15)
HSTL-LVTTL Thisoutputpinisusedtoreaddatafromtheprogrammableflagoffsets.UsedinconjunctionwithSREN
OUTPUT and SCLK.
(2)
TCK
HSTL-LVTTL ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
(F1)
INPUT
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds
tobe tiedtoGND.
(2)
TDI
JTAGTestData HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
(E2)
Input
INPUT
testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister
andBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
(F3)
Output
OUTPUT testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,
IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whileinSHIFT-
DRandSHIFT-IRcontrollerstates.
TMS(2)
(F2)
JTAGMode
Select
HSTL-LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
INPUT
thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
(E3)
JTAGReset
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
INPUT
automaticallyresetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHfor
fiveTCKcycles.IftheTAPcontrolleris notproperlyresetthentheFIFOoutputs willalways beinhigh-
impedance.IftheJTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetied
withMRStoensureproperFIFOoperation.IftheJTAGfunctionisnotusedthenthissignalneedstobe
tiedtoGND.Aninternalpull-upresistorforcesTRSTHIGHifleftunconnected.
WCLK
(G1)
WriteClock
HSTL-LVTTL InputclockwhenusedinconjunctionwithWENforwritingdataintotheFIFOmemory.
INPUT
WCS
(H2)
WriteChipSelect HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WEN
(H1)
WriteEnable
HSTL-LVTTL WhenLOWandinDDRmode,WENalongwitharisingandfallingedgeofWCLKwillwritedataintothe
INPUT FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.
7
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol &
Pin No.
WSDR
(L1)
Name
I/OTYPE
Description
(1)
WriteSingleData
Rate
LVTTL
INPUT
WhenLOW,thisinputpinsetsthewriteporttoSingleDataClockmode.WhenHIGH,thewriteportwill
operate inDouble Data Clockmode. This pinmustbe tiedeitherHIGHorLOWandcannottoggle
duringoperation.
VCC
(See below)
+2.5VSupply
INPUT
INPUT
INPUT
INPUT
There are Vcc supply inputs and must be connected to the 2.5V supply rail.
VDDQ
(See below)
O/PRailVoltage
Core Ground Pin
Thispinshouldbetiedtothedesiredvoltagerailforprovidingpowertotheoutputdrivers.Nominally1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
GND
(See below)
These are Ground pins are for the core device and must be connected to the GND rail.
Vref
(T3)
Reference
Voltage
This is aVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedinthe
RecommendedDCOperatingConditionssection.ThisprovidesthereferencevoltagewhenusingHSTL
classinputs.IfHSTLclassinputsarenotbeingused,thispinmustbeconnectedtoGND.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 25-28 and Figures 5-7.
PIN NUMBER TABLE
Symbol
Name
I/OTYPE
Pin Number
D0-39
DataInputs
HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7,
INPUT
D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3, D20-N2, D21-P2, D22-R2,
D23-N1, D24-P1, D25-R1, D26-N3, D(27-29)-M(1-3), D30-E1, D(31-33)-D(3-1), D34-C1,
D(35,36)-B(1,2), D37-C2, D38-A3, D39-B3
Q0-39
DataOutputs
HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14
OUTPUT Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10,
Q(20,21)-C(14,15), Q(22,23)-B(15,16), Q24-C16, Q(25-27)-D(16-14), Q(28,29)-E(16,15),
Q(30,31)-M(15,16), Q(32-34)- N(14-16), Q(35-37)-P(14-16), Q(38,39)-R(15,16)
VCC
+2.5VSupply
INPUT
INPUT
A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2)
VDDQ
O/PRailVoltage
A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13),
P(10-13), T(15,16)
GND
GroundPin
INPUT
A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9),
P(4,8,9), R(8,9), T(8,9)
8
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
–0.5to+3.6(2)
Unit
Symbol
Parameter(1)
Conditions
Max.
Unit
VTERM
TerminalVoltage
with respect to GND
V
(2,3)
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
(1,2)
COUT
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VCC
Parameter
Min.
2.375
2.375
0
Typ.
2.5
2.5
0
Max.
2.625
2.625
0
Unit
V
SupplyVoltage
VDDQ
GND
VIH
OutputRailVoltageforI/Os
SupplyVoltage
V
V
InputHighVoltage
LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
—
—
V
V
V
VIL
InputLowVoltage
LVTTL
eHSTL
HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF
(HSTL only)
VoltageReferenceInput eHSTL
HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
TA
NOTE:
-40
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
ILI
Parameter
Min.
–10
–10
Max.
10
Unit
InputLeakageCurrent
OutputLeakageCurrent
µA
µA
V
V
V
ILO
10
(5)
VOH
OutputLogic“1”Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
OutputLogic“0”Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
20
60
60
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
10
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 0.6mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 38mA + (0.7mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)
3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs
With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x 2N)/2000
fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.
tA = 25°C, CL = capacitive load (pf)
4. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
5. Outputs are not 3.3V tolerant.
9
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Commercial
IDT72T4088L4
IDT72T4098L4
Commercial
IDT72T4088L5
IDT72T4098L5
Com’l & Ind’l(2)
Commercial
IDT72T4088L6-7 IDT72T4088L10
IDT72T4098L6-7 IDT72T4098L10
IDT72T40108L4 IDT72T40108L5 IDT72T40108L6-7 IDT72T40108L10
IDT72T40118L4 IDT72T40118L5 IDT72T40118L6-7 IDT72T40118L10
Symbol
fS1
Parameter
Clock Cycle Frequency SDR
Clock Cycle Frequency DDR
DataAccessTime
Min.
—
—
0.6
0.6
4
Max.
250
110
3.2
3.2
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
—
0.6
0.6
5
Max.
200
100
3.6
3.6
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
—
0.6
0.6
6.7
13
2.8
6.0
2.8
6.0
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
45
15
5
Max.
150
75
Min.
—
—
0.6
0.6
10
20
4.5
9.5
4.5
9.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
Max.
100
50
Unit
MHz
MHz
ns
fS2
tA
3.8
3.8
—
—
—
—
—
—
—
—
—
—
—
—
10
4.5
4.5
—
—
—
—
—
—
—
—
—
—
—
—
10
tASO
DataAccessSerialOutputTime
Clock Cycle Time SDR
Clock Cycle Time DDR
Clock High Time SDR
Clock High Time DDR
Clock Low Time SDR
Clock Low Time DDR
DataSetupTime
ns
tCLK1
tCLK2
tCLKH1
tCLKH2
tCLKL1
tCLKL2
tDS
ns
9.1
1.8
4.0
1.8
4.0
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
10
2.3
4.5
2.3
4.5
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
ns
ns
ns
ns
ns
ns
tDH
DataHoldTime
ns
tENS
EnableSetupTime
ns
tENH
EnableHoldTime
ns
tWCSS
tWCSH
fC
WCSsetuptime
WCSholdtime
Clock Cycle Frequency (SCLK)
ns
ns
MHz
ns
tSCLK
tSCKH
tSCKL
tSDS
Serial Clock Cycle
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
15
Serial Clock High
ns
Serial Clock Low
45
ns
SerialDataInSetup
Serial Data In Hold
15
ns
tSDH
5
ns
tSENS
tSENH
tRS
SerialEnableSetup
5
5
5
5
ns
SerialEnableHold
ResetPulseWidth(3)
5
5
5
5
ns
30
30
15
4
30
15
4
30
15
4
ns
tRSS
ResetSetupTime
15
ns
tHRSS
tRSR
HSTLResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
4
µs
ns
10
10
—
0
10
—
0
10
—
0
tRSF
—
0
ns
(4)
tOLZ
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
—
3.2
3.2
3.2
3.2
3.2
3.2
3.6
3.2
3.2
3.2
—
—
—
—
3.6
3.6
3.6
3.6
3.6
3.6
4
—
3.8
3.8
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
—
—
4.5
4.5
4.5
4.5
4.5
4.5
5
ns
tOE
—
—
—
—
—
—
—
—
—
—
3.5
3.5
4
—
—
—
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
—
—
7
ns
(4)
tOHZ
OutputEnabletoOutputinHighZ
ns
tWFF
tREF
Write Clock to FF or IR
Read Clock to EF or OR
WriteClocktoProgrammableAlmost-FullFlag
ReadClocktoProgrammableAlmost-EmptyFlag
RCLK to Echo RCLK output
ns
ns
tPAFS
tPAES
tERCLK
tCLKEN
tRCSLZ
tRCSHZ
tSKEW1
tSKEW2
tSKEW3
NOTES:
ns
ns
ns
RCLK to Echo REN output
RCLK to Active from High-Z
3.6
3.6
3.6
—
—
—
4.5
4.5
4.5
—
—
—
ns
ns
(4)
RCLK to High-Z
ns
Skew time between RCLK and WCLK for EF/OR and FF/IR
SkewtimebetweenRCLK&WCLKforEF/OR &FF/IRinDDRmode
Skew time between RCLK and WCLK for PAE and PAF
ns
4
5
7
ns
5
6
8
ns
1. All AC timings apply to both IDT Standard mode and First Word Fall Through mode.
2. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
10
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
VDDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
50Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.75V
Z0 = 50Ω
I/O
0.75V
10pF
NOTE:
5995 drw04
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9V
0.9V
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
Capacitance (pF)
200
5995 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5VLVTTL
2.5V AC TEST CONDITIONS
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
1.25V
1.25V
NOTE:
1. For LVTTL VCC = VDDQ.
11
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
V
IH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
2
CC
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
CC
Output
Normally
HIGH
VCC
100mV
V
2
2
5995 drw04b
NOTES:
1. REN is HIGH.
2. RCS is LOW.
READ CHIP SELECT ENABLE & DISABLE TIMING
V
IH
tENH
RCS
VIL
tENS
RCLK
tRCSHZ
tRCSLZ
Output
Normally
LOW
V
2
CC
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
CC
Output
Normally
HIGH
VCC
100mV
V
2
2
5995 drw04c
NOTES:
1. REN is HIGH.
2. OE is LOW.
12
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IftheFIFOisfull,thefirstreadoperationwillcauseFFtogoHIGH.Subsequent
FUNCTIONALDESCRIPTION
readoperationswillcausePAFtogoHIGHattheconditionsdescribedinTable
4Iffurtherreadoperationsoccur,withoutwriteoperations,PAEwillgoLOW
when there are n words in the FIFO, where n is the empty offset value.
ContinuingreadoperationswillcausetheFIFOtobecomeempty.Thenthelast
wordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.IDTStandardmodeisavailablewhenthedeviceis
configuredinbothSingleDataRateandDoubleDataRatemode.
RelevanttimingdiagramsforIDTStandardmodecanbefoundinFigure10,
11, 12, 13, 14, 15, 16, 17, 18 and 23.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T4088/72T4098/72T40108/72T40118 support two different
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT)mode.Theselectionofwhichmodewilloperateisdeterminedduring
MasterReset,bythestateoftheFWFTinput.
DuringMasterReset,iftheFWFTpinisLOW,thenIDTStandardmodewill
beselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornotthere
are anywords presentinthe FIFO. Italsouses the FullFlagfunction(FF) to
indicatewhetherornottheFIFOhasanyfreespaceforwriting.InIDTStandard
mode,everywordreadfromtheFIFO,includingthefirst,mustberequested
using the Read Enable (REN) and RCLK.
If the FWFT pin is HIGH during Master Reset, then FWFT mode will be
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whetherornottheFIFOhasanyfreespaceforwriting.IntheFWFTmode,the
firstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,applyingREN=LOWisnotnecessary.However,subsequentwords
must be accessed using the Read Enable (REN) and RCLK.
Varioussignals,inbothinputsandoutputsoperatedifferentlydependingon
whichtimingmodeisineffect.
FIRST WORD FALL THROUGH MODE (FWFT)
Inthismode,thestatusflagsOR,IR,PAE,andPAFoperateinthemanner
outlinedinTable 5. Towrite data intotothe FIFO, WEN mustbe LOW. Data
presentedtothe DATAINlines willbe clockedintothe FIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern+2wordshavebeenloadedintotheFIFO,wherenistheempty
offset value. The default setting for these values are listed in Table 3. This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
ContinuingtowritedataintotheFIFOwithoutperformingreadoperationswill
causetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifnoreads
areperformed,thePAFwillgoLOWafter(16,385-m)writesfortheIDT72T4088,
(32,769-m)writesfortheIDT72T4098,(65,537-m)writesfortheIDT72T40108
and(131,073-m)writes fortheIDT72T40118.Theoffset“m”is thefulloffset
value.ThedefaultsettingforthesevaluesarelistedinTable3.Thisparameteris
alsouserprogrammable.SeethesectiononProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theInputReady(IR)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,IRwillgoLOWafterDwrites
to the FIFO. D = 16,385 writes for the IDT72T4088, 32,769 writes for the
IDT72T4098,65,537writesfortheIDT72T40108and131,073writesforthe
IDT72T40118,respectively.NotethattheadditionalwordinFWFTmodeisdue
tothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcauseIRtogoHIGH.Subsequent
readoperationswillcausePAFtogoHIGHattheconditionsdescribedinTable
5.Iffurtherreadoperationsoccur,withoutwriteoperations,PAEwillgoLOW
when there are n words in the FIFO, where n is the empty offset value.
ContinuingreadoperationswillcausetheFIFOtobecomeempty.Thenthelast
wordhasbeenreadfromtheFIFO,theORwillgoHIGHinhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
IDT STANDARD MODE
Inthismode,thestatusflagsFF,PAF,PAE,andEFoperateinthemanner
outlinedinTable4.TowritedataintotheFIFO,WriteEnable(WEN)mustbe
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern+1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarelistedinTable3.Thisparameter
isalsouserprogrammable.SeesectiononProgrammableFlagOffsetLoading.
ContinuingtowritedataintotheFIFOwithoutperformingreadoperationswill
causetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifnoreads
areperformed,thePAFwillgoLOWafter(16,384-m)writesfortheIDT72T4088,
(32,768-m)writesfortheIDT72T4098,(65,536-m)writesfortheIDT72T40108
and(131,072-m)writes fortheIDT72T40118.Theoffset“m”is thefulloffset
value.ThedefaultsettingforthesevaluesarelistedinTable3.Thisparameter
is also user programmable. See the section on Programmable Flag Offset
Loading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 16,384 writes for the IDT72T4088, 32,768 writes for the
IDT72T4098,65,536writesfortheIDT72T40108and131,072writesforthe
IDT72T40118,respectively.
WhenconfiguredinFWFTmode,theORflagoutputistripleregister-buffered
andtheIRflagoutputisdoubleregister-buffered.FWFTmodeisonlyavailable
whenthe device is configuredinSingle Data Rate mode.
RelevanttimingdiagramsforIDTStandardmodecanbefoundinFigure19,
20, 21, 22 and 24.
13
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
loaddatafromtheSIinputintotheoffsetregisters.SCLKrunsatanominalspeed
of10MHzatthemaximum.Theprogrammingsequencestartswithonebitfor
eachSCLKrisingedge,startingwiththeEmptyOffsetLSBandendingwiththe
Full Offset MSB. The total number of bits per device is listed in Figure 3,
ProgrammableFlagOffsetProgrammingSequence. SeeFigure25,Loading
ofProgrammableFlagRegisters,forthetimingdiagramforthismode.ThePAE
andPAFcanshowavalidstatusonlyafterthecompletesetofbits(foralloffset
registers)hasbeenentered.Theregisterscanbereprogrammedaslongas
thecompletesetofnewoffsetbitsisentered.
TABLE 3 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72T4088, 72T4098, 72T40108, 72T40118
FSEL1
FSEL0
Offsets n,m
H
L
H
L
H
H
L
L
255
127
63
7
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Similartoloadingoffsetvalues,setSRENLOWand
therisingedgeofSCLKwillsenddatafromtheoffsetregistersouttotheSOoutput
port.Wheninitializingareadtotheoffsetregisters,datawillbereadstartingfrom
thefirstlocationintheregister,regardlessofwhereitwaslastread.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summarizes
thecontrolpinsandsequenceforprogrammingoffsetregistersandreadingand
writingintotheFIFO.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T4088/
72T4098/72T40108/72T40118haveinternalregistersfortheseoffsets.There
arefourselectabledefaultoffsetvaluesduringMasterReset.Theseoffsetvalues
areshowninTable3.Theoffsetvaluescanalsobeprogrammedseriallyinto
theFIFO.Toloadoffsetvalues,setSENLOWandtherisingedgeofSCLKwill
The offset registers may be programmed (and reprogrammed) any time
after Master Reset. Valid programming ranges are from 0 to D-1.
TABLE 4 STATUS FLAGS FOR IDT STANDARD MODE
IDT72T4098
IDT72T40108
FF PAF PAE EF
IDT72T4088
IDT72T40118
0
0
0
0
H
H
H
H
L
H
H
H
L
L
L
L
1 to n (1)
1 to n (1)
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
H
(8,193) to (16,384-(m+1)) (16,385) to (32,768-(m+1)) (32,769) to (65,536-(m+1)) (65,537) to (131,072-(m+1))
(16,384-m) to 16,383
16,384
(32,768-m) to 32,767
32,768
(65,536-m) to 65,535
65,536
(131,072-m) to 131,071
131,072
H
H
L
NOTE:
1. See table 3 for values for n, m.
TABLE 5 STATUS FLAGS FOR FWFT MODE
IDT72T4098
IDT72T4088
IDT72T40108
IR PAF PAE OR
IDT72T40118
0
1 to n+1 (1)
0
0
0
L
L
L
L
H
H
H
H
L
L
L
H
L
L
L
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
Number of
Words in
FIFO
H
H
(8,194) to (16,385-(m+1)) (16,386) to (32,769-(m+1)) (32,770) to (65,537-(m+1)) (65,538) to (131,073-(m+1))
(16,385-m) to 16,384
16,385
(32,769-m) to 32,768
32,769
(65,537-m) to 65,536
65,537
(131,073-m) to 131,072
131,073
H
L
L
5995 drw05
NOTE:
1. See table 3 for values for n, m.
2. FWFT mode available only in Single Data Rate mode.
14
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088
IDT72T4098
IDT72T40108
IDT72T40118
SCLK
WSDR RSDR
X X
WEN
REN
SEN
SREN
WCLK RCLK
Serial write to registers:
In SDR Mode
Serial write to registers:
X
X
1
1
0
1
In DDR Mode
28 bits for the IDT72T4088
30 bits for the IDT72T4098
32 bits for the IDT72T40108
34 bits for the IDT72T40118
26 bits for the IDT72T4088
28 bits for the IDT72T4098
30 bits for the IDT72T40108
32 bits for the IDT 72T40118
1 bit for each rising SCLK edge 1 bit for each rising SCLK edge
Starting with Empty Offset
(LSB) Ending with Full Offset
(MSB)
Starting with Empty Offset
(LSB) Ending with Full Offset
(MSB)
Serial read from registers:
In SDR Mode
Serial read from registers:
In DDR Mode
X
X
1
1
1
0
X
X
28 bits for the IDT72T4088
30 bits for the IDT72T4098
26 bits for the IDT72T4088
28 bits for the IDT72T4098
32 bits for the IDT72T40108
34 bits for the IDT72T40118
30 bits for the IDT72T40108
32 bits for the IDT72T40118
1 bit for each rising SCLK edge 1 bit for each rising SCLK edge
Starting with Empty Offset
(LSB) Ending with Full Offset
(MSB)
Starting with Empty Offset
(LSB) Ending with Full Offset
(MSB)
1
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Write Memory (DDR)
Write Memory (SDR)
Read Memory (DDR)
Read Memory (SDR)
X
X
X
X
1
1
X
X
X
X
X
No Operation
5995 drw06
NOTES:
1. The programming sequence applies to both IDT Standard and FWFT modes.
2. When the input or output ports are in DDR mode, the depth is reduced by half but the overall density remains the same. For example, the IDT72T4088 in SDR mode is
16,384 x 40 = 655,360, in DDR mode the configuration becomes 8,192 x 80 = 655,360. In both cases, the total density are the same.
Figure 3. Programmable Flag Offset Programming Sequence
15
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RETRANSMIT FROM MARK OPERATION
23,RetransmitfromMarkinDoubleDataRateMode,fortherelevanttiming
The Retransmit from Mark feature allows FIFO data to be read repeatedly diagram.
starting at a user-selected position. The FIFO is first put into retransmit mode
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
that will “mark” a beginning word and also set a pointer that will prevent edge when the MARK input is HIGH and OR is LOW. The rising RCLK edge
ongoing FIFO write operations from over-writing retransmit data. The retrans- marks the data present in the FIFO output register as the first retransmit data.
mit data can be read repeatedly any number of times from the “marked” The data is marked in pairs. The FIFO remains in retransmit mode until a
position. The FIFO can be taken out of retransmit mode at any time to allow rising RCLK edge occurs while MARK is LOW.
normal device operation. The “mark” position can be selected any number of
times, each selection over-writing the previous mark location.
Once a marked location has been set, a retransmit can be initiated by a
rising RCLK edge while the Retransmit input (RT) is LOW. REN must be
In Double Data Rate, data is always marked in pairs. That is, the unit of data HIGH (reads disabled) before bringing RT LOW. The device indicates the
read on the rising and falling edge of WCLK. If the data marked was read on start of retransmit setup by setting OR HIGH, preventing read operations.
thefallingedgeofRCLK, thenthemarkeddatawillbetheunitofdataread from
When OR goes LOW, retransmit setup is complete and on the next rising
the rising and falling edge of that particular RCLK edge. Refer to Figure 23, RCLK edge (RT goes HIGH), the contents of the first retransmit location are
Retransmit from Mark in Double Data Rate Mode, for the timing diagram in loaded onto the output register. Since FWFTmode is selected, the first word
this mode. Retransmit operation is available in both IDT standard and FWFT appears on the outputs regardless of REN, a LOW on REN is not required for
modes.
the first word. Reading all subsequent words requires a LOW on REN to
During IDT standard mode the FIFO is put into retransmit mode by a Low- enable the rising RCLK edge. See Figure 24, Retransmit from Mark (FWFT
to-High transition on RCLK when the MARK input is HIGH and EF is HIGH. mode) for the relevant timing diagram.
The rising RCLK edge marks the data present in the FIFO output register as
Before a retransmit can be performed, there must be at least 1280 bits
the first retransmit data. Again, the data is marked in pairs. Thus if the data (or 160 bytes) of data between the write pointer and mark location.
marked was read on the falling edge of RCLK, the first part of retransmit will That is, 40 bits x32 for the x40 mode, 20 bits x64 for the x20 mode, and 10 bits
read out the data read on the rising edge of RCLK, followed by the data on the x128 for the x10 mode. Also, once the Mark is set, the write pointer will not
falling edge (the marked data). The FIFO remains in retransmit mode until a increment past the marked location, preventing overwrites of retransmit data.
rising edge on RCLK occurs while MARK is LOW.
Once a marked location has been set, a retransmit can be initiated by a HSTL/LVTTL I/O
rising edge on RCLK while the Retransmit input (RT) is LOW. REN must be
This device supports both LVTTL and HSTL logic levels on the input and
HIGH (reads disabled) before bringing RT LOW. The device indicates the start outputsignals.IfLVTTLisdesired,aLOWontheHSTLpinwillsettheinputs
of retransmit setup by setting EF LOW, also preventing reads. WhenEF goes andoutputstoLVTTLmode.IfHSTLisdesired,aHIGHontheHSTLpinwill
HIGH, retransmit setup is complete and read operations may begin starting settheinputsandoutputstoHSTLmode.VREFistheinputvoltagereference
with the first unit of data at the MARK location. Since IDT standard mode is usedinHSTLmode.TypicallyalogicHIGHinHSTLwouldbeVref+0.2Vand
selected, every word read including the first “marked” word following a re- alogicLOWwouldbeVREF–0.2V.Table6illustrateswhichpinsareandare
transmit setup requires a LOW on REN.
notassociatedwiththisfeature.Notethatall“StaticPins”mustbetiedtoVccor
Note,writeoperationsmaycontinueasnormalduringallretransmitfunctions, GND. These pins are LVTTL only and are purely device configuration pins.
howeverwriteoperationstothe“marked”locationwillbeprevented.SeeFigure
TABLE 6 — I/O CONFIGURATION
HSTL SELECT
STATIC PINS
HIGH = HSTL
LOW = LVTTL
LVTTL ONLY
Write Port
Read Port
Signal Pins
Static Pins
Dn (I/P)
Qn (O/P)
RCLK (I/P)
REN (I/P)
RCS (I/P)
MARK (I/P)
OE (I/P)
EF/OR (O/P)
PAF (O/P)
SCLK (I/P)
SI (I/P)
TRST (I/P)
IW (I/P)
OW (I/P)
BM ((I/P)
HSTL (I/P)
FSEL1 (I/P)
FSEL0 (I/P)
FWFT (I/P)
WSDR (I/P)
RSDR (I/P)
WCLK (I/P)
WEN (I/P)
WCS (I/P)
TDI (I/P)
PAE (O/P)
SO (O/P)
MRS (I/P)
PRS (I/P)
TCK (I/P)
TMS (I/P)
TDO (O/P)
SEN (I/P)
SREN (I/P)
FF/IR (O/P)
ERCLK (O/P)
EREN (O/P)
RT (I/P)
16
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If FWFT mode has been selected, the OR flag will go HIGH on the rising
SIGNAL DESCRIPTION
edge of RCLK that retransmit was initiated. OR will return LOW on the next
rising edge of RCLK, which signifies that retransmit setup is complete. Under
FWFT mode, the contents in the marked memory location will be loaded onto
the output register on the next rising edge of RCLK.To access all subsequent
data, a read operation will be required.
Subsequent retransmit operations may be performed, each time the read
pointer returning to the “marked” location. See Figure 24, Retransmit from
Mark (FWFT Mode) for the relevant timing diagram.
INPUTS:
DATA IN (D0 – Dn)
(D0 – D39) are data inputs for the 40-bit wide data, (D0 – D19) are data
inputs for the 20-bit wide data, or (D0 – D9) are data inputs for 10-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever theMRS input is taken to a LOW
state. Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
of the RAM array. PAE will go LOW and PAF will go HIGH.
If FWFT is LOW during Master Reset then IDT Standard mode along with
EF and FF are selected. EF will go LOW and FF will go HIGH, If FWFT is
HIGH, then the First Word Fall Through (FWFT) mode, along with IR and OR
are selected. OR will go HIGH and IR will go LOW.
All control settings such as OW, IW, BM, WSDR, RSDR, FSEL0 and FSEL1
are defined during the Master Reset cycle.
During a Master Reset the output register is initialized to all zeros. A Master
Reset is required after power up before a write operation can take place. MRS
is asynchronous.
MARK
The MARK input is used to select Retransmit mode of operation. On a rising
edge of RCLK while MARK is HIGH will mark the memory location of the data
currently present on the output register, in addition placing the device in
retransmit mode. Note, there must be a minimum of 1280 bits (or 160 bytes) of
data between the write pointer and mark location. That is, 40 bits x32 for the
x40 mode, 20 bits x64 for the x20 mode, and 10 bits x128 for the x10 mode.
Also, once the MARK is set, the write pointer will not increment past the
“marked” location until the MARK is deasserted. This prevents “overwriting” of
retransmit data.
The MARK input must remain HIGH during the whole period of retransmit
mode, a rising edge of RCLK while MARK is LOW will take the device out of
retransmit mode and into normal mode. Any number of MARK locations can
be set during FIFO operation, only the last marked location taking effect. Once
a mark location has been set the write pointer cannot be incremented past this
marked location. During retransmit mode write operations to the device may
continue without hindrance.
See Figure 8, Master Reset Timing, for the relevant timing diagram.
PARTIALRESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array. PAE goes LOW and PAF goes
HIGH.
FIRST WORD FALL THROUGH (FWFT)
Whichever mode was active at the time of Partial Reset will remain active
after Partial Reset. If IDT Standard Mode is active, then FF will go HIGH and
EF will go LOW. If the First Word FallThrough mode is active, thenOR will go
HIGH and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain un-
changed. The output register is initialized to all zeroes. PRS is asynchronous.
Partial Reset is useful for resetting the read and write pointers to zero without
affectingthevaluesoftheprogrammableflagoffsetsandthetimingmodeofthe
FIFO.
During Master Reset, the state of the FWFT input determines whether the
device will operate in IDT Standard mode or First Word Fall Through (FWFT)
mode.
If, at the time of Master Reset, FWFTis LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the outputs (Qn) to be read. It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn after
three RCLK rising edges, bringing REN LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK. Note that
FWFT mode can only be used when the device is configured to Single Data
Rate (SDR) mode.
See Figure 9, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
The Retransmit (RT) input is used in conjunction with the MARK input.
Together they provide a means by which data previously read out of the FIFO
can be reread any number of times. When the retransmit operation is selected
(i.e. after data has been marked), a rising edge on RCLK while RT is LOW will
reset the read pointer back to the memory location set by the user via the
MARK input.
If IDT Standard mode has been selected, the EF flag will go LOW on the
rising edge of RCLK that retransmit was initiated (i.e. rising edge of RCLK
while RT is LOW). EF will go back to HIGH on the next rising edge of RCLK,
which signifies that retransmit setup is complete. The next read operation will
access data from the “marked” memory location.
Subsequent retransmit operations may be performed, each time the read
pointer returning to the “marked” location. See Figure 23, Retransmit from
Mark in Double Data Rate Mode (IDT Standard Mode) for the relevant timing
diagram.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising and/or falling edge of the WCLK input.
If the Write Single Data Rate (WSDR) pin is selected, data will be written only
on the rising edge of WCLK, provided that WEN and WCS are LOW. If the
WSDR is not selected, data will be written on both the rising and falling edge of
WCLK, provided that WEN and WCS are LOW. Data setup and hold times
must be met with respect to the LOW-to-HIGH transition of the WCLK. It is
permissible to stop the WCLK. Note that while WCLK is idle, the FF, IR, and
PAF flags will not be updated. The write and read clocks can either be
independent or coincident.
17
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WRITE ENABLE (WEN)
transition of RCLK after the last word has been read from the FIFO will make
When the WEN input is LOW, data may be loaded into the FIFO RAM array Output Ready (OR) go HIGH with a true read (RCLK with REN and RCS
on the rising edge of every WCLK cycle if the device is not full. Data is stored LOW), inhibiting further read operations. REN is ignored when the FIFO is
in the RAM array sequentially and independently of any ongoing read opera- empty.
tion.
When WEN is HIGH, no new data is written in the RAM array on each READ SINGLE DATA RATE (RSDR)
WCLK cycle.
When the Read Single Data Rate pin is LOW, the read port will be set to
To prevent data overflow in the IDT Standard mode, FF will go LOW, Single Data Rate mode. In this mode, all read operations are based only on
inhibiting further write operations. Upon the completion of a valid read cycle, the rising edge of RCLK, provided that REN and RCS are LOW. When RSDR
FF will go HIGH, allowing a write to occur. The FF is updated by two WCLK is HIGH, the read port will be set to Double Data Rate mode. In this mode, all
cycles + tSKEW after the RCLK cycle.
read operations are based on both the rising and falling edge of RCLK,
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting provided that REN and RCS are LOW, on the rising edge of RCLK.
further write operations. Upon the completion of a valid read cycle, IR will go
LOW, allowing a write to occur. The IR flag is updated by two WCLK cycles + SERIAL CLOCK (SCLK)
tSKEW after the valid RCLK cycle.
The serial clock is used to load and read data in the programmable offset
WEN is ignored when the FIFO is full in either IDT Standard mode or registers. Data from the Serial Input (SI) can be loaded into the offset registers
FWFT.
on the rising edge of SCLK provided that SEN is LOW. Data can be read from
the offset registers via the Serial Output (SO) on the rising edge of SCLK
provided that SREN is LOW. The serial clock can operate at a maximum
WRITE SINGLE DATA RATE (WSDR)
When the Write Single Data Rate pin is LOW, the write port will be set to frequency of 10MHz and its parameters are different than the FIFO system
Single Data Rate mode. In this mode, all write operations are based only on clock.
the rising edge of WCLK, provided that WEN and WCS are LOW. When
WSDR is HIGH, the read port will be set to Double Data Rate mode. In this SERIAL ENABLE (SEN)
mode, all write operations are based on both the rising and falling edge of
The SEN input is an enable used for serial programming of the program-
WCLK, provided that WEN and WCS are LOW, on the rising edge of WCLK. mable offset registers. It is used in conjunction with SI and SCLK when pro-
gramming the offset registers. When SEN is LOW, data at the Serial In (SI)
READ CLOCK (RCLK)
input can be loaded into the offset register, one bit for each LOW-to-HIGH
A read cycle is initiated on the rising and/or falling edge of the RCLK input. transition of SCLK.
If the Read Single Data Rate (RSDR) pin is selected, data will be read only on
When SEN is HIGH, the offset registers retain the previous settings and no
the rising edge of RCLK, provided that REN and RCS are LOW. If the RSDR offsets are loaded. SEN functions the same way in both IDT Standard and
is not selected, data will be read on both the rising and falling edge of WCLK, FWFT modes.
provided thatREN andRCS are LOW, on the rising edge of RCLK. Setup and
hold times must be met with respect to the LOW-to-HIGH transition of the SERIAL READ ENABLE (SREN)
RCLK. It is permissible to stop the RCLK. Note that while RCLK is idle, theEF/
The SREN output is an enable used for reading the value of the program-
OR and PAE flags will not be updated. Write and Read Clocks can be inde- mable offset registers. It is used in conjunction with SI and SCLK when reading
pendent or coincident.
fromtheoffsetregisters. WhenSRENisLOW, datacanbereadoutoftheoffset
register from the SO output, one bit for each LOW-to-HIGH transition of SCLK.
When SREN is HIGH, the reading of the offset registers will stop. When-
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the ever SREN is activated values in the offset registers are read starting from the
output register on the rising edge of every RCLK cycle if the device is not first location in the offset registers and not from where the last offset value was
empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn SERIAL IN (SI)
read. SREN functions the same way in both IDT Standard and FWFT modes.
maintain the previous data value.
This pin acts as a serial input for loading PAE and PAF offsets into the
In IDT Standard mode, every word accessed at Qn, including the first word programmable offset registers. It is used in conjunction with the Serial Clock
written to an empty FIFO, must be requested using REN provided that the (SCLK) and the Serial Enable (SEN). Data from this input can be loaded into
Read Chip Select (RCS) is LOW. When the last word has been read from the the offset register, one bit for each LOW-to-HIGH transition of SCLK provided
FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. thatSEN is LOW.
REN is ignored when the FIFO is empty. Once a write is performed, EF will go
HIGH allowing a read to occur. Both RCS and REN must be active LOW for SERIAL OUT (SO)
data to be read out on the rising edge of RCLK.
This pin acts as a serial output for reading the values of the PAE and PAF
In FWFT mode, the first word written to an empty FIFO automatically goes offsets in the programmable offset registers. It is used in conjunction with the
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW Serial Clock (SCLK) and the Serial Enable Output (SREN). Data from the
after the first write. REN and RCS do not need to be asserted LOW for the First offset register can be read out using this pin, one-bit for each LOW-to-HIGH
Word to fall through to the output register.All subsequent words require that a transition of SCLK provided that SREN is LOW.
read operation to be executed using REN and RCS. The LOW-to-HIGH
18
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE (OE)
OUTPUTS:
When Output Enable is LOW, the parallel output buffers receive data from
the output register. When OE is HIGH, the output data bus (Qn) goes into a
high-impedance state. During Master or Partial Reset the OE is the only input
that can place the output data bus into high-impedance. During reset the RCS
input can be HIGH or LOW and has no effect on the output data bus.
DATAOUT (Q0-Q39)
(Q0 – Q39) are data outputs for 40-bit wide data, (Q0 – Q19) are data
outputs for 20-bit wide data, or (Q0 – Q9) are data outputs for 10-bit wide data.
FULL FLAG (FF/IR)
Thisisadual-purposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF is HIGH, the FIFOis notfull. Ifnoreads are performed
after a reset (either MRS orPRS), FF willgoLOWafterDwrites tothe FIFO
(D=16,384forthe IDT72T4088, 32,768forthe IDT72T4098, 65,536forthe
IDT72T40108,131,072fortheIDT72T40118.SeeFigure10,WriteCycleand
FullFlagTiming(IDTStandardMode), forthe relevanttiminginformation.
InFWFTmode,theInputReady(IR)functionisselected.IRgoesLOWwhen
memoryspaceisavailableforwritingindata.Whenthereisnolongeranyfree
space left, IR goes HIGH, inhibiting further write operations. If no reads are
performedafterareset(eitherMRSorPRS),IRwillgoHIGHafterDwritesto
theFIFO(D=16,385fortheIDT72T4088,32,769fortheIDT72T4098,65,537
for the IDT72T40108, 131,073 for the IDT72T40118). See Figure 19, Write
Timing(FWFTMode),fortherelevanttiminginformation.
The IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFTmode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
READ CHIP SELECT (RCS)
The Read Chip Select input provides synchronous control of the Read
output port. When RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the low-impedance state. WhenRCS goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to high-impedance. During
a Master or Partial Reset theRCS input has no effect on the Qn output bus, OE
is the only input that provides high-impedance control of the Qn outputs. IfOE
is LOW, the Qn data outputs will be low-impedance regardless of RCS until the
first rising edge of RCLK after a reset is complete. Then if RCS is HIGH the
data outputs will go to high-impedance.
The RCS input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, theEF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. For this reason the user should pay extra
attention when a data word is written to an empty FIFO in FWFT mode. If RCS
is HIGH when an empty FIFO is written into, the first word will fall through to the
output register but will not be available on the Qn outputs because they are in
high-impedance. TheusermusttakeRCS activeLOWtoaccessthisfirstword,
placing the output bus in low-impedance. REN must remain HIGH for at least
one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and
REN LOW will read out the next word. Care must be taken so as not to lose the
first word written to an empty FIFO when RCS is HIGH. Refer to Figure 22,
RCS and REN Read Operation (FWFT Mode). The RCS pin must also be
active (LOW) in order to perform a Retransmit. See Figure 18 for Read Cycle
and Read Chip Select Timing (IDT Standard Mode). See Figure 21 for Read
Cycle and Read Chip Select Timing (FWFT Mode).
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe“marked”location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
EMPTY FLAG (EF/OR)
Thisisadual-purposepin.IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle, EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited untilOR goes LOW
again. See Figure 20, Read Timing (FWFT Mode), for the relevant timing
information.
WRITE CHIP SELECT (WCS)
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
perform normal operations on the write port, the WCS must be enabled.
HSTL SELECT (HSTL)
The inputs that were listed in Table 6 can be setup to be either HSTL or
LVTTL. If HSTL is HIGH, then HSTL operation of those signals will be se-
lected. If HSTLis LOW , then LVTTLwill be selected.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode,ORisatripleregister-bufferedoutput.
BUS-MATCHING (BM, IW, OW)
The pins BM, IW, and OW are used to define the input and output bus
widths. During Master Reset, the state of these pins is used to configure the
device bus sizes. See Table 1 for control settings.All flags will operate on the
word/byte size boundary as defined by the selection of bus width. See Table
7 for Bus-Matching Write to Read Ratio.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(16,384-m)writesfortheIDT72T4088,
(32,768-m)writesfortheIDT72T4098,(65,536-m)writesfortheIDT72T40108,
(131,072-m) writes for the IDT72T40118. The offset “m” is the full offset
value. The default setting for this value is listed in Table 3.
FLAG SELECT BITS (FSEL0 and FSEL1)
Thesepinswillselectthefourdefaultoffsetvaluesforthe PAE and PAFflags
during Master Reset. The four possible settings are listed onTable 3. Note that
the status of these inputs should not change after Master Reset.
19
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
In FWFT mode, the PAF will go LOW after (16,385-m) writes for the data from the Qn outputs. This is especially helpful at high speeds when
IDT72T4088,(32,769-m)writesfortheIDT72T4098,(65,537-m)writesforthe variables within the device may cause changes in the data access times.
IDT72T40108, (131,073-m) writes for the IDT72T40118. where m is the full These variations in access time maybe caused by ambient temperature, sup-
offsetvalue.ThedefaultsettingforthisvalueislistedinTable3.
ply voltage, or device characteristics. The ERCLK output also compensates
SeeFigure29,ProgrammableAlmost-FullFlagTiming(IDTStandardand for any trace length delays between the Qn data outputs and receiving de-
FWFTMode),fortherelevanttiminginformation.
vices inputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
Any variations effecting the data access time will also have a corresponding
writepointertothe“marked”location.Thisdiffersfromnormalmodewherethis effect on the ERCLK output produced by the FIFO device, therefore the
flagis acomparisonofthewritepointertothereadpointer.
ERCLK output level transitions should always be at the same position in time
relative to the data outputs. Note, that ERCLK is guaranteed by design to be
slower than the slowest Qn, data output. Refer to Figure 4, Echo Read Clock
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO and Data Output Relationship, Figure 27, Echo Read Clock & Read Enable
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW Operation in Double Data Rate Mode and Figure 28, Echo RCLK & Echo
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset REN Operation for timing information.
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable3.
InFWFTmode, the PAE willgoLOWwhenthere are n+1words orless in ECHO READ ENABLE (EREN)
theFIFO.Thedefaultsettingforthis valueis statedinTable3.
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
See Figure 30, Programmable Almost-EmptyFlagTiming(IDTStandard selectableviaHSTL.
andFWFTMode),fortherelevanttiminginformation.
The EREN output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for
ECHO READ CLOCK (ERCLK)
reading data from the Qn output port at high speeds. The EREN output is
The Echo Read Clock output is provided in both HSTLand LVTTLmode, controlled by internal logic that behaves as follows: The EREN output is active
selectable via HSTL. The ERCLK is a free-running clock output, it will always LOW for the RCLK cycle that a new word is read out of the FIFO. That is, a
follow the RCLK input regardless of REN and RCS.
rising edge of RCLK will causeEREN to go active, LOW if both REN and RCS
The ERCLK output follows the RCLK input with an associated delay. This are active, LOW and the FIFO is NOTempty.
delay provides the user with a more effective read clock source when reading
RCLK
tERCLK
tERCLK
ERCLK
tA
tD
tD
tA
Q
SLOWEST(3)
5995 drw07
NOTES:
1. REN is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
5. REN = RCS = OE = 0.
Figure 4. Echo Read Clock and Data Output Relationship
20
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO
ONE WRITE TO ONE READ (1:1)
x40 DDR Input to x40 DDR Output
x40 SDR Input to x40 SDR Output
Configuration
Configuration
WSDR
H
RSDR
H
BM
L
IW
L
OW
L
WSDR
L
RSDR
L
BM
L
IW
L
OW
L
SDR Write Clock x40 Data In
SDR Read Clock x40 Data Out
DDR Write Clock x40 Data In
DDR Read Clock x40 Data Out
Positive Edge 1 D[39:0] <= LW1 Positive Edge 1 Q[39:0] <= LW1
Positive Edge 1 D[39:0] <= LW1 Positive Edge 1 Q[39:0] <= LW1
Negative Edge 1 D[39:0] <= LW2 Negative Edge 1 Q[39:0] <= LW2
x40 SDR Input to x20 DDR Output
x20 DDR Input to x40 SDR Output
Configuration
Configuration
WSDR
L
RSDR
H
BM
H
IW
L
OW
L
WSDR
H
RSDR
L
BM
H
IW
H
OW
L
DDR Write Clock x20 Data In
SDR Read Clock x40 Data Out
SDR Write Clock x40 Data In
DDR Read Clock x20 Data Out
Positive Edge 1 D[19:0] <= W1
Negative Edge 1 D[19:0] <= W2
Positive Edge 1 Q[39:20] <= W1
Q[19:0] <= W2
Positive Edge 1 D[39:20] <= W1 Positive Edge 1 Q[19:0] <= W1
D[19:0] <= W2
Negative Edge 1 Q[19:0] <= W2
ONE WRITE TO TWO READ (1:2)
x40 DDR Input to x40 SDR Output
x40 SDR Input to x20 SDR Output
Configuration
Configuration
WSDR
H
RSDR
L
BM
L
IW
L
OW
L
WSDR
L
RSDR
L
BM
H
IW
L
OW
L
DDR Write Clock x40 Data In
SDR Read Clock x40 Data Out
SDR Write Clock x40 Data In
SDR Read Clock x20 Data Out
Positive Edge 1 D[39:0] <= LW1 Positive Edge 1 Q[39:0] <= LW1
Negative Edge 1 D[39:0] <= LW2 Positive Edge 2 Q[39:0] <= LW1
Positive Edge 1 D[39:20] <= LW1 Positive Edge 1 Q[19:0] <= LW1
D[19:0] <= LW2 Positive Edge 2 Q[19:0] <= LW2
x40 DDR Input to x20 DDR Output
x40 SDR Input to x10 DDR Output
Configuration
Configuration
WSDR
H
RSDR
H
BM
H
IW
L
OW
L
WSDR
L
RSDR
H
BM
H
IW
L
OW
H
DDR Write Clock x40 Data In
DDR Read Clock x20 Data Out
SDR Write Clock x40 Data In
DDR Read Clock x10 Data Out
Positive Edge 1 D[39:20] <= LW1 Positive Edge 1 Q[19:0] <= LW1
D[19:0] <=LW2 Negative Edge 1 Q[19:0] <= LW2
Positive Edge 1 D[39:30] <= B1 Positive Edge 1 Q[9:0] <= B1
D[29:20] <= B2 Negative Edge 1 Q[9:0] <= B2
D[19:10] <= B3 Positive Edge 2 Q[9:0] <= B3
D[9:0] <= B4 Negative Edge 2 Q[9:0] <= B4
Negative Edge 1 D[39:20] <= LW3 Positive Edge 2 Q[19:0] <= LW3
D[19:0] <=LW4 Negative Edge 2 Q[19:0] <= LW4
21
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
ONE WRITE TO FOUR READ (1:4)
x40 DDR Input to x20 SDR Output
x40 SDR Input to x10 SDR Output
Configuration
Configuration
WSDR
H
RSDR
L
BM
H
IW
L
OW
L
WSDR
L
RSDR
L
BM
H
IW
L
OW
H
SDR Write Clock x40 Data In
SDR Read Clock x10 Data Out
DDR Write Clock x40 Data In
SDR Read Clock x20 Data Out
Positive Edge 1 D[39:30] <= B1 Positive Edge 1
D[29:20] <= B2 Positive Edge 2
Q[9:0] <= B1
Q[9:0] <= B2
Q[9:0] <= B3
Q[9:0] <= B4
Positive Edge 1 D[39:20] <= LW1 Positive Edge 1 Q[19:0] <= LW1
D[19:0] <=LW2 Positive Edge 2 Q[19:0] <= LW2
D[19:10] <= B3 Positive Edge 3
D[9:0] <= B4 Positive Edge 4
Negative Edge 1 D[39:20] <= LW3 Positive Edge 3 Q[19:0] <= LW3
D[19:0] <=LW4 Positive Edge 4 Q[19:0] <= LW4
x40 DDR Input to x10 DDR Output
Configuration
WSDR
H
RSDR
H
BM
H
IW
L
OW
H
DDR Write Clock x40 Data In
SDR Read Clock x10 Data Out
Positive Edge 1 D[39:30] <= B1 Positive Edge 1 Q[9:0] <= B1
D[29:20]<= B2 Negaitive Edge 1 Q[9:0] <= B2
D[19:10] <= B3 Positive Edge 2 Q[9:0] <= B3
D[9:0] <= B4 Negaitive Edge 2 Q[9:0] <= B4
Negative Edge 1 D[39:30] <= B5 Positive Edge 3 Q[9:0] <= B5
D[29:20]<= B6 Negaitive Edge 3 Q[9:0] <= B6
D[19:10] <= B7 Positive Edge 4 Q[9:0] <= B7
D[9:0] <= B8 Negaitive Edge 4 Q[9:0] <= B8
ONE WRITE TO EIGHT READ (1:8)
x40 DDR Input to x10 SDR Output
Configuration
WSDR
H
RSDR
L
BM
H
IW
L
OW
H
DDR Write Clock x40 Data In
SDR Read Clock x10 Data Out
Positive Edge 1 D[39:30] <= B1 Positive Edge 1 Q[9:0] <= B1
D[29:20]<= B2 Positive Edge 2 Q[9:0] <= B2
D[19:10] <= B3 Positive Edge 3 Q[9:0] <= B3
D[9:0] <= B4 Positive Edge 4 Q[9:0] <= B4
Negative Edge 1 D[39:30] <= B5 Positive Edge 5 Q[9:0] <= B5
D[29:20]<= B6 Positive Edge 6 Q[9:0] <= B6
D[19:10] <= B7 Positive Edge 7 Q[9:0] <= B7
D[9:0] <= B8 Positive Edge 8 Q[9:0] <= B8
22
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
TWO WRITE TO ONE READ (2:1)
x40 SDR Input to x40 DDR Output
x20 DDR Input to x40 DDR Output
Configuration
Configuration
WSDR
L
RSDR
H
BM
L
IW
L
OW
L
WSDR
H
RSDR
H
BM
H
IW
H
OW
L
DDR Write Clock x20 Data In
Positive Edge 1 D[19:0] <=W1 Positive Edge 1 Q[39:20] <=W1
Negative Edge 1 D[19:0] <=W2 Q[19:0] <=W2
Positive Edge 2 D[19:0] <=W3 Negative Edge 1 Q[39:20] <=W3
DDR Read Clock x40 Data Out
SDR Write Clock x40 Data In
DDR Read Clock x40 Data Out
Positive Edge 1 D[39:0] <=LW1 Positive Edge 1 Q[39:0] <= LW1
Positive Edge 2 D[39:0] <=LW2 Negative Edge 1 Q[39:0] <= LW2
Negative Edge 2 D[19:0] <=W4
Q[19:0] <=W4
x20 SDR Input to x40 SDR Output
x10 DDR Input to x40 SDR Output
Configuration
Configuration
WSDR
L
RSDR
L
BM
H
IW
H
OW
L
WSDR
H
RSDR
L
BM
H
IW
H
OW
H
DDR Write Clock x10 Data In
SDR Read Clock x40 Data Out
SDR Write Clock x20 Data In
SDR Read Clock x40 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[39:30] <= B1
Positive Edge 1 D[19:0] <= W1 Positive Edge 1 Q[39:20] <= W1
Negative Edge 1 D[9:0] <= B2
Q[29:20] <= B2
Positive Edge 2 D[19:0] <= W2
Q[19:0] <= W2
Positive Edge 2 D[9:0] <= B3
Negative Edge 2 D[9:0] <= B4
Q[19:10] <= B3
Q[9:0] <= B4
FOUR WRITE TO ONE READ (4:1)
x20 SDR Input to x40 DDR Output
x10 DDR Input to x40 DDR Output
Configuration
Configuration
WSDR
L
RSDR
H
BM
H
IW
H
OW
L
WSDR
H
RSDR
H
BM
H
IW
H
OW
H
SDR Write Clock x20 Data In
Positive Edge 1 D[19:0] <=W1 Positive Edge 1 Q[39:20] <=W1
Positive Edge 2 D[19:0] <=W2 Q[19:0] <=W2
Positive Edge 3 D[19:0] <=W3 Negative Edge 1 Q[39:20] <=W3
DDR Read Clock x40 Data Out
DDR Write Clock x10 Data In
DDR Read Clock x40 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[39:30] <= B1
Negative Edge 1 D[9:0] <= B2
Positive Edge 2 D[9:0] <= B3
Negative Edge 2 D[9:0] <= B4
Q[29:20] <= B2
Q[19:10] <= B3
Q[9:0] <= B4
Positive Edge 4 D[19:0] <=W4
Q[19:0] <=W4
Positive Edge 3 D[9:0] <= B5 Negative Edge 2 Q[39:30] <= B5
Negative Edge 3 D[9:0] <= B6
Positive Edge 4 D[9:0] <= B7
Negative Edge 4 D[9:0] <= B8
Q[29:20] <= B6
Q[19:10] <= B7
Q[9:0] <= B8
x10 SDR Input to x40 SDR Output
Configuration
WSDR
L
RSDR
L
BM
H
IW
H
OW
H
SDR Write Clock x10 Data In
SDR Read Clock x40 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[39:30] <= B1
Positive Edge 2 D[9:0] <= B2
Positive Edge 3 D[9:0] <= B3
Positive Edge 4 D[9:0] <= B4
Q[29:20] <= B2
Q[19:10] <= B3
Q[9:0] <= B4
23
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
EIGHT WRITE TO ONE READ (8:1)
x10 SDR Input to x40 DDR Output
Configuration
WSDR
L
RSDR
H
BM
H
IW
H
OW
H
SDR Write Clock x10 Data In
DDR Read Clock x40 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge
Positive Edge 2 D[9:0] <= B2
Positive Edge 3 D[9:0] <= B3
Q[39:30] <= B1
Q[29:20] <= B2
Q[19:10] <= B3
Q[9:0] <= B4
Positive Edge 4 D[9:0] <= B4
Positive Edge 5 D[9:0] <= B5 Negative Edge
Positive Edge 6 D[9:0] <= B6
Positive Edge 7 D[9:0] <= B7
Q[39:30] <= B5
Q[29:20] <= B6
Q[19:10] <= B7
Q[9:0] <= B8
Positive Edge 8 D[9:0] <= B8
TABLE 8 — TSKEW MEASUREMENT
Data Port
Status Flags
TSKEW Measurement
Configuration
DDR Input
to
EF & PAE
Negative Edge WCLK to
Positive Edge RCLK
DDR Output
FF & PAF
EF & PAE
Negative Edge RCLK to
Positive Edge WCLK
DDR Input
to
Negative Edge WCLK to
Positive Edge RCLK
SDR Output
FF & PAF
EF & PAE
Positive Edge RCLK to
Positive Edge WCLK
SDR Input
to
Positive Edge WCLK to
Positive Edge RCLK
DDR Output
FF & PAF
EF & PAE
Negative Edge RCLK to
Positive Edge WCLK
SDR Input
to
Positive Edge WCLK to
Positive Edge RCLK
SDR Output
FF & PAF
Positive Edge RCLK to
Positive Edge WCLK
24
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAGTIMINGSPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5995 drw08
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 5. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
SYSTEMINTERFACEPARAMETERS
Min. Max. Units
IDT72T4088
IDT72T4098
IDT72T40108
IDT72T40118
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
25
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T4088/72T4098/
72T40108/72T40118incorporatesthenecessarytapcontrollerandmodified
padcellstoimplementtheJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
•
•
•
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5995 drw09
Figure 6. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
26
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
Test-Logic
Reset
0
1
Select-
IR-Scan
0
1
1
Run-Test/
Idle
Select-
DR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
5995 drw10
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 7. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IR This state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstatesaresimilartotheShift-IR,Exit1-IR,Pause-IR,Exit2-IR and
Update-IRstatesintheInstructionpath.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetailsonTAPcontrollerreset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-Scan This is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
27
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
•
TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16
differentpossibleinstructions. Instructionsaredecodedasfollows.
Hex
Value
Instruction
Function
TESTDATAREGISTER
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
0x02
0x01
0x03
0x0F
IDCODE
SelectChipIdentificationdataregister
SelectBoundaryScanRegister
JTAG
SAMPLE/PRELOAD
HI-IMPEDANCE
BYPASS
SelectBypassRegister
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
Table 8. JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
SAMPLE/PRELOAD
THE DEVICE IDENTIFICATION REGISTER
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
entering and leaving the IC.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
For the IDT72T4088/72T4098/72T40108/72T40118, the Part Number
fieldcontainsthefollowingvalues:
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand
selects the one-bit bypass register to be connected between TDI and TDO.
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI
toTDOwithoutaffectingtheconditionoftheICoutputs.
Device
Part# Field
04A3
IDT72T4088
IDT72T4098
IDT72T40108
IDT72T40118
04A2
04A1
04A0
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
theIC.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
IDT72T4088/4098/40108/40118JTAGDeviceIdentificationRegister
EXTEST
The requiredEXTESTinstructionis notavailable forthis device.
28
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
tRSR
tRSS
REN
tRSR
tRSR
tRSS
WEN
tRSS
FWFT(2)
tRSS
FSEL0(2),
FSEL1
tRSS
OW(2),
IW, BM
tHRSS
HSTL(2)
tRSS
tRSR
tRSR
WSDR(2)
tRSS
RSDR(2)
tRSS
RT
tRSS
SEN
tRSS
SREN
tRSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
tRSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
tRSF
PAE
tRSF
PAF
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
5995 drw11
NOTES:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
2. The status of these pins are latched in when the Master Reset pulse is LOW.
Figure 8. Master Reset Timing
29
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
t
RSS
RSS
SEN
t
SREN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
PAF
t
RSF
t
RSF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
5995 drw12
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 9. Partial Reset Timing
30
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK1
tCLKH1
tCLKL1
NO WRITE
NO WRITE
2
WCLK
1
1
(1)
2
(1)
t
SKEW1
tDH
t
SKEW1
tDS
tDH
tDS
D
X+1
DX
D0
- D39
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
RCS
tENS
tA
t
A
Q0
- Q39
NEXT DATA READ
DATA READ
5995 drw13
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. OE = LOW, EF = HIGH.
3. WCS = LOW.
4. WCLK must be free running for FF to update.
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)
31
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
32
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK1
tCLKH1
tCLKL1
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0
- Q39
tOLZ
tOHZ
tOLZ
tOE
OE
WCLK
WEN
(1)
SKEW1
t
tENS
tENH
tENH
tENS
tWCSS
tWCS
H
WCS
tDS
tDH
tDH
tDS
D0
D1
D0 - D39
5995 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. First data word latency = tSKEW1 + 1*TRCLK + tREF.
3. RCS is LOW.
4. RCLK must be free running for EF to update.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
33
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
34
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
35
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
36
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
37
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
38
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
1
RCLK
tENS
REN
RCS
tENS
tENS
tENS
tENH
tREF
tREF
EF
tRCSHZ
tRCSHZ
tA
tA
tRCSLZ
tRCSLZ
LAST DATA-1
LAST DATA
Q0 - Qn
t
SKEW1(1)
WCLK
tENS
tENH
WEN
tDS
tDH
Dn
Dx
5995 drw21
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. First data word latency = tSKEW1 + 1*TRCLK + tREF.
3. OE is LOW.
4. RCLK must be free running for EF to update.
Figure 18. Read Cycle and Read Chip Select (IDT Standard Mode)
39
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
40
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
41
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
42
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ERN
CRS
43
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
44
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
45
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SEN
tSDH
t
SDS
BIT X(1)
BIT 1
BIT 1
BIT X(1)
SI
5995 drw28
EMPTY OFFSET
FULL OFFSET
NOTE:
1. In SDR mode, X = 14 for the IDT72T4088, X = 15 for the IDT72T4098, X = 16 for the IDT72T40108, X = 17 for the IDT72T40118.
2. In DDR mode, X = 13 for the IDT72T4088, X = 14 for the IDT72T4098, X = 15 for the IDT72T70108, X = 16 for the IDT72T40118.
Figure 25. Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SREN
t
SOA
t
SOA
BIT X(1)
BIT X(1)
BIT 0
BIT 0
SO
EMPTY OFFSET
FULL OFFSET
5995 drw29
NOTE:
1. In SDR mode, X = 14 for the IDT72T4088, X = 15 for the IDT72T4098, X = 16 for the IDT72T40108, X = 17 for the IDT72T40118.
2. In DDR mode, X = 13 for the IDT72T4088, X = 14 for the IDT72T4098, X = 15 for the IDT72T40108, X = 16 for the IDT72T40118.
3. Offset register values are always read starting from the first location in the offset register upon initiating SREN.
Figure 26. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes)
46
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
47
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tENS
tENH
WEN
tDS
t
DH
tDS
t
DH
tDS
tDH
Wn+1
Wn+2
Wn+3
D0 - Dn
tSKEW1
1
2
RCLK
b
e
h
a
d
g
c
i
f
tERCLK
ERCLK
tENS
tENH
REN
RCS
tENS
tCLKEN
tCLKEN
tCLKEN
tCLKEN
EREN
Qn
tA
tA
t
RCSLZ
HIGH-Z
Wn+1
Wn+2
Wn+3
tREF
tREF
OR
tA
tA
tA
O/P
Reg.
Wn
Last Word
Wn+1
Wn+2
Wn+3
5995 drw31
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
d.
e.
f.
g.
h.
i.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
3. OE is LOW.
4. The truth table for EREN is shown below:
RCLK
OR
RCS
REN
EREN
↑
↑
↑
↑
↑
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
0
1
1
1
1
Figure 28. Echo RCLK and Echo REN Operation (FWFT Mode Only)
48
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL1
tCLKH1
WCLK
WEN
PAF
1
2
2
1
tENS
tENH
tPAFS
tPAFS
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
D - (m +1) words in FIFO(2)
t
SKEW3(3)
RCLK
tENH
tENS
5995 drw32
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D=16,384 for the IDT72T4088, 32,768 for the IDT72T4098, 65,536 for the IDT72T40108, 131,072 for the IDT72T40118.
In FWFT Mode: D=16,385 for the IDT72T4088, 32,769 for the IDT72T4098, 65,537 for the IDT72T40108, 131,073 for the IDT72T40118.
3. PAF is asserted and updated on the rising edge of WCLK only.
4. tSKEW3 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW3, then the PAF deassertion time may be delayed one extra WCLK cycle.
5. RCS = LOW.
Figure 29. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH1
tCLKL1
WCLK
tENS
tENH
WEN
PAE
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n
words in FIFO(2)
n + 1 words in FIFO(3)
SKEW3(4)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
tPAES
tPAES
t
1
2
1
2
RCLK
tENS
tENH
5995 drw33
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted and updated on the rising edge of RCLK only.
5. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. RCS = LOW.
Figure 30. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
49
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
avoidedbycreatingcomposite flags, thatis, ANDingEF ofeveryFIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 31 demonstrates a width expansion using two IDT72T4088/
72T4098/72T40108/72T40118devices.D0-D40fromeachdeviceforma80-
bitwideinputbusandQ0-Q39fromeachdeviceforma80-bitwideoutputbus.
AnywordwidthcanbeattainedbyaddingadditionalIDT72T4088/72T4098/
72T40108/72T40118devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH
(FWFT)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
IDT
IDT
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
72T4088
72T4098
72T40108
72T40118
72T4088
72T4098
72T40108
72T40118
#1
FULL FLAG/INPUT READY (FF/IR)
(1)
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
FIFO
#1
FIFO
#2
m + n
n
Qm+1 - Qn
DATA OUT
m
5995 drw34
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 31. Block Diagram of 16,384 x 80, 32,768 x 80, 65,536 x 80, 131,072 x 80 Width Expansion
50
SEPTEMBER21,2004
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT
TRANSFER CLOCK
FWFT
FWFT
WRITE CLOCK
READ CLOCK
RCLK
WCLK
WEN
IR
RCLK
WCLK
IDT
IDT
READ CHIP SELECT
RCS
WRITE ENABLE
INPUT READY
OR
WEN
72T4088
72T4098
72T40108
72T40118
72T4088
72T4098
72T40108
72T40118
READ ENABLE
REN
REN
RCS
OUTPUT READY
IR
OR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
5995 drw35
Figure 32. Block Diagram of 32,768 x 40, 65,536 x 40, 131,072 x 40, 262,144 x 40 Depth Expansion in Single Data Rate Mode
DEPTH EXPANSION CONFIGURATION IN SINGLE DATA RATE
(FWFT MODE ONLY)
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The IDT72T4088 can easily be adapted to applications requiring depths
greaterthan16,384,32,768fortheIDT72T4098,65,536fortheIDT72T40108,
131,072 for the IDT72T40118 with an 40-bit bus width. In FWFT mode, the
FIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnectedto
the data inputs of the next) with no external logic necessary. The resulting
configuration provides a total depth equivalent to the sum of the depths
associatedwitheachsingleFIFO. Figure32showsadepthexpansionusing
twoIDT72T4088/72T4098/72T40108/72T40118devices.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towrite a wordtofillit.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
inthedepthexpansionconfiguration.Also,thedevices mustbeoperatingin
SingleDataRatemodesincethatistheonlymodeavailableinFWFT.Thefirst
wordwrittentoanemptyconfigurationwillpassfromoneFIFOtothenext("ripple
down")untilitfinallyappearsattheoutputsofthelastFIFOinthechain–noread
operationisnecessarybuttheRCLKofeachFIFOmustbefree-running. Each
timethedatawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoes
LOW, enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
51
SEPTEMBER21,2004
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB208-1)
BB
Commercial Only
Commercial Only
Commercial and Industrial
Commercial Only
4
5
6-7
10
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
L
Low Power
72T4088
72T4098
16,384 x 40 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
32,768 x 40 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
72T40108 65,536 x 40 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
72T40118 131,072 x 40 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
5995 drw36
NOTE:
1. Industrial temperature range product is available for 6-7ns as a standard product. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
03/01/2002
04/08/2002
04/24/2002
05/24/2002
11/21/2002
02/11/2003
03/20/2003
12/17/2003
09/21/2004
pgs. 1, 4, 6, 8, 9, and 23.
pgs. 1, 8, 9, 11, 33-37, 42, 46-48, and 51.
pgs. 19, and 28.
pgs. 6-9, and 12.
pgs. 1, and 10.
pgs. 7, 8, and 27.
pgs. 25, 27, 28, and 44.
pgs. 10, 31-34, 36-38, 44, and 49.
pgs. 1, 3, 9-11, 17, and 28.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
52
相关型号:
72T4088L10BBG
FIFO, 16KX40, 4.5ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208
IDT
72T4088L5BBG
FIFO, 16KX40, 3.6ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208
IDT
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