72T631S12BCGI [IDT]
Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 HEIGHT, 1 MM PITCH, GREEN, BGA-256;
| 型号： | 72T631S12BCGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 HEIGHT, 1 MM PITCH, GREEN, BGA-256 静态存储器 内存集成电路 |
| 文件： | 总27页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70T633/1S
HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
◆
Features
Full hardware support of semaphore signaling between
ports on-chip
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array and 208-ball fine pitch
BallGridArray
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
◆
◆
◆
– Commercial:8/10/12/15ns(max.)
– Industrial:10/12ns (max.)
◆
◆
◆
◆
◆
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
◆
◆
◆
◆
◆
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
Green parts available, see ordering information
On-chip port arbitration logic
Functional Block Diagram
U B
L
L
U B
R
L B
LB
R
R/W L
R/W R
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
C E 0L
C E 0R
R
CE1L
CE1R
OEL
OER
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
512/256K x 18
MEMORY
ARRAY
Din_L
I/O0L- I/O17L
Din_R
I/O0R - I/O17R
(1)
A
A
18R
0R
(1)
Address
Decoder
Address
Decoder
A
18L
ADDR_L
ADDR_R
A
0L
TDI
TCK
TMS
JTAG
OE
L
OER
ARBITRATION
TDO
T
R
ST
INTERRUPT
SEMAPHORE
LOGIC
C E 0R
CE1R
C E 0L
CE1L
R/WL
R/W
R
(2,3)
L
(2,3)
R
B U S Y
S EM
INT
B U S Y
S E M
M/S
L
R
(3)
(3)
R
L
IN T
ZZ
CONTROL
LOGIC
(4)
(4)
ZZR
ZZ
L
NOTES:
1. Address A18x is a NC for IDT70T631.
5670 drw 01
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
BUSY and INT are non-tri-state totem-pole outputs (push-pull).
3
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
OCTOBER 2011
1
DSC-5670/8
©2011IntegratedDeviceTechnology,Inc.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous feature controlled by the chip enables (either CE0 or CE1) permit the
Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a on-chip circuitry of each port to enter a very low standby power mode.
stand-alone9216/4608K-bitDual-PortRAMorasacombinationMAS-
TheIDT70T633/1hasaRapidWriteModewhichallowsthedesigner
TER/SLAVEDual-PortRAMfor36-bit-or-morewordsystem.Usingthe toperformback-to-backwriteoperationswithoutpulsingtheR/Winput
IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider eachcycle.Thisisespeciallysignificantatthe8and10nscycletimesof
memorysystemapplications results infull-speed, error-free operation the IDT70T633/1, easing design considerations at these high perfor-
withouttheneedforadditionaldiscretelogic.
mancelevels.
The70T633/1cansupportanoperatingvoltageofeither3.3Vor2.5V
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor on one or both ports, controlled by the OPT pins. The power supply for
reads or writes to any location in memory. An automatic power down the core ofthe device (VDD)remains at2.5V.
2
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfiguration(1,2,3)
70T633/1BC
BC-256(5,6)
256-Pin BGA
Top View
03/13/03
A4
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A5
A10
A15
A16
A
17L
NC
TDI
NC
A
11L
A
8L
9L
7L
NC CE1L
INT
L
A
5L
A
2L
A
0L
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
(4)
NC
NC TDO
A
12L
A
NC
A4L
A
1L
A
18L
A
15L
13L
UB
L
R/W
L
NC
NC
NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
NC
A
A
10L
I/O9L
V
SS
A
16L
A
NC
LBL
SEM
L
B U S Y
L
A6L
A
3L
I/O8L
OPT
L
NC
D1
D2
D6
D9
DDQL
D11
D3
D5
D7
D8
DDQR
D10
D12
D13
D14
D15
D16
D4
NC I/O9R
V
DDQL
VDDQR
V
NC
VDDQL
V
DDQR
V
V
DDQL
V
DDQR
V
DD
NC
NC I/O8R
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
DDQL
E14
E16
E15
V
DD
V
DD
V
SS
V
SS
V
SS
SS
SS
VSS
V
DD
VDD
V
DDQR
I/O10R I/O10L NC
V
NC
I/O7R
I/O7L
F7
F5
F6
F9
F10
F1
F2
F3
F11
F13
F14
F15
F16
F8
F12
F4
V
SS
I/O11L NC I/O11R
V
DD
NC
V
VSS
I/O6R NC I/O6L
DDQR
V
SS
V
VDDQL
V
SS
VDD
G1
G2
G3
G5
H5
G4
G6
G8
G9
G14
G15
G16
G7
G10
G12
G13
G11
NC
V
SS
NC
V
DDQR
V
SS
V
SS
V
I/O12L
V
SS
VSS
VSS
VDDQL I/O5L NC
NC
V
SS
H11
H12
H16
H13
H7
H8
H9
H10
H14
H15
H3
H4
H6
H1
H2
V
SS
V
SS
I/O5R
V
DDQL
V
SS
V
SS
V
SS
V
SS
SS
NC
NC
NC
V
DDQR
V
SS
VSS
NC I/O12R
J1
J5
J2
J3
J4
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O13L
ZZ
R
I/O14R I/O13R
V
DDQL
VSS
VSS
V
SS
V
SS
V
DDQR
I/O4R
V
V
SS
ZZL
I/O3R I/O4L
K6
K8
K10
K12
K13
K2
K4
K5
K7
K9
K11
K15
K16
K1
K3
K14
V
SS
V
SS
V
SS
V
SS
V
DDQR
V
SS
V
SS
V
SS
V
SS
SS
NC
V
DDQL
NC I/O3L
NC
I/O14L
NC
L7
L8
L11
L12
L13
L5
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
VSS
VSS
V
VDD
V
DDQL
I/O2L
I/O15R
VDDQR
VDD
NC
V
SS
V
SS
NC I/O2R
I/O15L NC
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1
M2
M3
M4
M16
M14
M15
VDD
V
DD
VSS
VSS
V
SS
VSS
V
DD
VDD
V
DDQL
I/O16R I/O16L NC
V
DDQR
NC
I/O1R I/O1L
N8
N12
N16
N13
N4
N5
N6
DDQR
N7
N9
N10
N11
N15
N1
N2
N3
N14
V
DDQL
V
DDQL
NC
V
DD
V
DD
V
VDDQL
V
DDQR
V
DDQR
VDDQL
I/O0R
VDDQR
NC I/O17R NC
NC
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
NC I/O17L TMS
A
16R
A
13R
15R
A
7R
NC
LB
R
SEM
R
B U S Y
R
A
6R
NC
NC
I/O0L
A
10R
A
3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
(4)
A
A
12R
A9R
UBR
CE0R R/W
R
M/S
NC
NC
NC TRST A18R
A4R
A1R OPTR
NC
T2
T3
T1
T4
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
TCK
NC
NC
A17R
A
14R
NC CE1R
NC
NC
A11R
A8R
OER
INT
R
A
5R
A
2R
A
0R
5670 drw 02c
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
,
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
3
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3)(con't.)
03/12/03
1
2
3
4
5
6
7
8
9
11 12 13 14
10
16 17
15
V
V
V
DD
SS
SS
I/O9L
A
12L
A
B
C
D
E
F
NC
V
SS
A
16L
13L
A
8L
NC
A
0L
VSS
NC
I/O8L
NC
A
4L
OPTL
TDO
NC
SEM
L
INTL
A
B
C
D
E
F
NC
VSS
A
9L
NC
A5L
TDI
A
17L
A
NC
A
1L
VDDQR
NC
V
V
SS
DD
CE0L
BUSY
L
L
(4)
A10L
V
SS
I/O7R
NC
I/O9R
V
DD
A
18L
A
14L
CE1L
A6
L
A2L
I/O8R
V
DDQL
V
DDQR
UB
L
R/W
NC
VSS
I/O10L
A
15L
A
11L
A7L
V
DD
VDDQL
I/O7L
NC
NC
VDD
NC
LB
L
A
3L
OE
L
V
DDQR I/O10R
I/O11L
NC
NC
I/O6L
VSS
V
DDQL
VSS
I/O6R
V
DDQR
I/O11R
V
SS
NC
NC
NC
V
SS
I/O12L
NC
V
DDQL
I/O5L
NC
NC
G
H
J
G
H
J
70T633/1BF
BF-208(5,6)
VDD
NC
VDDQR
V
DD
I/O12R
NC
V
SS
I/O5R
V
DD
V
DDQL
ZZ
L
V
SS
VDDQR
VDD
VSS
ZZR
208-Ball BGA
Top View(7)
V
DDQL
I/O3R
NC
V
SS
I/O4R
I/O14R
NC
VSS
I/O13R
K
L
V
SS
K
L
I/O14L
V
DDQR
I/O15R
NC
I/O13L
I/O3L
NC
V
SS
I/O4L
V
DDQL
V
SS
NC
V
SS
I/O2R
NC
V
DDQR
M
N
P
R
T
M
N
P
R
T
NC
V
SS
I/O15L
NC
I/O1R
NC
V
DDQL
I/O2L
NC
I/O1L
I/O16R I/O16L
V
DDQR
V
DD
I N T
R
A
4R
VSS
A
16R
A
12R
A8R
TR S T
NC
SEM
R
V
SS
SS
V
DDQL
I/O0R
V
DDQR
V
V
SS
SS
A5R
A
1R
2R
A
13R
14R
A
9R
NC
A
17R
TCK
CE0R
VSS
NC
I/O17R
BUSY
R
V
V
SS
A
NC
(4)
NC
A6R
A
A10R
CE1R
NC
I/O17L
VDDQL TMS
A18R
UB
R
R/WR
VDD
OPT
R
NC
I/O0L
V
DD
A
3R
A
0R
A
11R
A7R
VSS
V
DD
M/S
NC
NC
A
15R
LBR
OER
U
U
5670 drw 02b
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
4
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE1R
Names
Chip Enables (Input)
CE0L
R/W
OE
,
CE1L
CE0R
R/W
OE
,
L
R
Read/Write Enable (Input)
Output Enable (Input)
L
R
(1)
(1)
A
0L - A18L
A
0R - A18R
Address (Input)
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
Semaphore Enable (Input)
Interrupt Flag (Output)
SEM
INT
BUSY
UB
LB
L
SEM
INT
BUSY
UB
LB
R
L
R
Busy Flag (Output)
L
R
Upper Byte Select (Input)
Lower Byte Select (Input)
Power (I/O Bus) (3.3V or 2.5V)(2) (Input)
Option for selecting VDDQX(2,3) (Input)
Sleep Mode Pin(4) (Input)
Master or Slave Select (Input)(5)
Power (2.5V)(2) (Input)
L
R
L
R
V
DDQL
VDDQR
OPT
L
OPTR
ZZ
L
ZZR
M/S
NOTES:
V
DD
1. Address A18x is a NC for IDT70T631.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
V
SS
Ground (0V) (Input)
TDI
TDO
TCK
TMS
TRST
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
5670 tbl 01
5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master
(M/S=VIH).
5
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1)
Upper Byte Lower Byte
CE
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
H
I/O9-17
High-Z
High-Z
High-Z
High-Z
I/O0-8
High-Z
High-Z
High-Z
MODE
Deselected–Power Down
OE
X
X
X
X
X
X
L
SEM
H
CE
0
UB
X
X
H
H
L
LB
X
X
H
L
H
X
L
L
L
L
L
L
L
L
X
X
L
H
Deselected–Power Down
Both Bytes Deselected
Write to Lower Byte
Write to Upper Byte
Write to Both Bytes
Read Lower Byte
H
H
H
H
H
H
H
H
H
X
H
DIN
H
H
L
L
DIN
High-Z
H
L
L
DIN
DIN
H
H
L
L
H
H
H
X
X
High-Z
DOUT
L
H
H
L
DOUT
High-Z
Read Upper Byte
L
H
L
DOUT
DOUT
Read Both Bytes
H
X
H
L
L
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
X
X
X
High-Z Sleep Mode
5670 tbl 02
NOTE:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
Truth Table II – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE(2)
H
OE
L
UB
LB
L
SEM
L
R/W
H
I/O1-17
I/O
0
Mode
L
X
X
DATAOUT
DATAOUT Read Data in Semaphore Flag(3)
↑
H
X
L
L
X
DATAIN
Write I/O
0 into Semaphore Flag
______
______
L
X
X
X
L
Not Allowed
5670 tbl 03
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL.
6
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
RecommendedDCOperating
RecommendedOperating
TemperatureandSupplyVoltage(1)
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
2.4
0
Typ.
2.5
2.5
0
Max.
2.6
2.6
0
Unit
V
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
V
DD
DDQ
SS
V
V
2.5V
2.5V
+
+
100mV
100mV
V
V
Industrial
0V
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
5670 tbl 04
(2)
____
V
DDQ + 100mV
1.7
1.7
V
V
V
IH
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Input High Voltage _
JTAG
(2)
____
VIH
VDD + 100mV
Input High Voltage -
ZZ, OPT, M/S
(2)
____
____
____
V
IH
V
DD - 0.2V
V
DD + 100mV
V
V
AbsoluteMaximumRatings(1)
VIL
Input Low Voltage
-0.3(1)
0.7
0.2
Symbol
Rating
Commercial
& Industrial
Unit
V
Input Low Voltage -
ZZ, OPT, M/S
VIL
-0.3(1)
V
5670 tbl 05
V
TERM
VDD Terminal Voltage
-0.5 to 3.6
NOTES:
(VDD
)
with Respect to GND
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be
supplied as indicated above.
(2)
TERM
V
V
DDQ Terminal Voltage
-0.3 to VDDQ + 0.3
-0.3 to VDDQ + 0.3
-55 to +125
V
(VDDQ
)
with Respect to GND
(2)
TERM
V
Input and I/O Terminal
Voltage with Respect to GND
V
(INPUTS and I/O's)
(3)
TBIAS
Temperature
Under Bias
oC
oC
TSTG
Storage
-65 to +150
Temperature
RecommendedDCOperating
Conditions with VDDQ at 3.3V
T
JN
Junction Temperature
+150
50
oC
IOUT(For VDDQ = 3.3V) DC Output Current
mA
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
3.15
0
Typ.
2.5
3.3
0
Max.
2.6
3.45
0
Unit
V
IOUT(For VDDQ = 2.5V) DC Output Current
40
mA
V
DD
DDQ
SS
5670 tbl 07
V
V
NOTES:
V
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
(2)
____
2.0
1.7
V
DDQ + 150mV
V
V
V
IH
_
Input High Voltage
JTAG
(2)
____
VIH
VDD + 100mV
Input High Voltage -
ZZ, OPT, M/S
(2)
____
____
____
V
IH
V
DD - 0.2V
V
DD + 100mV
V
V
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
(1)
VIL
Input Low Voltage
-0.3
0.8
0.2
Input Low Voltage -
ZZ, OPT, M/S
(1)
VIL
-0.3
V
Capacitance(1)
5670 tbl 06
NOTES:
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be
supplied as indicated above.
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3)
OUT
C
V
10.5
pF
5670 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
7
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T633/1S
Symbol
|ILI
Parameter
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DD = Max. IN = 0V to VDD
CE = VIH or CE = VIL, VOUT = 0V to VDDQ
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Min.
Max.
10
Unit
µA
µA
µA
V
(1)
___
___
___
___
|
Input Leakage Current
V
(1,2)
|ILI|
JTAG & ZZ Input Leakage Current
V
,
V
+30
10
(1,3)
|ILO
|
Output Leakage Current
0
1
V
OL (3.3V) Output Low Voltage(1)
OH (3.3V) Output High Voltage(1)
OL (2.5V) Output Low Voltage(1)
OH (2.5V) Output High Voltage(1)
NOTES:
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
5670 tbl 09
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 2.5V ± 100mV)
70T633/1S8
Com'l Only
70T633/1S10
Com'l
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
& Ind(6)
Symbol
Parameter
Test Condition
= VIL
Outputs Disabled
f = fMAX
Version
COM'L
Typ.(4)
Max.
Typ.(4)
300
300
90
Max.
405
445
120
145
265
290
Typ.(4)
Max.
355
395
105
130
230
255
Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
305
CE
L
and CE
R
,
S
S
S
S
S
S
350
475
300
300
75
225
____
____
____
____
(1)
IND
(6)
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
mA
CE
L
= CE
R
= VIH
COM'L
IND
115
140
60
85
(1)
f = fMAX
____
____
____
____
90
75
(6)
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
COM'L
IND
240
315
200
200
180
180
150
200
____
____
____
____
(1)
f = fMAX
ISB3
Full Standby Current Both Ports CE
> VDDQ - 0.2V,
IN > VDDQ - 0.2V or VIN < 0.2V,
L and
COM'L
IND
S
S
2
10
2
2
10
20
2
2
10
20
2
10
(Both Ports - CMOS CE
R
Level Inputs)
V
f = 0
____
____
____
____
(2)
(6)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
CE"A" < 0.2V and
COM'L
IND
S
S
240
315
200
200
265
290
180
180
230
255
150
200
(5)
CE"B" > VDDQ - 0.2V ,
IN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
V
____
____
____
____
(1)
f = fMAX
IZZ
Sleep Mode Current ZZL = ZZR =
VIH
mA
COM'L
IND
S
S
2
10
2
2
10
20
2
2
10
20
2
10
(1)
(Both Ports - TTL
Level Inputs)
f = fMAX
____
____
____
____
5670 tbl 10
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. VDD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).
4. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V
CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
5. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.
8
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ = 3.3V/2.5V)
Input Pulse Levels
GND to 3.0V / GND to 2.5V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
Figure 1
5670 tbl 11
50Ω
50Ω
,
DATAOUT
1.5V/1.25
10pF
(Tester)
5670 drw 03
Figure 1. AC Output Test load.
4
3.5
3
2.5
Δ
tAA/tACE
(Typical, ns)
2
1.5
1
0.5
0
0
160
20
40
60
120
140
80
100
Δ
Capacitance (pF) from AC Test Load
5670 drw 04
Figure 3. Typical Output Derating (Lumped Capacitive Load).
9
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70T633/1S8
Com'l Only
70T633/1S10
Com'l
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
& Ind(5)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
LZOB
HZ
PU
PD
SOP
SAA
SOE
Read Cycle Time
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
8
8
4
10
10
5
12
12
6
15
15
7
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
4
5
6
7
____
____
____
____
t
Output Hold from Address Change
3
3
0
0
3
3
0
0
3
3
0
0
3
3
0
0
t
Output Low-Z Time Chip Enable and Semaphore(1,2)
Output Low-Z Time Output Enable and Byte Enable(1,2)
Output High-Z Time(1,2)
____
____
____
____
____
____
____
____
t
t
3.5
4
6
8
t
Chip Enable to Power Up Time(2)
0
0
0
0
____
____
____
____
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
7
4
8
5
8
4
8
6
12
8
____
____
____
____
t
____
____
____
____
t
t
2
2
10
5
2
12
6
2
15
7
____
____
____
____
t
Semaphore Output Enable Access Time
ns
5670 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(4)
70T633/1S8
Com'l Only
70T633/1S10
Com'l
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
& Ind(5)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
DH
WZ
OW
SWRD
SPS
Write Cycle Time
8
6
6
0
6
0
4
10
7
12
9
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
7
9
t
0
0
t
7
9
12
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
0
0
t
5
7
10
t
0
0
0
0
(1,2)
____
____
____
____
t
Write Enable to Output in High-Z
3.5
4
6
8
t
Output Active from End-of-Write(1,2)
SEM Flag Write to Read Time
SEM Flag Contention Window
3
4
4
3
5
5
3
5
5
3
5
5
____
____
____
____
____
____
____
____
____
____
____
____
t
t
ns
5670 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
10
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE(6)
(4)
tAOE
OE
(4)
tABE
UB, LB
R/W
tOH
(1)
tLZ/tLZOB
VALID DATA(4)
DATAOUT
(2)
tHZ
.
BUSYOUT
(3,4)
5670 drw 06
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD.
5. SEM = VIH.
6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
Timing of Power-Up Power-Down
CE
t
PU
tPD
ICC
50%
50%
.
5670 drw 07
ISB
11
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
t
HZ
OE
tAW
CE or SEM(9)
UB, LB(9)
R/W
(3)
(2)
(6)
t
WR
tAS
tWP
(7)
OW
(7)
t
t
WZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
5670 drw 10
.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)
t
WC
ADDRESS
t
AW
CE or SEM(9)
UB, LB(9)
(6)
AS
(3)
WR
(2)
t
t
EW
t
R/W
t
DW
tDH
DATAIN
.
.
5670 drw 11
NOTES:
1. R/W or CE or UB or LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
12
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CaremustbetakentostillmeettheWriteCycletime(tWC),thetimein
whichtheAddressinputsmustbestable. Inputdatasetupandholdtimes
(tDW andtDH)willnowbereferencedtotheendingaddresstransition. In
thisRapidWriteMode theI/OwillremainintheInputmodefortheduration
of the operations due toR/W beingheldlow. AllstandardWrite Cycle
specifications must be adhered to. However, tAS and tWR are only
applicable when switching between read and write operations. Also,
therearetwoadditionalconditionsontheAddressInputsthatmustalso
bemettoensurecorrectaddresscontrolled writes. Thesespecifications,
theAllowableAddressSkew(tAAS)andtheAddressRise/Falltime(tARF),
mustbemettousetheRapidWriteMode. Iftheseconditionsarenotmet
thereisthepotentialforinadvertentwriteoperationsatrandomintermediate
locationsasthedevicetransitionsbetweenthedesiredwriteaddresses.
RapidWrite Mode Write Cycle
Unlike othervendors'Asynchronous RandomAccess Memories,
theIDT70T633/1iscapableofperformingmultipleback-to-backwrite
operations without having to pulse the R/W, CE, or BEn signals high
duringaddresstransitions. ThisRapidWriteModefunctionalityallowsthe
systemdesignertoachieveoptimumback-to-backwritecycleperformance
withoutthedifficulttaskofgeneratingnarrowresetpulseseverycycle,
simplifyingsystemdesignandreducingtimetomarket.
DuringthisnewRapidWriteMode,theendofthewritecycleisnow
definedbytheendingaddresstransition,insteadoftheR/WorCEorBEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughouttheaddresstransitionbetweenwritecycles.
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)
(4)
WC
t
WC
t
t
WC
ADDRESS
(2)
EW
t
CE or SEM(6)
BEn
R/W
t
WR
t
WP
(5)
OW
(5)
WZ
t
t
DATAOUT
t
DH
tDH
t
DH
tDW
t
DW
tDW
DATAIN
5670 drw 08
NOTES:
1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
13
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle(1)
Symbol
Parameter
Min
Max
Unit
____
t
AAS
Allowable Address Skew for RapidWrite Mode
Address Rise/Fall Time for RapidWrite Mode
1
ns
____
tARF
1.5
V/ns
5670 tbl 14
NOTE:
1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.
Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle
A
0
t
ARF
t
AAS
(1)
A
18
t
ARF
5670 drw 09
NOTE:
1. A17 for IDT70T631.
14
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
AW
tWR
t
ACE
t
EW
SEM(1)
t
OH
t
SOP
t
DW
OUT
DATA
DATA INVALID
VALID(2)
I/O
t
AS
t
WP
tDH
R/W
t
SWRD
tSOE
OE
t
SOP
Write Cycle
Read Cycle
.
5670 drw 12
NOTES:
1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate UB/LB controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
t
SPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
.
5670 drw 13
NOTES:
1. DOR = DOL = VIL, CE0L = CE0R = VIH; CE1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
15
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70T633/1S8
Com'l Only
70T633/1S10
Com'l
70T633/1S12
Com'l
70T633/1S15
Com'l Only
& Ind(6)
& Ind
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
8
8
8
10
10
10
12
12
12
15
15
15
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
8
10
12
15
____
____
____
____
t
2.5
2.5
2.5
2.5
____
____
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
t
8
10
12
15
____
____
____
____
t
6
7
9
12
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
6
0
7
0
9
0
ns
ns
tWH
12
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
12
12
14
14
16
16
20
20
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5670 tbl 15
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2,3)
70T633/1S8
Com'l Only
70T633/1S10
Com'l
70T6331S12
Com'l
70T633/1S15
Com'l Only
& Ind
& Ind
Symbol
SLEEP MODE TIMING (ZZx=VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
)
____
____
____
____
____
____
____
____
____
____
____
____
t
ZZS
ZZR
ZZPD
ZZPU
Sleep Mode Set Time
8
8
10
10
12
12
15
15
t
Sleep Mode Reset Time
t
Sleep Mode Power Down Time(4)
Sleep Mode Power Up Time(4)
8
10
12
15
____
____
____
____
t
0
0
0
0
5670 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
4. This parameter is guaranteed by device characterization, but is not production tested.
16
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
tWC
MATCH
ADDR"A"
t
WP
R/W"A"
t
DH
t
DW
VALID
DATAIN "A"
(1)
APS
t
MATCH
ADDR"B"
t
BDA
t
BAA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
tDDD
.
5670 drw 14
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
t
WP
R/W"A"
(3)
WB
t
BUSY"B"
(1)
t
WH
(2)
R/W"B"
.
NOTES:
5670 drw 15
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB only applies to the slave mode.
17
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
(3)
CE"A"
(2)
tAPS
(3)
CE"B"
tBAC
tBDC
BUSY"B"
.
5670 drw 16
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1,3,4)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
t
BAA
t
BDA
BUSY"B"
5670 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.
4. CE0X = OEX = LBX = UBX = VIL. CE1X = VIH.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2)
70T633/1S8
Com'l Only
70T633/1S10
Com'l
70T633/1S12
Com'l
70T633/1S15
Com'l Only
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
0
ns
ns
ns
t
0
0
0
0
____
____
____
____
t
8
8
10
10
12
12
15
15
____
____
____
____
t
Interrupt Reset Time
ns
5670 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
18
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
t
WC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
(5)
(4)
tWR
t
AS
(3)
CE"A"
R/W"A"
INT"B"
(4)
t
INS
.
5670 drw 18
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
(4)
tAS
(3)
CE"B"
OE"B"
(4)
tINR
.
5670 drw 19
INT"B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (CE or R/W) is asserted last.
5. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
Right Port
(5)
(5)
R/W
L
L
A
18L-A0L
R/W
X
R
A
18R-A0R
Function
CE
L
OE
L
INT
L
CE
R
OE
R
INTR
(2)
L
X
X
L
X
X
X
L
7FFFF
X
X
X
L
L
X
X
L
X
L
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT Flag
R
Flag
(3)
X
X
X
7FFFF
7FFFE
X
H
R
Flag
(3)
X
X
L
L
X
X
X
L
(2)
X
7FFFE
H
X
X
L
5670 tbl 17
NOTES:
1. Assumes BUSYL = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.
19
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV —
AddressBUSY Arbitration
Inputs
Outputs
(4)
A
0L-A18L
(5)
(5)
(1)
(1)
A
0R-A18R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
H
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
MATCH
H
H
MATCH
(2)
(2)
(3)
Write Inhibit
5670 tbl 18
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70T633/1 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A18 is a NC for IDT70T631. Address comparison will be for A0 - A17.
5. CEX = L means CE0X = VIL and CE1X = VIH. CEX = H means CE0X = VIH and/or CE1X = VIL.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left
D0
- D17 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5670 tbl 19
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2.
3. CE0 = VIH, CE1 = SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 7FFFF. The
message(18bits)at7FFFEor7FFFF(3FFFFor3FFFEforIDT70T631)
isuser-definedsinceitisanaddressableSRAMlocation.Iftheinterrupt
functionisnotused, addresslocations7FFFEand7FFFFarenotused
asmailboxes,but aspartoftherandomaccessmemory.RefertoTruth
Table III forthe interruptoperation.
TheIDT70T633/1providestwoportswithseparatecontrol,address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T633/1 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
whennotselected(CE =HIGH). Whena portis enabled, access tothe
entirememoryarrayispermitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
20
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
andcorrupteddata inthe slave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether CMOS Static RAM with an additional 8 address locations dedicated to
anduse anyBUSY indicationas aninterruptsource toflagthe eventof binarysemaphoreflags.Theseflagsalloweitherprocessorontheleftor
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis right sideoftheDual-PortRAMtoclaimaprivilegeovertheotherprocessor
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave forfunctionsdefinedbythesystemdesigner’ssoftware.Asanexample,
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely the semaphore can be used by one processor to inhibit the
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying otherfromaccessingaportionoftheDual-PortRAMoranyothershared
the BUSY pins HIGH. If desired, unintended write operations can be resource.
prevented to a port by tying the BUSY pin for that port LOW.
The Dual-Port RAM features a fast access time, with both ports
The BUSY outputs on the IDT70T633/1 RAM in master mode, are being completely independent of each other. This means that the
push-pull type outputs and do not require pull up resistors to operate. activityontheleftportinnowayslows theaccess timeoftherightport.
Ifthese RAMs are beingexpandedindepth, thenthe BUSY indication Both ports are identical in function to standard CMOS Static RAM and
for the resulting array requires the use of an external AND gate.
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
featurecontrolledbyCE0andCE1,theDual-PortRAMchipenables,and
SEM,thesemaphoreenable.The CE0, CE1, andSEM pins controlon-
chippowerdowncircuitrythatpermitstherespectiveporttogointostandby
modewhennotselected.
Systems which can best use the IDT70T633/1 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the hardware
semaphores of the IDT70T633/1, which provide a lockout mechanism
withoutrequiringcomplexprogramming.
A
19
CE0
CE
0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
L
BUSYL
CE1
CE
1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
L
BUSY
L
BUSY
R
BUSY
R
.
5670 drw 20
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70T633/1 Dual-Port RAMs.
Softwarehandshakingbetweenprocessors offers themaximumin
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T633/1 does not use its semaphore
flags to control any resources through hardware, thus allowing the
systemdesignertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speedsystems.
Width Expansion with Busy Logic
Master/SlaveArrays
When expanding an IDT70T633/1 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T633/1 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration on a master is based on the chip enable and
21
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
usedinstead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,it
proceeds to assume control over the shared resource. If it was not
successfulinsettingthelatch,itdeterminesthattherightsideprocessor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquishedthetoken,theleftsideshouldsucceedingainingcontrol.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
sidewritesaonetothatlatch.
The eight semaphore flags reside within the IDT70T633/1 in a
separate memory space from the Dual-Port RAM array. This address
spaceisaccessedbyplacingalowinputontheSEM pin(whichactsas
a chip select for the semaphore flags) and using the other control pins
(Address,CE0,CE1,R/WandLB/UB)astheywouldbeusedinaccessing
astandardStaticRAM.Eachoftheflagshasauniqueaddresswhichcan
beaccessedbyeithersidethroughaddresspinsA0–A2.Whenaccessing
thesemaphores,noneoftheotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
Thatsemaphorecannowonlybemodifiedbythesideshowingthezero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the opposite side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
If the opposite side semaphore request latch has been written to
zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first request latch. The
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
5670 drw 21
Figure 4. IDT70T633/1 Semaphore Logic
fromtheothersideispending)andthencanbewrittentobybothsides. opposite side flag will now stay LOW until its semaphore request latch
The fact that the side which is able to write a zero into a semaphore is written to a one. From this it is easy to understand that, if a
subsequently locks out writes from the other side is what makes semaphore is requested and the processor which requested it no
semaphore flags useful in interprocessor communications. (A thor- longer needs the resource, the entire system can hang up until a one
ough discussion on the use of this feature follows shortly.) A zero iswrittenintothatsemaphorerequestlatch.
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by a single tokenbyattemptingtowrite a zerointoitatthe same time. The
thefirstside. semaphore logic is specially designed to resolve this problem. If
The critical case of semaphore timing is when both sides request
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso simultaneous requests are made, the logic guarantees that only one
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining side receives the token. If one side is earlier than the other in making
a zeroreads as allzeros fora semaphore read, theSEM, BEn, andOE the request, the first side to make the request will receive the token. If
signals needtobeactive.(PleaserefertoTruthTableII).Furthermore, bothrequests arriveatthesametime,theassignmentwillbearbitrarily
thereadvalueislatchedintooneside’soutputregisterwhenthatside's made to one port or the other.
semaphoreselect(SEM,BEn)andoutputenable(OE)signalsgoactive.
Thisservestodisallowthesemaphorefromchangingstateinthemiddle semaphores alone do not guarantee that access to a resource is
of a read cycle due to a write cycle from the other side. secure. As with any powerful programming technique, if semaphores
A sequence WRITE/READ must be used by the semaphore in are misusedormisinterpreted, a software errorcaneasilyhappen.
order to guarantee that no system level contention will occur. A Initialization of the semaphores is not automatic and must be
One caution that should be noted when using semaphores is that
processor requests access to shared resources by attempting to write handled via the initialization program at power-up. Since any sema-
a zero into a semaphore location. If the semaphore is already in use, phore request flag which contains a zero must be reset to a one,
the semaphore request latch will contain a zero, yet the semaphore all semaphores on both sides should have a one written into them
flag will appear as one, a fact which the processor will verify by the at initialization from both sides to assure that they will be free
subsequent read (see Table V). As an example, assume a processor when needed.
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
22
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
23
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
SleepMode
The IDT70T633/1 is equipped with an optional sleep or low power
modeonbothports.Thesleepmodepinonbothportsisactivehigh.During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will have the lowest possible power
consumption.Thesleepmodetimingdiagramdemonstratesthemodesof
operation:NormalOperation,NoRead/WriteAllowedandSleepMode.
Foraperiodoftime priortosleepmodeandafterrecoveringfromsleep
mode(tZZS andtZZR),newreadsorwritesarenotallowed.Ifawriteorread
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediatelyafterZZis asserted(priortobeinginsleep).
DuringsleepmodetheRAMautomaticallydeselectsitselfanddiscon-
nectsitsinternalbuffer.Alloutputswillremaininhigh-Zstatewhileinsleep
mode.Allinputsareallowedtotoggle,buttheRAMwillnotbeselectedand
will not perform any reads or writes.
JTAGTimingSpecifications
t
JCYC
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
TRST
x
5670 drw 23
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T633/1
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
____
____
t
ns
t
40
ns
(1)
____
t
3
ns
(1)
____
t
3
ns
____
____
t
50
ns
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
5. JTAG cannot be tested in sleep mode.
t
JTAG Hold
ns
5670 tbl 20
24
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
(1)
IDT Device ID (27:12)
Defines IDT part number 70T633
0x33B
0x33
1
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5670 tbl 21
NOTE:
1. Device ID for IDT70T631 is 0x33C.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5670 tbl 22
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
RESERVED
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
5670 tbl 23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
25
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(1)
Green
BC
BF
256-ball BGA (BC-256)
208-ball fpBGA (BF-208)
Commercial Only
8
10
12
15
Commercial & Industrial
Speed in nanoseconds
Commercial & Industrial
Commercial Only
S
Standard Power
70T633 9Mbit (512K x 18) 2.5V Asynchronous Dual-Port RAM
70T631 4Mbit (256K x 18) 2.5V Asynchronous Dual-Port RAM
5670 drw 24
NOTES:
1. Green parts available. For specific speeds, packages and poweres contact your local sales office.
26
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory:
04/25/03:
10/01/03:
InitialDatasheet
Page 9
Added8ns speedDCpowernumbers toDCElectricalCharacteristics Table
Page 9
Page 9,11,15,
17&25
UpdatedDCpowernumbers for10, 12&15ns speeds inthe DCElectricalCharacteristics Table
Addedfootnotethatindicates that8ns speedis availableinBF-208andBC-256packages only
Page 10
AddedCapacitanceDeratingDrawing
Page 11,15 & 17 Added8nsACtimingnumberstotheACElectricalCharacteristicsTables
Page 11
AddedtSOE andtLZOB totheACReadCycleElectricalCharacteristicsTable
AddedtLZOB tothe WaveformofReadCycles Drawing
AddedtSOE toTimingWaveformofSemaphoreReadafterWriteTiming,EitherSideDrawing
Added8ns speedgradeand10ns I-temptofeatures andtoorderinginformation
Page 12
Page 14
Page 1& 25
Page 1, 14 & 15 AddedRapidWriteModeWriteCycletextandwaveforms
10/20/03:
04/21/04:
01/05/06:
Page 15
CorrectedtARF to1.5V/nsMin.
RemovedPreliminarystatusfromentiredatasheet
Addedgreenavailabilitytofeatures
Addedgreenindicatortoorderinginformation
Corrected a typo in the DC Chars table
Removed "IDT" from orderable part number
Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01
Corrected 70T651/9 to 70T633/1
Page 1
Page 27
Page 9
Page 27
07/25/08:
01/19/09:
04/20/10:
10/15/11:
Page 2,13
Page 26
Updatedorderinginformationtoinclude tube ortrayandtape &reel.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
408-284-2794
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
27
相关型号：
72T631S12BFG
Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208
IDT
72T631S12BFGI
Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208
IDT
72T633S12BCG
Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
72T633S12BCGI
Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 HEIGHT, 1 MM PITCH, GREEN, BGA-256
IDT
©2020 ICPDF网 联系我们和版权申明