72V205L15PF8 [IDT]
TQFP-64, Reel;
| 型号： | 72V205L15PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-64, Reel |
| 文件： | 总25页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
IDT72V245
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FEATURES:
• 256 x 18-bit organization array (IDT72V205)
• 512 x 18-bit organization array (IDT72V215)
• 1,024 x 18-bit organization array (IDT72V225)
• 2,048 x 18-bit organization array (IDT72V235)
• 4,096 x 18-bit organization array (IDT72V245)
• 10 ns read/write cycle time
DESCRIPTION:
TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-
patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memorieswithclockedreadandwritecontrols. TheseFIFOsareapplicable
forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local
AreaNetworks(LANs),andinterprocessorcommunication.
• 5V input tolerant
• IDT Standard or First Word Fall Through timing
• Single or double register-buffered Empty and Full flags
• Easily expandable in depth and width
• Asynchronous or coincident Read and Write Clocks
• Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
• Half-Full flag capability
• Output enable puts output data bus in high-impedance state
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)
TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).
TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.
AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol
oftheoutput.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0-D17
LD
WEN
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
FLAG
WRITE CONTROL
LOGIC
EF/OR
PAE
LOGIC
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
HF/(WXO)
READ POINTER
WRITE POINTER
FL
WXI
READ CONTROL
LOGIC
EXPANSION LOGIC
(HF)/WXO
RXI
RXO
OUTPUT REGISTER
RESET LOGIC
RS
4294 drw 01
OE
REN
RCLK
Q0-Q17
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
MARCH 2013
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4294/7
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes
nothavetobeassertedforaccessingthefirstword.
These devices are depth expandable using a Daisy-Chain technique or
FirstWordFallThroughmode(FWFT).TheXIandXOpinsareusedtoexpand
theFIFOs.Indepthexpansionconfiguration,FirstLoad(FL)isgroundedon
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
high-speedsubmicronCMOStechnology.
DESCRIPTION(CONTINUED)
ThesynchronousFIFOshavetwofixedflags,EmptyFlag/OutputReady
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmableflagsiscontrolledbyasimplestatemachine,andisinitiatedby
assertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailablewhentheFIFO
isusedinasingledeviceconfiguration.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall-Through (FWFT) mode.
InIDTStandardMode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
PIN CONFIGURATIONS
PIN 1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D15
D14
D13
1
2
3
Q
Q
GND
14
13
48
47
46
D
D
D
D
D
D
D
D
D
D
D
D
D
12
11
10
4
5
6
7
8
9
10
11
12
13
14
15
16
Q
Q
12
11
45
44
43
42
41
40
39
38
37
36
VCC
9
Q10
8
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
7
6
5
4
3
2
35
34
33
1
0
VCC
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
4294 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
MARCH2013
2
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol
Name
I/O
Description
D0–D17 DataInputs
I
I
Datainputsforan18-bitbus.
RS
Reset
WhenRSissetLOW,internalreadandwritepointersaresettothefirstlocationoftheRAMarray,FFandPAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
WriteClock
I
I
WhenWENisLOW,dataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLK,iftheFIFOisnotfull.
WhenWENisLOW, dataiswrittenintotheFIFOonevery LOW-to-HIGHtransitionofWCLK. When WENis
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
WEN
WriteEnable
RCLK
ReadClock
I
I
WhenRENisLOW,dataisreadfromtheFIFOonaLOW-to-HIGHtransitionofRCLK,iftheFIFOisnotempty.
WhenRENisLOW,dataisreadfromtheFIFOoneveryLOW-to-HIGHtransitionofRCLK. WhenRENisHIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
REN
Read Enable
OE
LD
OutputEnable
Load
I
I
WhenOEisLOW,thedataoutputbusisactive.IfOEisHIGH,theoutputdatabuswillbeinahigh-impedance
state.
WhenLDisLOW,dataontheinputsD0–D11iswrittentotheoffsetanddepthregistersontheLOW-to-HIGH
transitionoftheWCLK, whenWENisLOW. WhenLDisLOW, dataontheoutputsQ0–Q11isreadfromthe
offsetanddepthregistersontheLOW-to-HIGHtransitionoftheRCLK, whenRENisLOW.
FL
FirstLoad
I
I
Inthesingledeviceorwidthexpansionconfiguration, FLtogetherwithWXIandRXI determineifthemodeis
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, FL is
grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXI
RXI
FF/IR
WriteExpansion
Input
In thesingledeviceorwidthexpansionconfiguration, WXI togetherwith FLandRXI determineifthemode
isIDTStandardmodeorFWFTmode,aswellas whetherthePAE/PAFflagsaresynchronousorasynchronous.
(SeeTable1.) IntheDaisyChainDepthExpansionconfiguration,WXIisconnectedtoWXO(WriteExpansion
Out) of the previous device.
Read Expansion
Input
I
Inthesingledeviceorwidthexpansionconfiguration, RXI togetherwithFLandWXI, determineifthemode
isIDTStandardmodeorFWFTmode,aswellas whetherthePAE/PAFflagsaresynchronousorasynchronous.
(SeeTable1.) IntheDaisyChainDepthExpansionconfiguration,RXIisconnectedtoRXO(ReadExpansion
Out) of the previous device.
Full Flag/
Input Ready
O
IntheIDTStandardmode,theFFfunctionisselected.FFindicateswhetherornottheFIFOmemoryisfull.In
theFWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailableforwritingto
theFIFOmemory.
EF/OR
EmptyFlag/
OutputReady
O
O
IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
InFWFTmode,theORfunctionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
WhenPAEisLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetis31fromemptyforIDT72V205,63fromemptyforIDT72V215,and127fromemptyforIDT72V225/
72V235/72V245.
PAE
Programmable
Almost-EmptyFlag
PAF
Programmable
Almost-FullFlag
O
O
WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffsetat
resetis31fromfullforIDT72V205,63fromfullforIDT72V215,and127fromfullforIDT72V225/72V235/72V245.
WXO/HF WriteExpansion
Inthesingledeviceorwidthexpansionconfiguration,thedeviceismorethanhalffullwhenHFisLOW.Inthe
depthexpansionconfiguration,apulseissentfromWXOtoWXIofthenextdevicewhenthelastlocationinthe
FIFOiswritten.
Out/Half-FullFlag
RXO
Read Expansion
Out
O
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last
location in the FIFO is read.
Q0–Q17 DataOutputs
Dataoutputsforan18-bitbus.
+3.3V power supply pins.
Seven ground pins.
VCC
Power
GND
Ground
3
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Min.
Typ.
Max. Unit
VTERM(2)
TerminalVoltage
–0.5 to +5
V
VCC
SupplyVoltage
3.0
3.3
3.6
V
with respect to GND
Commercial/Industrial
TSTG
Storage
Temperature
–55to+125
–50to+50
°C
GND
VIH
SupplyVoltage
0
0
0
V
V
InputHighVoltage
2.0
—
5.5
IOUT
DCOutputCurrent
mA
Commercial/Industrial
NOTES:
VIL(1)
TA
InputLowVoltage
Commercial/Industrial
-0.5
0
—
—
0.8
70
85
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OperatingTemperature
Commercial
°C
°C
TA
OperatingTemperature
Industrial
-40
⎯
2. VCC terminal only.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V 0.3V, TA = -40°C to +85°C)
IDT72V205
IDT72V215
IDT72V225
IDT72V235
IDT72V245
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
–1
Typ.
—
Max.
1
Unit
(2)
ILI
InputLeakageCurrent(anyinput)
OutputLeakageCurrent
μA
μA
V
(3)
ILO
–10
2.4
—
—
10
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
—
0.4
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
—
—
30
5
mA
mA
(4.7)
ICC2
NOTES:
1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. Typical ICC1 = 2.04 + 0.88*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
MARCH2013
4
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Commercial
Com'l & Ind'l(1)
Commercial
IDT72V205L10
IDT72V215L10
IDT72V225L10
IDT72V235L10
IDT72V245L10
IDT72V205L15
IDT72V215L15
IDT72V225L15
IDT72V235L15
IDT72V245L15
IDT72V205L20
IDT72V215L20
IDT72V225L20
IDT72V235L20
IDT72V245L20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
Min.
—
2
Max.
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
22
12
22
12
22
12
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
100
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
tA
DataAccessTime
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
20
8
Clock HIGH Time
Clock LOW Time
6
8
DataSet-upTime
4
5
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tRS
EnableSet-upTime
4
5
EnableHoldTime
ResetPulseWidth(2)
0.5
10
8
1
1
15
10
10
—
0
20
12
12
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
ResetSet-upTime
ResetRecoveryTime
8
ResettoFlagandOutputTime
OutputEnabletoOutputinLow-Z(3)
OutputEnabletoOutputValid
OutputEnabletoOutputinHigh-Z(3)
Write Clock to Full Flag
—
0
—
1
3
3
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
6
3
8
3
—
—
—
—
—
—
—
—
3
6.5
6.5
17
8
—
—
—
—
—
—
—
—
6.5
5
10
10
20
10
20
10
20
10
—
—
—
—
—
—
—
—
—
—
—
8
Read Clock to Empty Flag
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to Half-Full Flag
17
8
17
6.5
—
—
—
tXO
Clock to Expansion Out
tXI
Expansion In Pulse Width
tXIS
Expansion In Set-Up Time
3
8
tSKEW1
Skew time between Read Clock & Write Clock for FF/IR
and EF/OR
5
6
8
(4)
tSKEW2
Skew time between Read Clock & Write Clock for PAE
and PAF
14
—
18
—
20
—
ns
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous PAE and synchronous PAF only.
3.3V
330Ω
D.U.T.
30pF*
AC TEST CONDITIONS
510Ω
Input Pulse Levels
GND to 3.0V
3ns
1.5V
1.5V
SeeFigure1
4294 drw 03
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
OutputLoad
Figure 1. Output Load
Includes jig and scope capacitances.
*
5
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
72V245. ContinuingreadoperationswillcausetheFIFOtobeempty. When
thelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibitingfurther
read operations. REN is ignored when the FIFO is empty.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
FIRST WORD FALL THROUGH MODE (FWFT)
TheIDT72V205/72V215/72V225/72V235/72V245supporttwodifferent
timing modes of operation. The selection of which mode will operate is
determinedduringconfigurationatReset(RS).Duringa RSoperation,theFirst
Load(FL),ReadExpansionInput(RXI),andWriteExpansionInput(WXI)pins
areusedtoselectthetimingmodeperthetruthtableshowninTable3.InIDT
StandardMode,thefirstwordwrittentoanemptyFIFOwillnotappearonthe
dataoutputlinesunlessaspecificreadoperationisperformed.Areadoperation,
which consists of activating Read Enable (REN) and enabling a rising Read
Clock(RCLK)edge,willshiftthewordfrominternalmemorytothedataoutput
lines.InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes
nothavetobeassertedforaccessingthefirstword.
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable2.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 130th
(72V205), 258th(72V215),514th(72V225),1,026th(72V235),and2,050th
(72V245)wordrespectivelywaswrittenintotheFIFO. Continuingtowritedata
intotheFIFOwillcausethePAFtogoLOW.Again,ifnoreadsareperformed,
the PAFwillgoLOWafter(257-m)writesfortheIDT72V205, (513-m)writes
fortheIDT72V215,(1,025-m)writesfortheIDT72V225,(2,049–m)writesfor
the IDT72V235 and (4,097–m) writes for the IDT72V245, where m is the full
offsetvalue. ThedefaultsettingforthisvalueisstatedinthefootnoteofTable
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable1.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
2.
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
DwritestotheFIFO. D=257writesfortheIDT72V205,513fortheIDT72V215,
1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the
IDT72V245.NotethattheadditionalwordinFWFTmodeisduetothecapacity
ofthememoryplusoutputregister.
IftheFIFOisfull, thefirstreadoperationwillcausethe IRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable2.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.Ifthereisnoemptyoffsetspecified,thePAEwillbe
LOWwhenthedeviceis32awayfromcompletelyemptyforIDT72V205, 64
awayfromcompletelyemptyforIDT72V215,and128awayfromcompletely
emptyforIDT72V225/72V235/72V245.Continuingreadoperationswillcause
the FIFO to be empty. When the last word has been read from the FIFO, OR
willgoHIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFO
isempty.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-FullFlag(HF)wouldtoggletoLOWonce
the129th(72V205), 257th(72V215),513th(72V225),1,025th(72V235),and
2,049th(72V245)wordrespectivelywaswrittenintotheFIFO. Continuingto
writedataintotheFIFOwillcausetheProgrammableAlmost-FullFlag(PAF)
togoLOW.Again,ifnoreadsareperformed, thePAFwillgoLOWafter(256-m)
writesfortheIDT72V205,(512-m)writesfortheIDT72V215,(1,024-m)writes
fortheIDT72V225,(2,048-m)writesfortheIDT72V235and(4,096–m)writes
fortheIDT72V245. Theoffset“m”isthefulloffsetvalue. Thisparameterisalso
userprogrammable.SeesectiononProgrammableFlagOffsetLoading. Ifthere
isnofulloffsetspecified,thePAFwillbeLOWwhenthedeviceis31awayfrom
completelyfullforIDT72V205,63awayfromcompletelyfullforIDT72V215,and
127awayfromcompletelyfullfor theIDT72V225/72V235/72V245.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
totheFIFO. D=256writesfortheIDT72V205,512fortheIDT72V215,1,024
for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245,
respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandtheHalf-FullFlag(HF)togo
HIGHattheconditionsdescribedinTable1.Iffurtherreadoperationsoccur,
withoutwriteoperations,theProgrammableAlmost-EmptyFlag(PAE)willgo
LOW when there are n words in the FIFO, where n is the empty offset value.
Ifthereisnoemptyoffsetspecified,thePAEwillbeLOWwhenthedeviceis31
awayfromcompletelyemptyforIDT72V205,63awayfromcompletelyempty
forIDT72V215,and127awayfromcompletelyemptyforIDT72V225/72V235/
PROGRAMMABLEFLAGLOADING
FullandEmptyflagoffsetvaluescanbeuserprogrammable.TheIDT72V205/
72V215/72V225/72V235/72V245 has internal registers for these offsets.
DefaultsettingsarestatedinthefootnotesofTable1andTable2.Offsetvalues
areloadedintotheFIFOusingthedatainputlinesD0-D11. Toloadtheoffset
registers,theLoad(LD)pinandWENpinmustbeheldLOW.Datapresenton
D0-D11willbetransferredintotheEmptyOffsetregisteronthefirstLOW-to-HIGH
transitionofWCLK.BycontinuingtoholdtheLDandWENpinlow, datapresent
onD0-D11 willbetransferredintotheFullOffsetregisteronthenexttransition
oftheWCLK.ThethirdtransitionagainwritestotheEmptyOffsetregister. Writing
alloffsetregistersdoesnothavetooccuratonetime.Oneortwooffsetregisters
can be written and then by bringing the LD pin HIGH, the FIFO is returned to
normalread/writeoperation. WhentheLDpinandWENareagainsetLOW,
thenextoffsetregisterinsequenceiswritten.
MARCH2013
6
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ThecontentsoftheoffsetregisterscanbereadonthedataoutputlinesQ0-
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
Q11 whentheLDpinissetLOWandRENissetLOW. Datacanthenberead updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
onthenextLOW-to-HIGHtransitionofRCLK. ThefirsttransitionofRCLKwill assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Fordetail
presenttheemptyoffsetvaluetothedataoutputlines.ThenexttransitionofRCLK timingdiagrams,seeFigure22forsynchronousPAEtimingandFigure23for
willpresentthefulloffsetvalue.OffsetregistercontentcanbereadoutintheIDT synchronousPAFtiming.
Standard mode only. It cannot be read in the FWFT mode.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
The IDT72V205/72V215/72V225/72V235/72V245 can be configured
duringthe"ConfigurationatReset"cycledescribedinTable4withsingle,double
The IDT72V205/72V215/72V225/72V235/72V245 can be configured ortripleregister-bufferedflagoutputsignals.Thevariouscombinationsavail-
during the "Configuration at Reset" cycle described in Table 3 with either able are described in Table 4 and Table 5. In general, going from single to
asynchronous or synchronous timing for PAE and PAF flags.
doubleortriplebufferedflagoutputsremovesthepossibilityofmetastableflag
If asynchronous PAE/PAF configurationisselected(asperTable3), the indicationsonboundarystates(i.e,emptyorfullconditions).Thetrade-offisthe
PAEisassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresetto addition of clock cycle delays for the respective flag to be asserted. Not all
HIGHontheLOW-to-HIGHtransitionofWCLK.Similarly,thePAFisasserted combinationsof register-bufferedflagoutputsaresupported.Register-buffered
LOWontheLOW-to-HIGHtransitionofWCLKandPAFisresettoHIGHonthe outputsapplytotheEmptyFlagandFullFlagonly. Partialflagsarenoteffected.
LOW-to-HIGHtransitionofRCLK.Fordetailtimingdiagrams,seeFigure13for Table 4 and Table 5 summarize the options available.
asynchronous PAE timingandFigure14forasynchronous PAFtiming.
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO
IDT72V205
IDT72V215
IDT72V225
IDT72V235
IDT72V245
FF PAF HF PAE EF
0
0
1 to n(1)
0
0
1 to n(1)
0
1 to n(1)
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
(n + 1) to 128
129 to (256-(m+1))(2)
(256-m)to255
(n + 1) to 256
257 to (512-(m+1))(2)
(512-m)to511
512
(n + 1) to 512
513 to (1,024-(m+1))(2)
(1,024-m)to1,023
1,024
(n + 1) to 1,024
1,025 to (2,048-(m+1))(2)
(2,048-m)to2,047
2,048
(n + 1) to 2,048
2,049 to (4,096-(m+1))(2)
(4,096-m)to4,095
4,096
H
H
H
H
L
256
L
L
NOTES:
1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127)
2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127)
TABLE 2 — STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO
IDT72V205
IDT72V215
IDT72V225
IDT72V235
IDT72V245
IR PAF HF PAE OR
0
0
1 to (n + 1)(1)
(n + 2) to 257
258 to (513-(m+1))(2)
(513-m) to 512
513
0
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to (n + 1)(1)
1 to (n + 1)(1)
(n + 2) to 513
514 to (1,025-(m+1))(2)
(1,025-m) to 1,024
1,025
1 to (n + 1)(1)
1 to (n + 1)(1)
(n + 2) to 129
130 to (257-(m+1))(2)
(257-m) to 256
(n + 2) to 1,025
1,026 to (2,049-(m+1))(2)
(2,049-m) to 2,048
2,049
(n + 2) to 2,049
2,050 to (4,097-(m+1))(2)
(4,097-m) to 4,096
4,097
H
H
H
H
L
257
L
L
NOTES:
1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127)
2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127)
7
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
FL
RXI
WXI
EF/OR
FF/IR
PAE, PAF
FIFO Timing Mode
0
0
0
Singleregister-buffered
EmptyFlag
Singleregister-buffered
Full Flag
Asynchronous
Standard
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Tripleregister-buffered
Output Ready Flag
Doubleregister-buffered
EmptyFlag
Singleregister-buffered
EmptyFlag
Singleregister-buffered
EmptyFlag
Tripleregister-buffered
Output Ready Flag
Doubleregister-buffered
EmptyFlag
Singleregister-buffered
EmptyFlag
Doubleregister-buffered
Input Ready Flag
Doubleregister-buffered
Full Flag
Singleregister-buffered
Full Flag
Singleregister-buffered
Full Flag
Doubleregister-buffered
Input Ready Flag
Doubleregister-buffered
Full Flag
Singleregister-buffered
Full Flag
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
FWFT
0
Standard
Standard
Standard
FWFT
0(1)
1
1
1
Standard
Standard
1(2)
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the
preceding device.
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding
RXO and WXO outputs of the preceding device.
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD
MODE
Empty Flag (EF)
Buffered Output
Full Flag (FF)
Buffered Output
Partial Flags
Timing Mode
Programming at Reset
Flag Timing
Diagrams
FL
RXI
WXI
Single
Single
Single
Single
Asynch
Sync
0
1
0
1
0
0
Figure 9, 10
Figure 9, 10
Figure 24, 26
Figure 24, 26
0
1
1
0
Double
Double
Double
Double
Asynch
Synch
0
0
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
Output Ready (OR)
Input Ready (IR)
Partial Flags
Programming at Reset
Flag Timing
Diagrams
FL
RXI
WXI
Triple
Triple
Double
Double
Asynch
Sync
0
1
0
1
1
Figure 27
0
Figure 20, 21
MARCH2013
8
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW
afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess
allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH
transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrue read(RCLKwithREN=LOW),inhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
SIGNALDESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Datainputsfor18-bitwidedata.
CONTROLS:
RESET (RS)
OUTPUTENABLE(OE)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW
state. During reset, both internal read and write pointers are set to the first
location. Aresetisrequiredafterpower-upbeforeawriteoperationcantake
place.TheHalf-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)will
beresettoHIGHaftertRSF.TheProgrammableAlmost-EmptyFlag(PAE)will
beresettoLOWaftertRSF. TheFullFlag (FF)willresettoHIGH. TheEmpty
Flag(EF)willresettoLOWinIDTStandardmodebutwillresettoHIGHinFWFT
mode. Duringreset,theoutputregisterisinitializedtoallzerosandtheoffset
registersareinitializedtotheirdefaultvalues.
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput
databusisinahigh-impedancestate.
LOAD (LD)
The IDT72V205/72V215/72V225/72V235/72V245 devices contain two
12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs. Whenthe
Load(LD)pinissetLOWandWENissetLOW,dataontheinputsD0-D11is
writtenintotheEmptyOffsetregisteronthefirstLOW-to-HIGHtransitionofthe
Write Clock (WCLK). When the LD pin and WEN are held LOW then data is
writtenintotheFullOffsetregisteronthesecondLOW-to-HIGHtransitionof
WCLK.ThethirdtransitionofWCLKagainwritestotheEmptyOffsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime.One
ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the
FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,
andWENisLOW,thenextoffsetregisterinsequenceiswritten.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FFwillgoHIGHallowingawritetooccur. TheFFflagisupdatedontherising
edgeofWCLK.
LD
WEN
WCLK
Selection
Writingtooffsetregisters:
EmptyOffset
0
0
FullOffset
0
1
1
1
0
1
NoOperation
WriteIntoFIFO
NoOperation
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle, IRwillgo
LOWallowingawritetooccur. TheIRflagisupdatedontherisingedgeofWCLK.
NOTE:
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
READ CLOCK (RCLK)
Figure 2. Writing to Offset Registers
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
17
0
11
EMPTY OFFSET REGISTER
READ ENABLE (REN)
DEFAULT VALUE
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
11
17
0
FULL OFFSET REGISTER
IntheIDTStandardmode, everywordaccessedatQn, includingthefirst
wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
furtherreadoperations. RENisignoredwhentheFIFOisempty. Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
on the rising edge of RCLK.
DEFAULT VALUE
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
4294 drw 04
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
9
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WhentheLDpinisLOWandWENisHIGH,theWCLKinputisdisabled; PROGRAMMABLE ALMOST-FULL FLAG (PAF)
thenasignalatthisinputcanneitherincrementthewriteoffsetregisterpointer,
nor execute a write.
The Programmable Almost-Full Flag (PAF) will go LOW when FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhen performedafterReset(RS),thePAFwillgoLOWafter(256-m)writesforthe
theLDpinissetLOWandRENissetLOW;then,datacanbereadontheLOW- IDT72V205, (512-m) writes for the IDT72V215, (1,024-m) writes for the
to-HIGHtransitionoftheReadClock(RCLK).Theactofreadingthecontrol IDT72V225,(2,048–m)writesfortheIDT72V235and(4,096–m)writesforthe
registersemploysadedicatedreadoffsetregisterpointer.(Thereadandwrite IDT72V245. Theoffset“m”isdefinedintheFullOffsetregister.
pointersoperateindependently). Offsetregistercontentcanbereadoutinthe
IDT Standard mode only. It is inhibited in the FWFT mode.
In FWFT mode, if no reads are performed, PAF will go LOW after 257-m
fortheIDT72V205,513-mfortheIDT72V215,1,025fortheIDT72V225,2,049
A readandawriteshouldnotbeperformedsimultaneouslytotheoffset fortheIDT72V235and4,097fortheIDT72V245.Thedefaultvaluesformare
registers.
noted in Table 1 and 2.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).IfsynchronousPAF
configurationisselected(seeTable3),thePAFisupdatedontherisingedge
ofWCLK.
FIRST LOAD (FL)
Forthesingledevicemode,seeTable3foradditionalinformation. Inthe
DaisyChainDepthExpansionconfiguration,FLisgroundedtoindicateitisthe
firstdeviceloadedandissettoHIGHforallotherdevicesintheDaisyChain.
(SeeOperatingConfigurationsforfurtherdetails.)
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
The PAE flag will go LOW when the FIFO reaches the almost-empty
condition. In IDT Standard mode, PAE will go LOW when there are n words
orlessintheFIFO. InFWFTmode,thePAEwillgoLOWwhentherearen + 1
wordsorlessintheFIFO.Theoffset"n"isdefinedastheemptyoffset. Thedefault
values for n are noted in Table 1 and 2.
WRITE EXPANSION INPUT (WXI)
This is a dual purpose pin. For single device mode, see Table 3 for
additionalinformation. WXIisconnectedtoWriteExpansionOut(WXO)ofthe
previous device in the Daisy Chain Depth Expansion mode.
Ifthereisnoemptyoffsetspecified,theProgrammableAlmost-EmptyFlag
(PAE) will be LOW when the device is 31 away from completely empty for
IDT72V205, 63 away from completely empty for IDT72V215, and 127 away
fromcompletelyemptyforIDT72V225/72V235/72V245.
READ EXPANSION INPUT (RXI)
This is a dual purpose pin. For single device mode, see Table 3 for
additionalinformation.RXIisconnectedtoReadExpansionOut(RXO)ofthe
previous device in the Daisy Chain Depth Expansion mode.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOWon
theLOW-to-HIGHtransitionoftheReadClock(RCLK).PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).IfsynchronousPAE
configurationisselected(seeTable3),thePAEisupdatedontherisingedge
ofRCLK.
OUTPUTS:
FULL FLAG/INPUT READY (FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
functionisselected.WhentheFIFOisfull,FFwillgoLOW,inhibitingfurtherwrite
operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed
afterareset,FFwillgoLOWafterDwritestotheFIFO. D=256writesforthe
IDT72V205,512fortheIDT72V215,1,024fortheIDT72V225,2,048forthe
IDT72V235 and 4,096 for the IDT72V245.
InFWFTmode,theInputReady(IR)functionisselected. IRgoesLOW
whenmemoryspaceisavailableforwritingindata. When thereisnolonger
anyfreespaceleft, IRgoesHIGH,inhibitingfurtherwriteoperations.
IRwillgoHIGHafterDwritestotheFIFO. D=257writesfortheIDT72V205,
513fortheIDT72V215, 1,025fortheIDT72V225, 2,049fortheIDT72V235
and 4,097 for the IDT72V245. Note that the additional word in FWFT mode
isduetothecapacityofthememoryplusoutputregister.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
Thisisadual-purposeoutput. IntheSingleDeviceandWidthExpansion
mode, when Write Expansion In (WXI) and/or Read Expansion In (RXI) are
grounded,thisoutputactsasanindicationofahalf-fullmemory.
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext
writecycle,theHalf-FullFlaggoesLOWandwillremainsetuntilthedifference
betweenthewritepointerandreadpointerislessthanorequaltoonehalfof
thetotalmemoryofthedevice. TheHalf-FullFlag(HF)isthenresettoHIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
IntheDaisyChainDepthExpansion mode, WXIisconnectedtoWXOof
thepreviousdevice. ThisoutputactsasasignaltothenextdeviceintheDaisy
Chainbyprovidingapulsewhenthepreviousdevicewritestothelastlocation
ofmemory.
FF/IR is synchronous and updated on the rising edge of WCLK.
EMPTYFLAG/OUTPUTREADY(EF/OR)
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
read operations. When EF is HIGH, the FIFO is not empty.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith
atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
indicating the last word was read. Further data reads are inhibited until OR
goesLOWagain.
READ EXPANSION OUT (RXO)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(RXI)isconnectedtoReadExpansionOut(RXO)ofthepreviousdevice.This
outputactsasasignaltothenextdeviceintheDaisyChainbyprovidingapulse
whenthepreviousdevicereadsfromthelastlocationofmemory.
DATAOUTPUTS(Q0-Q17)
Q0-Q17 aredataoutputsfor18-bitwidedata.
EF/OR is synchronous and updated on the rising edge of RCLK.
MARCH2013
10
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
RS
tRSR
REN, WEN, LD
FL, RXI, WXI (1)
t
RSS
tRSR
CONFIGURATION SETTING
RCLK, WCLK (2)
FF/IR
(4)
t
RSF
IDT Standard Mode
FWFT Mode
t
RSF
FWFT Mode
EF/OR
IDT Standard Mode
t
RSF
PAF, WXO/
HF, RXO
t
RSF
PAE
t
RSF
OE = 1(3)
Q0 - Q17
4294 drw 05
OE = 0
NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
4. In FWFT mode IR goes LOW based on the WCLK edge after Reset.
Figure 5. Reset Timing(2)
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0
- D17
DATA IN VALID
tENH
tENS
NO OPERATION
WEN
FF
tWFF
tWFF
(1)
tSKEW1
RCLK
4294 drw 06
REN
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)
11
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
RCLK
REN
EF
tENS
tENH
NO OPERATION
t
REF
tREF
tA
Q0
- Q17
OE
VALID DATA
tOLZ
tOHZ
tOE
(1)
SKEW1
t
WCLK
WEN
4294 drw 07
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
WCLK
tDS
(first valid write)
D0
- D17
D0
D1
D2
D3
D4
tENS
WEN
(1)
tFRL
tSKEW1
RCLK
tREF
EF
tENS
REN
tA
tA
Q0
- Q17
D0
D1
tOLZ
tOE
OE
4294 drw 08
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The
Latency Timing applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
MARCH2013
12
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NO WRITE
NO WRITE
(1)
WCLK
(1)
SKEW1
t
tSKEW1
tDS
tDS
DATA
WRITE
D0
- D17
DATA WRITE
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
OE
LOW
tA
tA
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4294 drw 09
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
WCLK
tDS
tDS
DATA WRITE 1
DATA WRITE 2
D0
- D17
tENS
tENS
tENH
tENH
WEN
(1)
(1)
FRL
tFRL
t
tSKEW1
tSKEW1
RCLK
t
REF
t
REF
t
REF
EF
REN
OE
LOW
tA
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
4294 drw 10
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The
Latency Timing apply only at the Empty Boundary (EF = LOW).
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
13
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0 - D15
4294 drw 11
PAE OFFSET
PAF OFFSET
D0 - D11
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
tENS
REN
tA
PAE OFFSET
Q0
- Q15
UNKNOWN
PAE OFFSET
PAF OFFSET
4294 drw 12
Figure 12. Read Programmable Registers (IDT Standard Mode)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
(2)
n words in FIFO
n + 1 words in FIFO
,
n+1wordsinFIFO
,
PAE
RCLK
REN
(3)
(3)
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
4294 drw 13
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
MARCH2013
14
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words in FIFO(1)
D - (m + 1) words
in FIFO
tPAFA
RCLK
tENS
REN
4294 drw 14
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(2),
D/2 words in FIFO(2)
D-1
2
,
D/2 words in FIFO(2)
D-1
2
,
D-1
[
+ 2]
words in FIFO(3)
2
[
+ 1
]
words in FIFO(3)
[
+ 1
words in FIFO(3)
]
tHF
RCLK
tENS
REN
4294 drw 15
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
15
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLKH
WCLK
Note 1
tXO
tXO
WXO
WEN
tENS
4294 drw 16
NOTE:
1. Write to Last Physical Location.
Figure 16. Write Expansion Out Timing
tCLKH
RCLK
Note 1
tXO
tXO
RXO
REN
tENS
4294 drw 17
NOTE:
1. Read from Last Physical Location.
Figure 17. Read Expansion Out Timing
tXI
WXI
tXIS
WCLK
4294 drw 18
Figure 18. Write Expansion In Timing
tXI
RXI
tXIS
RCLK
4294 drw 19
Figure 19. Read Expansion In Timing
MARCH2013
16
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
17
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH2013
18
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
PAE
n words in FIFO(2)
,
n Words in FIFO(2),
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
n + 1words in FIFO(3)
n + 1 words in FIFO(3)
(4)
t
PAES
tSKEW2
t
PAES
RCLK
tENH
tENS
4294 drw 22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK
and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAFS
t
tPAFS
D - (m + 1) Words
in FIFO
D - (m + 1) Words in FIFO
PAF
D - m Words in FIFO
(3)
tSKEW2
RCLK
tENH
tENS
4294 drw 23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
19
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
(1)
SKEW1
tDS
tDS
t
t
DATA WRITE
Wd
D0
- D17
FF
t
WFF
tWFF
t
WFF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
tA
NEXT DATA READ
DATA IN OUTPUT REGISTER
DATA READ
Q0
- Q17
4294 drw 24
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
tCLK
t
CLKH
tCLKL
1
2
WCLK
tDS
tDH
D0
-
D17
DATA IN VALID
ENS
tENH
t
NO OPERATION
WEN
FF
t
WFF
t
WFF
(1)
tSKEW1
RCLK
REN
4294 drw 25
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)
MARCH2013
20
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
1
2
RCLK
tENH
tENS
NO OPERATION
REN
EF
t
REF
tREF
tA
Q0
-
Q17
LAST WORD
tOLZ
tOHZ
tOE
OE
(1)
SKEW1
t
WCLK
tENH
tENS
WEN
tDH
tDS
FIRST WORD
D0
-
D17
4294 drw 26
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing)
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
W[n+3]
W4
W[n +2]
W1
W2
W3
D0 - D17
(1)
tSKEW1
2
1
RCLK
3
REN
tA
Q0 - Q17
DATA IN OUTPUT REGISTER
W1
tREF
tREF
4294 drw 27
OR
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and
the rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
21
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
These FIFOs are in a single Device Configuration when the First Load (FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
OPERATINGCONFIGURATIONS
SINGLE DEVICE CONFIGURATION
AsingleIDT72V205/72V215/72V225/72V235/72V245maybeusedwhen
theapplicationrequirementsarefor256/512/1,024/2,048/4,096wordsorless.
RESET (RS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
72V205
72V215
72V225
72V235
72V245
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
FL
RXI
WXI
4294 drw 28
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
29demonstratesa36-wordwidthbyusingtwoIDT72V205/72V215/72V225/
72V235/72V245s. Any word width can be attained by adding additional
IDT72V205/72V215/72V225/72V235/72V245s. TheseFIFOsareinasingle
DeviceConfigurationwhentheFirstLoad(FL),WriteExpansionIn(WXI)and
Read Expansion In (RXI) control inputs are configured as (FL, RXI,
WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure
29). Please see the Application Note AN-83.
Word width may be increased simply by connecting together the control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEmptyFlag/OutputReadyandFullFlag/InputReady.
BecauseofvariationsinskewbetweenRCLKandWCLK,itispossibleforflag
assertion and deassertion to vary by one cycle between FIFOs. To avoid
problemstheusermustcreatecompositeflagsbygatingtheEmptyFlags/Output
ReadyofeveryFIFO,andseparatelygatingallFullFlags/InputReady. Figure
RESET (RS)
RESET (RS)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
LOAD (LD)
72V205
72V215
72V225
72V235
72V245
PROGRAMMABLE (PAF)
72V205
72V215
72V225
72V235
72V245
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
EMPTY FLAG/OUTPUT
READY (EF/OR)
FF/IR
EF/OR
FF/IR
EF/OR
18
DATA OUT (Q)
36
FULL FLAG/INPUT
READY (FF/IR)
FL WXI RXI
FL WXI RXI
18
4294 drw 29
NOTE:
1. Do not connect any output control signals directly together.
Figure 29. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
MARCH2013
22
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using three IDT72V205/72V215/72V225/72V235/72V245s.
Maximumdepthislimitedonlybysignalloading.
Followthesesteps:
1. The first device must be designated by grounding the First Load (FL)
control input.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 30.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
togethereveryrespectiveflags formonitoring.ThecompositePAE
and PAF flags are not precise.
8. InDaisyChainmode, theflagoutputsaresingleregister-bufferedand
thepartialflagsareinasynchronoustimingmode.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO)pinofeachdevicemustbetiedto
the Write Expansion In (WXI) pin of the next device. See Figure 30.
WXO RXO
WCLK
WEN
RS
RCLK
REN
OE
LD
IDT
72V205
72V215
72V225
72V235
72V245
Dn
Qn
Vcc
FL
FF/IR
EF/OR
PAF
PAE
WXI RXI
WXO RXO
WCLK
WEN
RS
RCLK
REN
OE
LD
IDT
72V205
72V215
72V225
72V235
72V245
Dn
DATA OUT
DATA IN
Qn
Vcc
FL
FF/IR
EF/OR
PAE
PAF
WXI RXI
RXO
WXO
WCLK
WRITE CLOCK
WRITE ENABLE
RESET
READ CLOCK
RCLK
WEN
REN
READ ENABLE
OUTPUT ENABLE
RS
OE
Dn
Qn
IDT
72V205
72V215
72V225
72V235
72V245
LD
LOAD
EF/OR
FF/IR
FF/IR
EF/OR
PAE
PAF
PAE
RXI
PAF
WXI
FIRST LOAD (FL)
4294 drw 30
Figure 30. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
23
MARCH2013
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The“rippledown”delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill“bubbleup”fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO’sIRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sum of the delays for each individual FIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
InFWFTmode,theFIFOscanbeconnectedinseries(thedataoutputsof
one FIFO connected to the data inputs of the next) with no external logic
necessary. Theresultingconfigurationprovidesatotaldepthequivalenttothe
sumofthedepthsassociatedwitheachsingleFIFO. Figure31showsadepth
expansionusingtwoIDT72V205/72V215/72V225/72V235/72V245devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext(“rippledown”)untilitfinally
appears at the outputs of the last FIFO in the chain–no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device’s OR line goes LOW,
enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO’s
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
(N – 1)*(4*transfer clock) + 3*TRCLK
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod. isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
Note that extra cycles should be added for the possibility that the tSKEW1 endofthechainandfreelocationstothebeginningofthechain.
HF
HF
PAF
PAE
TRANSFER CLOCK
WRITE CLOCK
WRITE ENABLE
INPUT READY
READ CLOCK
READ ENABLE
OUTPUT READY
WCLK
WEN
IR
RCLK
WCLK
RCLK
OR
WEN
REN
72V205
72V215
72V225
72V235
72V245
72V205
72V215
72V225
72V235
72V245
REN
OE
OR
OE
Qn
IR
OUTPUT ENABLE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
FL
(0,1)
RXI
FL
(0,1)
WXI
RXI
WXI
4294 drw 31
VCC
VCC
GND
GND
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration
MARCH2013
24
ORDERING INFORMATION
XXXXX
X
XX
X
X
X
X
Device Type Power Speed Package
Process /
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
10
15
20
Commercial Only
Clock Cycle Time (tCLK)
Com'l & Ind'l
Speed in Nanoseconds
Commercial Only
Low Power
L
72V205
72V215
72V225
72V235
72V245
256 x 18 ⎯ 3.3V SyncFIFO
512 x 18 ⎯ 3.3V SyncFIFO
1,024 x 18 ⎯ 3.3V SyncFIFO
2,048 x 18 ⎯ 3.3V SyncFIFO
4,096 x 18 ⎯ 3.3V SyncFIFO
4294 drw 32
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
05/02/2001
01/11/2002
02/01/2002
02/22/2006
10/22/2008
03/21/2013
pgs. 4, 5 and 25.
pg. 4.
pg. 4.
pgs. 1 and 25.
pg. 25.
pg. 2 and 25.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
25
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