72V221L20JGI [IDT]
3.3 VOLT CMOS SyncFIFO;
| 型号： | 72V221L20JGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS SyncFIFO 先进先出芯片 |
| 文件： | 总14页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
4,096 x 9 and 8,192 x 9
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-
bitmemoryarray,respectively.TheseFIFOsareapplicableforawidevariety
ofdatabufferingneedssuchasgraphics,localareanetworksandinterprocessor
communication.
FEATURES:
• 256 x 9-bit organization IDT72V201
• 512 x 9-bit organization IDT72V211
• 1,024 x 9-bit organization IDT72V221
• 2,048 x 9-bit organization IDT72V231
• 4,096 x 9-bit organization IDT72V241
• 8,192 x 9-bit organization IDT72V251
• 10 ns read/write cycle time
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every
rising clock edge when the Write Enable pins are asserted. The output
port is controlled by another clock pin (RCLK) and two Read Enable pins
(REN1, REN2). The Read Clock can be tied to the Write Clock for single
clock operation or the two clocks can run asynchronous of one another
for dual-clock operation. An Output Enable pin (OE) is provided on the
read port for three-state control of the output.
TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).
Twoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF),are
provided for improved system control. The programmable flags default to
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting
the Load pin (LD).
• 5V input tolerant
• Read and Write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full Flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can be set to
any depth
• Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
• Output Enable puts output data bus in high-impedance state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
These FIFOs are fabricated using high-speed submicron CMOS
technology.
DESCRIPTION:
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™
FUNCTIONAL BLOCK DIAGRAM
D0 - D8
WCLK
WEN1
WEN2
LD
INPUT REGISTER
OFFSET REGISTER
EF
FLAG
LOGIC
PAE
PAF
FF
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
READ POINTER
WRITE POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
4092 drw 01
Q0 - Q8
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AUGUST 2013
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4092/6
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
PIN CONFIGURATION
INDEX
INDEX
29 28 27 26 25
32 31 30
4
3
2
32 31 30
1
5
29
28
27
26
25
24
23
22
21
D
1
RS
1
2
3
4
5
6
7
8
D
1
WEN1
24
23
22
21
20
19
18
17
6
D0
WEN1
WCLK
WEN2/LD
D0
WCLK
WEN2/LD
VCC
PAF
PAE
7
PAF
PAE
8
9
GND
REN1
RCLK
REN2
OE
VCC
GND
Q8
10
11
12
13
Q8
REN1
RCLK
REN2
Q7
Q7
Q6
Q6
Q5
Q5
9
10 11 12 13 14 15 16
14 15 16 17 18 19 20
4092 drw02
4092 drw02a
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PINDESCRIPTIONS
Symbol
D0-D8
RS
Name
DataInputs
Reset
I/O
Description
I
I
Datainputsfora9-bitbus.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up.
WCLK
WriteClock
I
I
DataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLKwhentheWriteEnable(s)areasserted.
WEN1
WriteEnable1
If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is
LOW, dataiswrittenintotheFIFOoneveryLOW-to-HIGHtransitionWCLK. IftheFIFOisconfiguredto
have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
willnotbewrittenintotheFIFOiftheFF isLOW.
WEN2/LD
WriteEnable2/
Load
I
The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/LD
isHIGHatReset, thispinoperatesasasecondwriteenable. IfWEN2/LD isLOWatReset, thispinoperates
as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written
into the FIFOif theFF isLOW. IftheFIFOisconfiguredtohaveprogrammableflags, WEN2/LD isheldLOWto
writeorreadtheprogrammableflagoffsets.
Q0-Q8
RCLK
REN1
DataOutputs
ReadClock
O
I
Dataoutputsfora9-bitbus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
will not be read from the FIFO if the EF is LOW.
Read Enable 1
I
REN2
OE
Read Enable 2
OutputEnable
EmptyFlag
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
COMMERCIALANDINDUSTRIAL
Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
TEMPERATURERANGES
I
state.
EF
O
O
O
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is
HIGH, the FIFO is not empty. EF is synchronized to RCLK.
WhenPAE isLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetisEmpty+7. PAE issynchronizedtoRCLK.
WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetisFull-7. PAF issynchronizedtoWCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
isnotfull. FFissynchronizedtoWCLK.
PAE
PAF
FF
Programmable
Almost-EmptyFlag
Programmable
Almost-FullFlag
Full Flag
VCC
Power
One 3.3V volt power supply pin.
One 0 volt ground pin.
GND
Ground
2
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS
Symbol
Rating
TerminalVoltagewith
RespecttoGND
Com'l & Ind'l
Unit
V
(2)
Symbol
Parameter
Min.
Typ. Max. Unit
VTERM
–0.5 to +5
VCC
SupplyVoltage
3.0
3.3
3.6
V
Commercial/Industrial
SupplyVoltage
InputHighVoltage
Commercial/Industrial
InputLowVoltage
Commercial/Industrial
TSTG
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
GND
VIH
0
2.0
0
—
0
5.5
V
V
IOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL
TA
TA
-0.5
0
—
—
—
0.8
70
85
V
OperatingTemperature
Commercial
°C
°C
2. VCC terminal only.
OperatingTemperature
Industrial
-40
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V201
IDT72V211
IDT72V221
IDT72V231
IDT72V241
IDT72V251
Commercial and Industrial(1)
tCLK = 10, 15, 20 ns
Typ.
Symbol
Parameter
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Min.
–1
Max.
1
Unit
μA
μA
V
(2)
ILI
—
—
—
—
—
—
(3)
ILO
–10
2.4
—
10
—
0.4
20
5
VOH
VOL
ICC1
ICC2
Output Logic “1” Voltage, IOH = –2mA
Output Logic “0” Voltage, IOL = 8mA
Active Power Supply Current
StandbyCurrent
V
(4,5,6)
(4,7)
—
mA
mA
—
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
InputCapacitance
VIN = 0V
10
pF
(1,2)
COUT
OutputCapacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected (OE ≥ VIH).
2. Characterized values, not currently tested.
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3 ±0.3V, TA = 0°C to + 70°C;Industrial: VCC = 3.3 ±0.3V, TA = -40°C to + 85°C)
Commercial
Com'l & Ind'l(2)
Commercial
IDT72V201L10
IDT72V211L10
IDT72V221L10
IDT72V231L10
IDT72V241L10
IDT72V251L10
IDT72V201L15
IDT72V211L15
IDT72V221L15
IDT72V231L15
IDT72V241L15
IDT72V251L15
IDT72V201L20
IDT72V211L20
IDT72V221L20
IDT72V231L20
IDT72V241L20
IDT72V251L20
Symbol
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
—
100
—
66.7
—
50
MHz
tA
DataAccessTime
2
10
4.5
4.5
3
6.5
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6.5
6.5
6.5
6.5
—
2
15
6
10
—
—
—
—
—
—
—
—
—
—
15
—
8
2
20
8
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock High Time
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tRS
EnableSetupTime
4
5
EnableHoldTime
ResetPulseWidth(1)
0.5
10
8
1
1
15
10
10
—
0
20
12
12
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
OutputEnabletoOutputinLow-Z(3)
OutputEnabletoOutputValid
OutputEnabletoOutputinHigh-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
WriteClocktoAlmost-FullFlag
Read Clock to Almost-Empty Flag
8
—
0
3
3
3
tOHZ
tWFF
tREF
tAF
3
3
8
3
—
—
—
—
5
—
—
—
—
6
10
10
10
10
—
—
—
—
—
8
tAE
tSKEW1
Skew time between Read Clock & Write
Clock for Empty Flag &Full Flag
tSKEW2
Skew time between Read Clock & Write
Clock for Almost-Empty Flag &
Almost-FullFlag
14
—
18
—
20
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range is available by special order for speed grades faster than 15ns.
3. Values guaranteed by design, not currently tested.
3.3V
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
330Ω
D.U.T.
ACTESTCONDITIONS
30pF*
510Ω
In Pulse Levels
GND to 3.0V
3ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
4092 drw03
1.5V
or equivalent circuit
SeeFigure1
Figure 1. Output Load
*Includes jig and scope capacitances.
4
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
OUTPUTENABLE(OE)
SIGNALDESCRIPTIONS
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister. WhenOutputEnable(OE)isdisabled
(HIGH), theQoutputdatabusisinahigh-impedancestate.
INPUTS:
DATA IN (D0 - D8)
Datainputsfor9-bitwidedata.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmableflagsortohavetwowriteenables,whichallowsdepthexpansion.
If Write Enable 2/Load (WEN2/LD) is set high at Reset (RS = LOW), this pin
operatesasasecondWriteEnablepin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition
ofeveryWriteClock(WCLK). DataisstoredintheRAMarraysequentiallyand
independently of any on-going read operation.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.
During reset, both internal read and write pointers are set to the first location.
Aresetisrequiredafterpower-upbeforeawriteoperationcantakeplace. The
Full Flag (FF) and Programmable Almost-Full Flag (PAF) will be reset to HIGH
aftertRSF. TheEmptyFlag(EF)andProgrammableAlmost-EmptyFlag(PAE)
will be reset to LOW after tRSF. During reset, the output register is initialized to
all zeros and the offset registers are initialized to their default values.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable2/Load(WEN2/LD)isLOW,theinputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
WRITE CLOCK (WCLK)
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
TheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable
2/Load(WEN2/LD)issetLOWatReset(RS =LOW). TheIDT72V201/72V211/
72V221/72V231/72V241/72V251 devices contain four 8-bit offset registers
whichcanbeloadedwithdataontheinputs,orreadontheoutputs. SeeFigure
3fordetailsofthesizeoftheregistersandthedefaultvalues.
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH
transitionoftheWriteClock(WCLK). TheFullFlag(FF)andProgrammable
Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH
transitionoftheWriteClock(WCLK).
The Write and Read clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
IftheFIFOisconfiguredforprogrammableflags,WriteEnable1(WEN1)
istheonlyenablecontrolpin. Inthisconfiguration,whenWriteEnable1(WEN1)
islow,datacanbeloadedintotheinputregisterandRAMarrayontheLOW-
to-HIGHtransitionofeveryWriteClock(WCLK). DataisstoredintheRAMarray
sequentially and independently of any on-going read operation.
Inthisconfiguration,whenWriteEnable1(WEN1)isHIGH,theinputregister
holdsthepreviousdataandnonewdataisallowedtobeloadedintotheregister.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion,therearetwoenablecontrolpins. SeeWriteEnable2paragraph
belowforoperationinthisconfiguration.
If theFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable
1(WEN1)andWriteEnable2/Load(WEN2/LD)aresetlow,dataontheinputs
DiswrittenintotheEmpty(LeastSignificantBit)OffsetregisteronthefirstLOW-
to-HIGHtransitionoftheWriteClock(WCLK). DataiswrittenintotheEmpty(Most
SignificantBit)OffsetregisteronthesecondLOW-to-HIGHtransitionoftheWrite
Clock(WCLK), intotheFull(LeastSignificantBit)Offsetregisteronthethird
transition, andintotheFull(MostSignificantBit)Offsetregisteronthefourth
transition. Thefifth transitionofthe WriteClock(WCLK)againwritestotheEmpty
(LeastSignificantBit)Offsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime. One
ortwooffsetregisterscanbewrittenandthenbybringingtheWriteEnable2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. WhentheWriteEnable2/Load(WEN2/LD)pinissetLOW,andWrite
Enable1(WEN1)isLOW,thenextoffsetregisterinsequenceiswritten.
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe
WriteEnable2/Load(WEN2/LD)pinissetlowandbothReadEnables(REN1,
REN2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransitionofthe
Read Clock (RCLK).
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock(RCLK).TheEmptyFlag(EF)andProgrammableAlmost-EmptyFlag
(PAE)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionoftheRead
Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.
LD
WEN1
WCLK
Selection
Empty Offset (LSB)
The Write and Read clocks can be asynchronous or coincident.
0
0
Empty Offset (MSB)
READ ENABLES (REN1, REN2)
FullOffset(LSB)
WhenbothReadEnables(REN1, REN2)areLOW, dataisreadfromthe
RAMarraytotheoutputregisterontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK).
WheneitherReadEnable(REN1,REN2)isHIGH,theoutputregisterholds
the previous data and no new data is allowed to be loaded into the register.
WhenallthedatahasbeenreadfromtheFIFO,theEmptyFlag(EF)willgo
LOW,inhibitingfurtherreadoperations.Onceavalidwriteoperationhasbeen
accomplished,theEmptyFlag(EF)willgoHIGHaftertREFandavalidreadcan
begin. TheReadEnables(REN1,REN2)areignoredwhentheFIFOisempty.
Full Offset (MSB)
NoOperation
0
1
1
0
1
WriteIntoFIFO
NoOperation
1
NOTES:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
5
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
IDT72V221 - 1,024 x 9-BIT
0
Empty Offset (LSB) Reg.
IDT72V201 - 256 x 9-BIT
IDT72V211 - 512 x 9-BIT
8
8
8
8
7
7
8
8
8
8
7
0
0
0
0
8
8
8
8
0
0
0
0
7
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
Default Value 007H
0
1
(MSB)
1
(MSB)
0
00
0
Full Offset (LSB) Reg.
7
7
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Default Value 007H
0
1
1
(MSB)
(MSB)
0
00
IDT72V231 - 2,049 x 9-BIT
IDT72V241 - 4,096 x 9-BIT
IDT72V251 - 8,192 x 9-BIT
0
8
8
8
8
7
0
0
0
0
8
8
8
8
0
0
0
0
8
8
8
8
7
7
7
7
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
0
2
3
4
(MSB)
(MSB)
00000
(MSB)
0000
000
7
0
Full Offset (LSB)
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Default Value 007H
0
2
3
4
(MSB)
(MSB)
(MSB)
0000
00000
000
4092 drw 05
Figure 3. Offset Register Location and Default Values
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
6
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
IDT72V221, (2,048-m) writes for the IDT72V231, (4,096-m) writes for the
IDT72V241and(8,192-m)writesfortheIDT72V251. Theoffset“m”isdefined
intheFullOffsetregisters.
Ifthereisnofulloffsetspecified,theProgrammableAlmost-Fullflag(PAF)
will go LOW at Full-7 words.
OUTPUTS:
FULL FLAG (FF)
TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
willgoLOWafter256writesfortheIDT72V201,512writesfortheIDT72V211,
1,024writesfortheIDT72V221,2,048writesfortheIDT72V231,4,096writes
for the IDT72V241 and 8,192 writes for the IDT72V251.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transitionoftheWriteClock(WCLK).
TheProgrammableAlmost-Fullflag(PAF)issynchronizedwithrespectto
theLOW-to-HIGHtransitionoftheWriteClock(WCLK).
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheread
pointeris"n+1"locationslessthanthewritepointer. Theoffset"n"isdefined
in the Empty Offset registers. If no reads are performed after Reset the
Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the
IDT72V201/72V211/72V221/72V231/72V241/72V251.
Ifthereisnoemptyoffsetspecified,theProgrammableAlmost-Emptyflag
(PAE)willgoLOWatEmpty+7words.
EMPTY FLAG (EF)
TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when
thereadpointerisequaltothewritepointer, indicatingthedeviceisempty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transitionoftheReadClock(RCLK).
TheProgrammableAlmost-Emptyflag(PAE)issynchronizedwithrespect
totheLOW-to-HIGHtransitionoftheReadClock(RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reachesthealmost-fullcondition.IfnoreadsareperformedafterReset(RS),
theProgrammableAlmost-Fullflag(PAF)willgoLOWafter (256-m)writesfor
the IDT72V201, (512-m) writes for the IDT72V211, (1,024-m) writes for the
DATA OUTPUTS (Q0 - Q8)
Dataoutputsfora9-bitwidedata.
TABLE 1 — STATUS FLAGS
NUMBER OF WORDS IN FIFO
IDT72V201
IDT72V211
IDT72V221
FF
PAF
PAE
EF
0
1 to n(1)
0
1 to n(1)
0
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
1 to n(1)
(n+1)to(256-(m+1))
(256-m)(2)to255
256
(n+1)to(512-(m+1))
(512-m)(2)to511
512
(n+1)to(1,024-(m+1))
(1,024-m)(2)to1,023
1,024
H
H
H
L
NUMBER OF WORDS IN FIFO
IDT72V231
IDT72V241
IDT72V251
FF
PAF
PAE
EF
0
0
0
H
H
L
L
1 to n(1)
1 to n(1)
1 to n(1)
H
H
H
H
L
H
H
(n+1)to(2,048-(m+1))
(n+1)to(4,096-(m+1))
(n+1)to(8,192-(m+1))
H
(2,048-m)(2)to2,047
(4,096-m)(2) to4,095
4,096
(8,192-m)(2) to8,191
8,192
H
L
L
L
H
H
H
H
2,048
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
7
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tRS
RS
tRSS
tRSS
tRSS
tRSR
tRSR
tRSR
REN1,
REN2
WEN1
WEN2/LD(1)
EF, PAE
t
RSF
t
RSF
FF, PAF
t
RSF
OE = 1(2)
Q0 - Q8
4092 drw06
OE = 0
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable
flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and high-impedance if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
tCLK
tCLKH
tCLKL
WCLK
tDH
tDS
D0 - D8
DATA IN VALID
tENH
tENS
NO OPERATION
NO OPERATION
WEN1
t
ENH
tENS
WEN2/
(If Applicable)
COMMERCIALANDINDUSTRIAL
t
WFF
tWFF
TEMPERATURERANGES
FF
(1)
SKEW1
t
RCLK
REN1,
REN2
4092 drw07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
REN1,
REN2
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 - Q8
tOLZ
tOHZ
tOE
OE
(1)
tSKEW1
WCLK
WEN1
4092 drw08
WEN2
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
WCLK
tDS
D1
D0 (First Valid Write)
D2
D3
D0 - D8
tENS
tENS
WEN1
WEN2
(If Applicable)
(1)
tFRL
tSKEW1
RCLK
tREF
EF
tENS
REN1,
REN2
tA
tA
D0
D1
Q0 - Q8
tOLZ
tOE
OE
NOTE:
4092 drw09
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
NO WRITE
NO WRITE
NO WRITE
WCLK
tSKEW1
tSKEW1
tDS
D0 - D8
t
WFF
t
WFF
t
WFF
FF
(1)
ENS
t
tENH
tENS
WEN1
(1)
ENS
tENS
tENH
t
WEN2
(If Applicable)
RCLK
tENH
tENH
tENS
tENS
REN1,
REN2
tA
LOW
OE
tA
Q0
- Q8
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
4092 drw10
NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLK
tDS
tDS
DATA WRITE 1
tENH
DATA WRITE 2
tENH
D0 - D8
tENS
tENS
tENS
WEN1
tENS
tENH
tENH
WEN2
(If Applicable)
(1)
tFRL
(1)
tFFL
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EF
REN1,
REN2
OE
LOW
tA
DATA READ
DATA IN OUTPUT REGISTER
Q0 - Q8
4092 drw11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
10
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tCLKH
tCLKL
(4)
WCLK
tENS
tENH
WEN1
tENS
tENH
WEN2
(If Applicable)
t
PAF
Full - (m + 1) words in FIFO(1)
Full - m words in FIFO (2)
PAF
(3)
t
PAF
tSKEW2
RCLK
tENS
tENH
REN1,
REN2
4092 drw12
NOTES:
1. m = PAF offset.
2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m
words for IDT72V251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
tCLKH
tCLKL
WCLK
t
ENH
ENH
t
ENS
ENS
WEN1
t
t
WEN2
(If Applicable)
n + 1 words in FIFO
n words in FIFO(1)
PAE
(2)
tSKEW2
t
PAE
t
PAE
(3)
RCLK
tENH
tENS
REN1,
REN2
4092 drw13
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and
the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
11
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN1
tDS
tDH
D0 - D7
4092 drw14
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
Figure 12. Write Offset Registers Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tENS
REN1,
REN2
tA
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
DATA IN OUTPUT REGISTER
Q0 - Q7
(LSB)
FULL OFFSET
(MSB)
4092 drw15
Figure 13. Read Offset Registers Timing
12
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
theReadEnable2(REN2)controlinputcanbegrounded(seeFigure14). In
thisconfiguration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatReset
so that the pin operates as a control to load and read the programmable flag
offsets.
OPERATINGCONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be
usedwhentheapplicationrequirementsarefor256/512/1,024/2,048/4,096/
8,192wordsorless. WhentheseFIFOsareinaSingleDeviceConfiguration,
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
IDT
72V201
72V211
72V221
72V231
72V241
72V251
WRITE ENABLE 1 (WEN1)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (D - D
0
8)
DATA OUT (Q
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)
0 - Q8)
FULL FLAG (FF)
PROGRAMMABLE ALMOST-FULL (PAF)
4092 drw16
READ ENABLE 2 (REN2)
Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
1,024/2,048/4,096/8,192words. Theexistenceoftwoenablepinsontheread
andwriteportallowdepthexpansion. TheWriteEnable2/Loadpinisusedas
a second write enable in a depth expansion configuration thus the program-
mableflagsaresettothedefaultvalues. Depthexpansionispossiblebyusing
oneenableinputforsystemcontrolwhiletheotherenableinputiscontrolledby
expansionlogictodirecttheflowofdata. Atypicalapplicationwouldhavethe
expansionlogicalternatedataaccessfromonedevicetothenextinasequential
manner. TheseFIFOsoperateintheDepthExpansionconfigurationwhenthe
followingconditionsaremet:
Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput
controlssignalsofmultipledevices. Acompositeflagshouldbecreatedforeach
oftheend-pointstatusflags(EFandFF). Thepartialstatusflags(AEandAF)
canbedetectedfromanyonedevice. Figure15demonstratesa18-bitword
widthbyusingtwoIDT72V201/72V211/72V221/72V231/72V241/72V251s.
Any word width can be attained by adding additional IDT72V201/72V211/
72V221/72V231/72V241/72V251s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
configuration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatResetso
thatthepinoperatesasacontroltoloadandreadtheprogrammableflagoffsets.
1. The WEN2/ LD pin is held HIGH during Reset so that this pin
operatesasecondWriteEnable.
2. Externallogicisusedtocontroltheflowofdata.
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN-
CHRONOUSFIFOsUSINGTHERINGCOUNTERAPPROACH"fordetails
ofthisconfiguration.
DEPTHEXPANSION
The IDT72V201/72V211/72V221/72V231/72V241/72V251 can be
adaptedtoapplicationswhentherequirementsareforgreaterthan256/512/
RESET (RS)
RESET (RS)
DATA IN (D)
18
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE1 (REN1)
WRITE ENABLE1 (WEN1)
OUTPUT ENABLE (OE)
IDT
IDT
WRITE ENABLE2/LOAD (WEN2/LD)
72V201
72V211
72V221
72V231
72V241
72V251
72V201
72V211
72V221
72V231
72V241
72V251
PROGRAMMABLE (PAE)
FULL FLAG (FF) #1
FULL FLAG (FF) #2
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
9
PROGRAMMABLE (PAF)
9
DATA OUT (Q)
18
READ ENABLE 2 (REN2)
READ ENABLE 2 (REN2)
4092 drw17
Figure 15. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
13
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
X
Device Type Power Speed Package
Process/
Temperature
Range
BLANK
8
Tube or Tray
Tape and Reel
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
J
PF
Plastic Leaded Chip Carrier (PLCC, J32-1)
Plastic Thin Quad Flatpack (TQFP, PR32-1)
10
15
20
Commerical Only
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commerical & Industrial
Commerical Only
Low Power
L
72V201
72V211
72V221
72V231
72V241
72V251
256 x 9 ⎯ 3.3V SyncFIFO™
512 x 9 ⎯ 3.3V SyncFIFO™
1,024 x 9 ⎯ 3.3V SyncFIFO™
2,048 x 9 ⎯ 3.3V SyncFIFO™
4,096 x 9 ⎯ 3.3V SyncFIFO™
8,192 x 9 ⎯ 3.3V SyncFIFO™
4092 drw 18
NOTES:
1. Industrial temperature range product for the 15ns is available as a standard device. All other speed grades are available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
01/11/2002
02/01/2002
02/08/2006
10/22/2008
08/08/2013
pg. 3.
pg. 3.
pgs. 1 and 14.
pg. 14.
pgs. 1, 13 and 14.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
14
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