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72V3624L10PF [IDT]

TQFP-128, Tray;
72V3624L10PF
型号： 72V3624L10PF
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
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TQFP-128, Tray
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3.3 VOLT CMOS SyncBiFIFOTM  
WITH BUS-MATCHING  
256 x 36 x 2  
IDT72V3624  
IDT72V3644  
1,024 x 36 x 2  
(byte)  
FEATURES:  
• Memory storage capacity:  
• Big- or Little-Endian format for word and byte bus sizes  
• Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
IDT72V3624–256 x 36 x 2  
IDT72V3644–1,024 x 36 x 2  
• Mailbox bypass registers for each FIFO  
• Clock frequencies up to 100 MHz (6.5ns access time)  
• Two independent clocked FIFOs buffering data in opposite  
directions  
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB  
flags functions) or First Word Fall Through Timing (using ORA,  
ORB, IRA, and IRB flag functions)  
• Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
• Serial or parallel programming of partial flags  
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
• Free-running CLKA and CLKB may be asynchronous or coinci-  
dent (simultaneous reading and writing of data on a single clock  
edge is permitted)  
• Auto power down minimizes power dissipation  
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
• Pin and functionally compatible version of the 5V operating  
IDT723624/723644  
• Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
RAM ARRAY  
256 x 36  
1,024 x 36  
36  
36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS  
1
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO1  
FIFO2  
SPM  
FS0/SD  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS1/SEN  
A
0-A35  
B0-B35  
10  
EFA/ORA  
Status Flag  
Logic  
FFB/IR  
B
AFB  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS  
2
RAM ARRAY  
256 x 36  
36  
36  
1,024 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
SIZE  
MBF2  
4664 drw01  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc.NSynGcBEiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
MARCH 2015  
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4664/6  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
SRAM FIFOs on board each chip buffer data in opposite directions. FIFO  
data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with  
a choice of Big- or Little-Endian configurations.  
These devices are a synchronous (clocked) FIFO, meaning each port  
employsasynchronousinterface.Alldatatransfersthroughaportaregated  
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor  
each port are independent of one another and can be asynchronous or  
DESCRIPTION:  
The IDT72V3624/72V3644 are pin and functionally compatible  
versions of the IDT723624/723644, designed to run off a 3.3V supply for  
exceptionally low-power consumption. These devices are monolithic,  
high-speed, low-power, CMOS bidirectional synchronous (clocked) FIFO  
memory which supports clock frequencies up to 100 MHz and has read  
access times as fast as 6.5ns. Two independent 256/1,024 x 36 dual-port  
PIN CONFIGURATION  
INDEX  
W/RA  
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
CLKB  
PRS2  
1
2
3
4
5
6
7
8
ENA  
CLKA  
GND  
A35  
A34  
A33  
A32  
Vcc  
A31  
A30  
GND  
A29  
A28  
A27  
A26  
A25  
A24  
A23  
Vcc  
B35  
B34  
B33  
B32  
GND  
GND  
B31  
B30  
B29  
B28  
B27  
B26  
Vcc  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
B25  
B24  
BM  
GND  
B23  
B22  
B21  
B20  
B19  
B18  
GND  
B17  
B16  
SIZE  
Vcc  
B15  
B14  
B13  
B12  
GND  
B11  
B10  
BE/FWFT  
GND  
A22  
Vcc  
A21  
A20  
A19  
A18  
GND  
A17  
A16  
A15  
A14  
A13  
Vcc  
A12  
GND  
A11  
A10  
4664 drw02  
TQFP (PK128, order code: PF)  
TOP VIEW  
2
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
coincident. The enables for each port are arranged to provide a simple IRB). The EF and FF functions are selected in the IDT Standard mode.  
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- EF indicates whether or not the FIFO memory is empty. FF shows  
nouscontrol.  
whether the memory is full or not. The IR and OR functions are selected  
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox in the First Word Fall Through mode. IR indicates whether or not the FIFO  
registers.Themailboxregisters’widthmatchestheselectedPortBbuswidth. has available memory locations. OR shows whether the FIFO has data  
Each Mailbox register has a flag (MBF1 and MBF2)tosignalwhennewmail available for reading or not. It marks the presence of valid data on the  
hasbeenstored.  
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial  
outputs.  
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and  
Reset.MasterResetinitializesthereadandwritepointerstothefirstlocationof aprogrammableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen  
thememoryarray,configurestheFIFOforBig-orLittle-Endianbytearrange- aselectednumberofwordsremainintheFIFOmemory.AFAandAFBindicate  
mentandselectsserialflagprogramming,parallelflagprogramming,oroneof when the FIFO contains more than a selected number of words.  
threepossibledefaultflagoffsetsettings,8,16or64.TherearetwoMasterReset  
pins, MRS1 and MRS2.  
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport  
clockthatwritesdataintoitsarray.EFA/ORA,EFB/ORB,AEAandAEBaretwo-  
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe stagesynchronizedtotheportclockthatreadsdatafromitsarray.Program-  
memory.UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., mableoffsetsforAEA,AEB,AFAandAFBareloaded inparallelusingPortA  
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset orinserialviatheSDinput.TheSerialProgrammingModepin(SPM)makes  
is useful since it permits flushing of the FIFO memory without changing any thisselection.Threedefaultoffsetsettingsarealsoprovided.TheAEAandAEB  
configurationsettings.EachFIFOhasitsown,independentPartialResetpin, thresholdcanbesetat8,16or64locationsfromtheemptyboundaryandthe  
PRS1 and PRS2.  
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.  
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.  
AFAandAFBthresholdcanbesetat8,16or64locationsfromthefullboundary.  
read operation is required to access that word (along with all other words If, at any time, the FIFO is not actively performing a function, the chip will  
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong- automatically power down. During the power down state, supply current  
word (36-bit wide) written to an empty FIFO appears automatically on the consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol  
outputs,noreadoperationisrequired(Nevertheless,accessingsubsequent inputs)willimmediatelytakethedeviceoutofthepowerdownstate.  
wordsdoesnecessitateaformalreadrequest).ThestateoftheBE/FWFTpin  
duringFIFOoperationdeterminesthemodeinuse.  
The IDT72V3624/72V3644 are characterized for operation from 0°C  
to 70°C. Industrial temperature range (-40°C to +85°C) is available. They  
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and are fabricated using high speed, submicron CMOS technology.  
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/  
3
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
PINDESCRIPTIONS  
Symbol  
Name  
I/O  
Description  
A0-A35  
Port A Data  
I/O 36-bit bidirectional data port for side A.  
AEA  
Port A Almost-  
Empty Flag  
O
O
O
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in  
FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.  
AEB  
AFA  
AFB  
Port B Almost-  
Empty Flag  
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in  
FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.  
Port A Almost-  
Full Flag  
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations  
in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.  
Port B Almost-  
Full Flag  
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations  
in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.  
B0-B35  
Port A Data  
I/O 36-bit bidirectional data port for side B.  
BE/FWFT  
Big-Endian/  
First Word  
Fall Through  
Select  
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In  
this case, depending on the bus size, the most significant byte or word on Port A is read from Port B  
first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little-Endian  
operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B  
data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode  
A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the  
timing mode has been selected, the level on FWFT must be static throughout device operation.  
BM  
Bus-Match  
Select  
(Port B)  
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE.  
A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian  
arrangement for Port B. The level of BM must be static throughout device operation.  
CLKA  
CLKB  
Port A Clock  
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous  
or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH  
transition of CLKA.  
Port B Clock  
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous  
or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition  
of CLKB.  
CSA  
Port A Chip  
Select  
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35  
outputs are in the high-impedance state when CSA is HIGH.  
CSB  
Port B Chip  
Select  
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The  
B0-B35 outputs are in the high-impedance state when CSB is HIGH.  
EFA/ORA  
Port A Empty/  
Output Ready  
Flag  
O
This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether  
or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the  
presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized to the LOW-  
to-HIGH transition of CLKA.  
EFB/ORB  
Port B Empty/  
Output Ready  
Flag  
O
This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether  
or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the  
presence of valid data on the B0-B35 outputs, available for reading. EFB/ORB is synchronized to the LOW-  
to-HIGH transition of CLKB.  
ENA  
Port A Enable  
Port B Enable  
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.  
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.  
ENB  
FFA/IRA  
Port A Full/  
Input Ready  
Flag  
O
This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates  
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates  
whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the  
LOW-to-HIGH transition of CLKA.  
FFB/IRB  
Port B Full/  
Input Ready  
Flag  
O
This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates  
whether or not the FIFO2 memory is full.In the FWFT mode, the IRB function is selected. IRB indicates  
whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the  
LOW-to-HIGH transition of CLKB.  
4
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
PINDESCRIPTIONS(CONTINUED)  
Symbol  
Name  
I/O  
Description  
FS1/SEN Flag Offset Select 1/  
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master  
Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three  
offset register programming methods are available: automatically load one of three preset values (8, 16,  
or 64), parallel load from Port A, and serial load.  
Serial Enable,  
FS0/SD Flag Offset Select 0/  
Serial Data  
I
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable  
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA  
load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program  
the offset registers is 32 for the 72V3624, and 40 for the 72V3644. The first bit write stores the Y-register  
(Y1) MSB and the last bit write stores the X-register (X2) LSB.  
MBA  
MBB  
MBF1  
Port A Mailbox  
Select  
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35  
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level  
selects FIFO2 output register data for output.  
Port B Mailbox  
Select  
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35  
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level  
selects FIFO1 output register data for output.  
Mail1 Register  
Flag  
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to  
the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition  
CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or  
Partial Reset of FIFO1.  
MBF2  
MRS1  
Mail2 Register  
Flag  
O
I
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to  
the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of  
CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or  
Partial Reset of FIFO2.  
FIFO1 Master  
Reset  
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the  
Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method  
(serial or parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures  
Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH  
transitions of CLKB must occur while MRS1 is LOW.  
MRS2  
FIFO2 Master  
Reset  
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the  
Port A output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1,  
selects the programming method (serial or parallel) and one of the programmable flag default offsets for  
FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while  
MRS2 is LOW.  
PRS1  
PRS2  
SIZE  
FIFO1 Partial  
Reset  
I
I
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the  
Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,  
programming method (serial or parallel), and programmable flag settings are all retained.  
FIFO2 Partial  
Reset  
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the  
Port A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,  
programming method (serial or parallel), and programmable flag settings are all retained.  
Bus Size Select  
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is  
HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian  
arrangement for Port B. The level of SIZE must be static throughout device operation.  
SPM  
Serial Programming  
Mode  
I
I
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel  
programming or default offsets (8, 16, or 64).  
W/RA  
W/RB  
Port-A Write/  
Read Select  
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition  
of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.  
Port-B Write/  
Read Select  
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition  
of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.  
5
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR  
TEMPERATURE RANGE (Unless otherwise noted)(1)  
Symbol  
VCC  
VI(2)  
Rating  
Commercial  
–0.5 to +4.6  
–0.5 to VCC+0.5  
–0.5 to VCC+0.5  
±20  
Unit  
V
SupplyVoltageRange  
InputVoltageRange  
OutputVoltageRange  
V
VO(2)  
V
IIK  
Input Clamp Current (VI < 0 or VI > VCC)  
Output Clamp Current (VO = < 0 or VO > VCC)  
Continuous Output Current (VO = 0 to VCC)  
Continuous Current Through VCC or GND  
StorageTemperatureRange  
mA  
mA  
mA  
mA  
°C  
IOK  
±50  
IOUT  
ICC  
±50  
±400  
TSTG  
–65 to 150  
NOTES:  
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these  
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect  
device reliability.  
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.  
RECOMMENDEDOPERATINGCONDITIONS  
Symbol  
VCC(1)  
VIH  
Parameter  
SupplyVoltage  
Min.  
3.0  
2
Typ.  
3.3  
—
Max.  
3.6  
Unit  
V
High-LevelInputVoltage  
Low-LevelInputVoltage  
High-LevelOutputCurrent  
Low-LevelOutputCurrent  
OperatingTemperature  
VCC+0.5  
0.8  
V
VIL  
—
—
—
0
—
V
IOH  
—
–4  
mA  
mA  
°C  
IOL  
—
8
TA  
—
70  
NOTE:  
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70° C; JEDEC JESD8-A compliant.  
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-  
AIR TEMPERATURE RANGE (Unless otherwise noted)  
IDT72V3624  
IDT72V3644  
Commercial  
tCLK = 10(1), 15ns  
Symbol  
VOH  
Parameter  
Test Conditions  
IOH = –4 mA  
Min. Typ.(2) Max.  
Unit  
V
Output Logic "1" Voltage  
VCC = 3.0V,  
VCC = 3.0V,  
VCC = 3.6V,  
VCC = 3.6V,  
VCC = 3.6V,  
VCC = 3.6V,  
VI = 0,  
2.4  
—
—
—
—
—
—
—
—
—
—
—
—
—
4
—
0.5  
±10  
±10  
5
VOL  
Output Logic "0" Voltage  
IOL = 8 mA  
V
ILI  
Input Leakage Current (Any Input)  
Output Leakage Current  
VI = VCC or 0  
VO = VCC or 0  
μA  
μA  
mA  
mA  
pF  
pF  
ILO  
ICC2(3)  
ICC3(3)  
CIN(4)  
COUT(4)  
Standby Current (with CLKA and CLKB running)  
Standby Current (no clocks running)  
Input Capacitance  
VI = VCC - 0.2V or 0  
VI = VCC - 0.2V or 0  
f = 1 MHz  
1
—
Output Capacitance  
VO = 0,  
f = 1 MHZ  
8
—
NOTES:  
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70° C; JEDEC JESD8-A compliant.  
2. All typical values are at VCC = 3.3V, TA = 25°C.  
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).  
4. Characterized values, not currently tested.  
5. Industrial temperature range is available by special order.  
6
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION  
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3624/72V3644 with  
CLKAandCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputswere  
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's  
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.  
CALCULATING POWER DISSIPATION  
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:  
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)  
N
where:  
N
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)  
output capacitance load  
CL  
fo  
switchingfrequencyofanoutput  
200  
175  
150  
fdata = 1/2 fS  
TA = 25οC  
CL = 0 pF  
VCC = 3.6V  
VCC = 3.3V  
125  
100  
VCC = 3.0V  
75  
50  
25  
0
80  
100  
0
10  
20  
30  
40  
50  
60  
70  
90  
4664 drw03  
fS Clock Frequency MHz  
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)  
7
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY  
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE  
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0°Cto +70°C; JEDEC JESD8-A compliant  
IDT72V3624L10(1) IDT72V3624L15  
IDT72V3644L10(1)  
IDT72V3644L15  
Symbol  
Parameter  
Min.  
—
10  
4.5  
4.5  
3
Max.  
100  
—
Min.  
—
15  
6
Max.  
66.7  
—
Unit  
MHz  
ns  
fS  
Clock Frequency, CLKA or CLKB  
tCLK  
Clock Cycle Time, CLKA or CLKB  
tCLKH  
tCLKL  
tDS  
Pulse Duration, CLKA or CLKB HIGH  
—
—
ns  
Pulse Duration, CLKA and CLKB LOW  
Setup Time, A0-A35 before CLKA↑and B0-B35 before CLKB↑  
SetupTimeCSAbeforeCLKA↑;CSBbeforeCLKB↑  
—
6
—
ns  
—
4
—
ns  
tENS1  
tENS2  
4
—
4.5  
4.5  
—
ns  
Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB  
beforeCLKB↑  
3
—
—
ns  
(2)  
tRSTS  
tFSS  
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑or CLKB↑  
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH  
Setup Time, BE/FWFT before MRS1 and MRS2HIGH  
Setup Time, SPM before MRS1 and MRS2 HIGH  
SetupTime,FS0/SDbeforeCLKA↑  
5
7.5  
7.5  
7.5  
3
—
—
—
—
—
—
—
—
—
5
7.5  
7.5  
7.5  
4
—
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tBES  
tSPMS  
tSDS  
tSENS  
tFWS  
tDH  
SetupTime,FS1/SENbeforeCLKA↑  
3
4
SetupTime,BE/FWFTbeforeCLKA↑  
0
0
HoldTime, A0-A35afterCLKA↑andB0-B35afterCLKB↑  
0.5  
0.5  
1
tENH  
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and  
MBBafterCLKB↑  
1
(2)  
tRSTH  
tFSH  
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑  
4
2
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH  
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH  
Hold Time, SPM after MRS1 and MRS2 HIGH  
Hold Time, FS0/SD after CLKA↑  
tBEH  
2
2
tSPMH  
tSDH  
2
2
0.5  
0.5  
2
1
tSENH  
tSPH  
tSKEW1(3)  
HoldTime, FS1/SENHIGHafterCLKA↑  
1
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH  
2
Skew Time between CLKA↑and CLKB↑for EFA/ORA, EFB/ORB, FFA/IRA,  
and FFB/IRB  
5
7.5  
tSKEW2(3,4) Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB  
12  
—
12  
—
ns  
NOTES:  
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70°C; JEDEC JESD8-A compliant.  
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.  
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.  
4. Design simulated, not tested.  
5. Industrial temperature range is available by special order.  
8
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY  
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF  
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0°C to +70°C; JEDEC JESD8-A compliant  
IDT72V3624L10(1)  
IDT72V3644L10(1)  
IDT72V3624L15  
IDT72V3644L15  
Symbol  
tA  
Parameter  
Min.  
Max.  
6.5  
6.5  
6.5  
6.5  
6.5  
6.5  
Min.  
Max.  
Unit  
ns  
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35  
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to FFB/IRB  
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB  
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB  
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB  
2
2
1
1
1
0
2
2
1
1
1
0
10  
8
tWFF  
tREF  
tPAE  
ns  
8
ns  
8
ns  
tPAF  
8
ns  
tPMF  
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑  
to MBF2 LOW or MBF1 HIGH  
8
ns  
tPMR  
tMDV  
tRSF  
Propagation Delay Time, CLKA↑to B0-B35(2) and CLKB↑to A0-A35(3)  
2
2
1
8
2
2
1
10  
10  
15  
ns  
ns  
ns  
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid  
6.5  
10  
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and  
MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2  
HIGH  
tEN  
tDIS  
Enable Time, CSA or W/RA LOW to A0-A35 Active and CSB LOW and W/RB  
2
1
6
6
2
1
10  
8
ns  
ns  
HIGH to B0-B35 Active  
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB  
HIGH or W/RB LOW to B0-B35 at HIGH impedance  
NOTES:  
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70°C; JEDEC JESD8-A compliant.  
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.  
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.  
4. Industrial temperature range is available by special order.  
9
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
writtentoorreadfromPortB.Thisselectiondeterminestheorderbywhichbytes  
(or words) of data are transferred through this port. For the following  
illustrations,assumethatabyte(orword)bussizehasbeenselectedforPort  
B. (Note that when Port B is configured for a long word size, the Big-Endian  
function has no application and the BE input is a “don’t care”1.)  
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2)  
inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata  
ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)  
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant  
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When  
dataismovinginthedirectionfromPortBtoPortA,thebyte(word)writtento  
PortBfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong  
word;thebyte(word)writtentoPortBlastwillbereadfromPortAastheleast  
significant byte (word) of the long word.  
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)  
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata  
ismovinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)  
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant  
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When  
dataismovinginthedirectionfromPortBtoPortA,thebyte(word)writtento  
PortBfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong  
word;thebyte(word)writtentoPortBlastwillbereadfromPortAasthemost  
significantbyte(word)ofthelongword.RefertoFigure2foranillustrationof  
the BE function. See Figure 3 (Master Reset) for the Endian select timing  
diagram.  
SIGNAL DESCRIPTION  
MASTER RESET (MRS1, MRS2)  
Afterpowerup,aMasterReset operationmustbeperformedbyproviding  
aLOWpulsetoMRS1andMRS2simultaneously. Afterwards,eachofthetwo  
FIFO memories of the IDT72V3624/72V3644 undergoes a complete  
resetbytakingitsassociatedMasterReset(MRS1, MRS2)inputLOWforat  
leastfourPortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGH  
transitions. TheMasterResetinputscanswitchasynchronouslytotheclocks.  
A Master Reset initializes the associated write and read pointers to the first  
locationofthememoryandforcestheFull/InputReadyflag(FFA/IRA,FFB/  
IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the  
Almost-Emptyflag(AEA,AEB)LOWandforcestheAlmost-Fullflag(AFA,AFB)  
HIGH. AMasterResetalsoforcestheassociatedMailboxFlag(MBF1,MFB2)  
of the parallelmailboxregister HIGH. After a Master Reset, the FIFO'sFull/  
InputReadyflagissetHIGHaftertwowriteclockcycles. ThentheFIFOisready  
tobewrittento.  
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input  
latches the values of the Big-Endian (BE) input for determining the order by  
which bytes are transferred through Port B. It also latches the values of the  
Flag Select (FS0, FS1) and Serial Programming Mode (SPM) inputs for  
choosingtheAlmost-FullandAlmost-Emptyoffsetprogrammingmethod.  
ALOW-to-HIGHtransitionontheFIFO2MasterReset(MRS2)clearsthe  
Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the  
FIFO2MasterReset(MRS2)togetherwiththeFIFO1MasterReset(MRS1)  
inputlatchesthevalueoftheBig-Endian(BE)inputforPortBandalsolatches  
thevaluesoftheFlagSelect(FS0,FS1)andSerialProgrammingMode(SPM)  
inputs for choosing the Almost-Full and Almost-Empty offset programming  
method. (FordetailsseeTable1,FlagProgramming,andtheProgramming  
theAlmost-EmptyandAlmost-FullFlagssection). TherelevantFIFOMaster  
Reset timing diagram can be found in Figure 3.  
— TIMING MODE SELECTION  
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice  
between two possible timing modes: IDT Standard mode or First Word Fall  
Through(FWFT)mode.OncetheMasterReset(MRS1,MRS2)inputisHIGH,  
aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA  
(forFIFO1)andCLKB(forFIFO2)willselectIDTStandardmode.Thismode  
usestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereare  
any words present in the FIFO memory. It uses the Full Flag function (FFA,  
FFB)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.  
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must  
be requested using a formal read operation.  
OncetheMasterReset(MRS1, MRS2)inputisHIGH, aLOWontheBE/  
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and  
CLKB(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady  
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata  
outputs(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)  
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In  
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata  
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby  
performingaformalreadoperation.  
PARTIAL RESET (PRS1, PRS2)  
EachofthetwoFIFOmemoriesofthesedevicesundergoesalimitedreset  
bytakingitsassociatedPartialReset(PRS1,PRS2)inputLOWforatleastfour  
PortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.  
ThePartialResetinputscanswitchasynchronouslytotheclocks. APartial  
ResetinitializestheinternalreadandwritepointersandforcestheFull/Input  
Readyflag(FFA/IRA, FFB/IRB)LOW, theEmpty/OutputReadyflag(EFA/  
ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the  
Almost-Fullflag(AFA,AFB)HIGH.APartialResetalsoforcestheMailboxFlag  
(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,the  
FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles. Then  
the FIFO is ready to be written to.  
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming  
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial  
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof  
the reset operation. A Partial Reset may be useful in the case where  
reprogrammingaFIFOfollowingaMasterResetwouldbeinconvenient.See  
Figure4forthePartialResettimingdiagram.  
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose  
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation.Refer  
toFigure3(MasterReset)foraFirstWordFallThroughselecttimingdiagram.  
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS  
Four registers in the IDT72V3624/72V3644 are used to hold the offset  
values for the Almost-Empty and Almost-Full flags. The Port B Almost-  
Emptyflag(AEB)OffsetregisterislabeledX1andthePortAAlmost-Emptyflag  
(AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset  
register is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register is  
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)  
— ENDIAN SELECTION  
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction  
isactive,permittingachoiceofBigorLittle-Endianbytearrangementfordata  
NOTE:  
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with  
unused inputs) must not be left open, rather they must be either HIGH or LOW.  
10  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
labeled Y2. The index of each register name corresponds to its FIFO  
number. The offset registers can be loaded with preset values during the  
reset of a FIFO, programmed in parallel using the FIFO’s Port A data  
inputs, or programmed in serial using the Serial Data (SD) input (see  
Table 1).  
— SERIAL LOAD  
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master  
Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the  
LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete,  
the X and Y register values are loaded bit-wise through the FS0/SD input  
on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW.  
There are 32- or 40-bit writes needed to complete the programming for  
the IDT72V3624 or IDT72V3644, respectively. The four registers are  
written in the order Y1, X1, Y2, and finally, X2. The first-bit write stores  
the most significant bit of the Y1 register and the last-bit write stores the  
least significant bit of the X2 register. Each register value can be  
programmed from 1 to 252 (IDT72V3624) or 1 to 1,020 (IDT72V3644).  
When the option to program the offset registers serially is chosen, the  
Port A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits  
are written. FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA  
after the last bit is loaded to allow normal FIFO1 operation. The Port B  
Full/Input Ready (FFB/IRB) flag also remains LOW throughout the serial  
programming process, until all register bits are written. FFB/IRB is set  
HIGH by the LOW-to-HIGH transition of CLKB after the last bit is loaded  
to allow normal FIFO2 operation. See Figure 6 for Serial Programming  
of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT  
Standard and FWFT Modes) timing diagram.  
SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard  
and FWFT modes.  
— PRESET VALUES  
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith  
oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(SPM)  
andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH  
transitionofitsMasterResetinput(MRS1, MRS2). Forexample, toloadthe  
preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when  
FlFO1reset(MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2  
areloadedwithoneofthepresetvaluesinthesamewaywithFIFO2Master  
Reset(MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For  
relevant preset value loading timing diagram, see Figure 3.  
— PARALLEL LOAD FROM PORT A  
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster  
ResetonbothFlFOssimultaneouslywithSPMHIGHandFS0andFS1LOW  
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is  
complete, thefirstfourwritestoFIFO1donotstoredataintheRAMbutload  
theoffsetregistersintheorderY1,X1,Y2,X2.ThePortAdatainputsusedby  
the offset registers are (A7-A0) or (A9-A0) for the IDT72V3624 or  
IDT72V3644, respectively. The highest numbered input is used as the  
most significant bit of the binary number in each case. Valid program-  
ming values for the registers range from 1 to 252 for the IDT72V3624;  
and 1 to 1,020 for the IDT72V3644. After all the offset registers are  
programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is  
set HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for  
a timing diagram illustration of parallel programming of the flag offset  
values.  
FIFO WRITE/READ OPERATION  
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect  
(CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-  
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are  
active outputs when both CSA and W/RA are LOW.  
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH  
transitionofCLKAwhenCSAisLOW,W/RAisHIGH,ENAisHIGH,MBAis  
LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs  
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA  
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand  
writes on Port A are independent of any concurrent Port B operation.  
TABLE 1 — FLAG PROGRAMMING  
SPM  
H
FS1/SEN FS0/SD  
MRS1  
MRS2  
X1 AND Y1 REGlSTERS(1)  
X2 AND Y2 REGlSTERS(2)  
H
H
H
H
L
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
↑
X
↑
X
↑
↑
↑
↑
↑
↑
64  
X
H
64  
64  
H
16  
X
H
L
16  
16  
H
H
H
L
8
X
H
L
8
Parallel programming via Port A  
Serial programming via SD  
Reserved  
8
Parallel programming via Port A  
Serial programming via SD  
Reserved  
H
L
L
H
H
L
L
L
H
H
L
L
Reserved  
Reserved  
L
L
Reserved  
Reserved  
NOTES:  
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.  
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.  
11  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
are not related to high-impedance control of the data outputs. If a port  
enable is LOW during a clock cycle, the port’s Chip Select and Write/  
Read select may change states during the setup and hold time window  
of the cycle.  
When operating the FIFO in FWFT mode and the Output Ready flag  
is LOW, the next word written is automatically sent to the FIFO’s output  
register by the LOW-to-HIGH transition of the port clock that sets the  
Output Ready flag HIGH. When the Output Ready flag is HIGH, subse-  
quent data is clocked to the output registers only when a read is selected  
using the port’s Chip Select, Write/Read select, Enable, and Mailbox  
select.  
The Port B control signals are identical to those of Port A with the  
exception that the Port B Write/Read select (W/RB) is the inverse of the  
Port A Write/Read select (W/RA). The state of the Port B data (B0-B35)  
lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read  
select (W/RB). The B0-B35 lines are in the high-impedance state when  
either CSB is HIGH or W/RB is LOW. The B0-B35 lines are active outputs  
when CSB is LOW and W/RB is HIGH.  
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH  
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is  
LOW,andFFB/IRBisHIGH.DataisreadfromFIFO1totheB0-B35outputs  
byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB  
isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand  
writes on Port B are independent of any concurrent Port A operation.  
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects  
andWrite/Readselectsareonlyforenablingwriteandreadoperationsand  
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause  
theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe  
ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.  
TABLE 2 — PORT A ENABLE FUNCTION TABLE  
CSA  
W/RA  
ENA  
MBA  
CLKA  
Data A (A0-A35) I/O  
Port Function  
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
↑
X
↑
X
↑
High-Impedance  
Input  
None  
None  
H
H
L
Input  
FIFO1 write  
Mail1 write  
H
L
Input  
Output  
Output  
Output  
Output  
None  
L
H
L
L
FIFO2read  
None  
L
H
H
L
H
Mail2 read (set MBF2 HIGH)  
TABLE 3 — PORT B ENABLE FUNCTION TABLE  
CSB  
W/RB  
ENB  
MBB  
CLKB  
Data B (B0-B35) I/O  
Port Function  
H
L
L
L
L
L
L
L
X
L
X
L
X
X
L
X
X
↑
↑
X
↑
X
↑
High-Impedance  
Input  
None  
None  
L
H
H
L
Input  
FIFO2 write  
Mail2 write  
L
H
L
Input  
H
H
H
H
Output  
Output  
Output  
Output  
None  
H
L
L
FIFO1read  
None  
H
H
H
Mail1 read (set MBF1 HIGH)  
Instead, data residing in the FIFO's memory array is clocked to the SYNCHRONIZED FIFO FLAGS  
output register only when a read is selected using the port’s Chip Select,  
Each FIFO is synchronized to its port clock through at least two flip-  
Write/Read select, Enable, and Mailbox select. Write and read timing flop stages. This is done to improve flag-signal reliability by reducing the  
diagrams for Port A can be found in Figure 7 and 14. Relevant Port B probability of metastable events when CLKA and CLKB operate asyn-  
write and read cycle timing diagrams together with Bus-Matching and chronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are  
Endian select operations can be found in Figures 8 through 13.  
synchronized to CLKA. EFB/ORB, AEB, FFB/IRB, and AFB are synchro-  
12  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)  
Synchronized  
to CLKB  
Synchronized  
to CLKA  
Number of Words in FIFO Memory(1,2)  
(3)  
(3)  
IDT72V3624  
IDT72V3644  
EFB/ORB  
AEB  
AFA  
FFA/IRA  
0
1 to X1  
0
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
1 to X1  
(X1+1)to[256-(Y1+1)]  
(256-Y1) to 255  
256  
(X1+1)to[1,024-(Y1+1)]  
(1,024-Y1) to 1,023  
1,024  
H
H
H
L
NOTES:  
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.  
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read  
operation necessary), it is not included in the FIFO memory count.  
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.  
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.  
TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)  
Synchronized  
to CLKA  
Synchronized  
to CLKB  
Number of Words in FIFO Memory(1,2)  
(3)  
(3)  
IDT72V3624  
IDT72V3644  
EFA/ORA  
AEA  
AFB  
H
FFB/IRB  
0
1 to X2  
0
L
H
H
H
H
L
L
H
H
H
H
L
1 to X2  
H
(X2+1)to[256-(Y2+1)]  
(256-Y2) to 255  
256  
(X2+1)to[1,024-(Y2+1)]  
(1,024-Y2) to 1,023  
1,024  
H
H
H
H
L
L
NOTES:  
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.  
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read  
operation necessary), it is not included in the FIFO memory count.  
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.  
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.  
nized to CLKB. Tables 4 and 5 show the relationship of each port flag to  
FIFO1 and FIFO2.  
In FWFT mode, from the time a word is written to a FIFO, it can be  
shifted to the FIFO output register in a minimum of three cycles of the  
Output Ready flag synchronizing clock. Therefore, an Output Ready  
flag is LOW if a word in memory is the next data to be sent to the FlFO  
output register and three cycles of the port Clock that reads data from  
the FIFO have not elapsed since the time the word was written. The  
Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH  
transition of the synchronizing clock occurs, simultaneously forcing the  
Output Ready flag HIGH and shifting the word to the FIFO output register.  
In IDT Standard mode, from the time a word is written to a FIFO, the  
Empty Flag will indicate the presence of data available for reading in a  
minimum of two cycles of the Empty Flag synchronizing clock. There-  
fore, an Empty Flag is LOW if a word in memory is the next data to be  
sent to the FlFO output register and two cycles of the port Clock that  
reads data from the FIFO have not elapsed since the time the word was  
written. The Empty Flag of the FIFO remains LOW until the second  
LOW-to-HIGH transition of the synchronizing clock occurs, forcing the  
Empty Flag HIGH; only then can data be read.  
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)  
These are dual purpose flags. In the FWFT mode, the Output Ready  
(ORA, ORB) function is selected. When the Output-Ready flag is HIGH,  
new data is present in the FIFO output register. When the Output Ready  
flag is LOW, the previous data word is present in the FIFO output register  
and attempted FIFO reads are ignored.  
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is  
selected. When the Empty Flag is HIGH, data is available in the FIFO’s  
RAM memory for reading to the output register. When the Empty Flag is  
LOW, the previous data word is present in the FIFO output register and  
attempted FIFO reads are ignored.  
The Empty/Output Ready flag of a FIFO is synchronized to the port  
clock that reads data from its array. For both the FWFT and IDT Standard  
modes, the FIFO read pointer is incremented each time a new word is  
clocked to its output register. The state machine that controls an Output  
Ready flag monitors a write pointer and read pointer comparator that  
indicates when the FIFO memory status is empty, empty+1, or empty+2.  
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing  
clock begins the first synchronization cycle of a write if the clock transition  
13  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
occurs at time tSKEW1 or greater after the write. Otherwise, the subse- is defined by the contents of register Y1 for AFA and register Y2 for AFB.  
quent clock cycle can be the first synchronization cycle (see Figures 15, These registers are loaded with preset values during a FlFO reset,  
16, 17, and 18).  
programmed from Port A, or programmed serially (see Almost-Empty  
flag and Almost-Full flag offset programming section). An Almost-Full  
flag is LOW when the number of words in its FIFO is greater than or equal  
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)  
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and to (256-Y) or (1,024-Y) for the IDT72V3624 or IDT72V3644 respec-  
IRB) function is selected. In IDT Standard mode, the Full Flag (FFA and tively. An Almost-Full flag is HIGH when the number of words in its FIFO  
FFB) function is selected. For both timing modes, when the Full/Input is less than or equal to [256-(Y+1)] or [1,024-(Y+1)] for the IDT72V3624  
Ready flag is HIGH, a memory location is free in the FIFO to receive new or IDT72V3644 respectively. Note that a data word present in the FIFO  
data. No memory locations are free when the Full/Input Ready flag is output register has been read from memory.  
LOW and attempted writes to the FIFO are ignored.  
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing  
The Full/Input Ready flag of a FlFO is synchronized to the port clock clock are required after a FIFO read for its Almost-Full flag to reflect the  
that writes data to its array. For both FWFT and IDT Standard modes, new level of fill. Therefore, the Almost-Full flag of a FIFO containing [256/  
each time a word is written to a FIFO, its write pointer is incremented. The 1,024-(Y+1)] or less words remains LOW if two cycles of its synchroniz-  
state machine that controls a Full/Input Ready flag monitors a write ing clock have not elapsed since the read that reduced the number of  
pointer and read pointer comparator that indicates when the FlFO words in memory to [256/1,024-(Y+1)]. An Almost-Full flag is set HIGH  
memory status is full, full-1, or full-2. From the time a word is read from by the second LOW-to-HIGH transition of its synchronizing clock after  
a FIFO, its previous memory location is ready to be written to in a the FIFO read that reduces the number of words in memory to  
minimum of two cycles of the Full/Input Ready flag synchronizing clock. [256/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-Full flag  
Therefore, an Full/Input Ready flag is LOW if less than two cycles of the synchronizing clock begins the first synchronization cycle if it occurs at  
Full/Input Ready flag synchronizing clock have elapsed since the next  
memory write location has been read. The second LOW-to-HIGH  
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets  
the Full/Input Ready flag HIGH.  
time tSKEW2 or greater after the read that reduces the number of words  
in memory to [256/1,024-(Y+1)]. Otherwise, the subsequent synchro-  
nizing clock cycle may be the first synchronization cycle (see Figure 25  
and 26).  
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock  
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat  
timetSKEW1 orgreateraftertheread.Otherwise,thesubsequentclockcycle  
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).  
MAILBOX REGISTERS  
Each FIFO has a 36-bit bypass register to pass command and control  
informationbetweenPortAandPortBwithoutputtingitinqueue.TheMailbox  
select(MBA, MBB)inputschoosebetweenamailregisterandaFIFOfora  
port data transfer operation. The usable width of both the Mail1 and Mail2  
registersmatchestheselectedbussizeforPortB.  
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen  
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the  
selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register  
employsdatalinesA0-A35.IftheselectedPortBbussizeis18bits,thenthe  
usablewidthoftheMail1RegisteremploysdatalinesA0-A17.(Inthiscase,  
A18-A35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits, then  
theusablewidthoftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,  
A9-A35 are don’t care inputs.)  
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2  
RegisterwhenaPortBwriteisselectedbyCSB, W/RB,andENBwithMBB  
HIGH.IftheselectedPortBbussizeisalso36bits,thentheusablewidthof  
theMail2employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,  
thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthis  
case,B18-B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,  
thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B8.(Inthis  
case, B9-B35 are don’t care inputs.)  
ALMOST-EMPTY FLAGS (AEA, AEB)  
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads  
data from its array. The state machine that controls an Almost-Empty flag  
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe  
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.  
Thealmost-emptystateisdefinedbythecontentsofregisterX1forAEBand  
register X2 for AEA. Theseregistersareloadedwithpresetvaluesduringa  
FIFOreset, programmedfromPortA, orprogrammedserially(seeAlmost-  
Empty flag and Almost-Full flag offset programming section). An Almost-  
EmptyflagisLOWwhenitsFIFOcontainsXorlesswordsandisHIGHwhen  
itsFIFOcontains(X+1)ormorewords.AdatawordpresentintheFIFOoutput  
register has been read from memory.  
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock  
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel  
offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords  
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsince  
thewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflagisset  
HIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter  
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition  
ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization  
cycleifitoccursattimetSKEW2 orgreaterafterthewritethatfillstheFIFOto(X+1)  
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)  
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.  
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe  
words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe  
synchronization cycle. (See Figure 23 and 24).  
mail register when the port Mailbox select input is HIGH.  
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition  
onCLKBwhenaPortBreadisselectedbyCSB, W/RB,andENBwithMBB  
ALMOST-FULL FLAGS (AFA, AFB)  
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.  
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthis  
a write pointer and read pointer comparator that indicates when the FIFO case,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailboxdata  
memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate are placed on B0-B8. (In this case, B9-B35 are indeterminate.)  
14  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH data is read from the FIFO1 RAM and before data is written to the FIFO2  
transition on CLKA when a Port A read is selected by CSA, W/RA, and RAM. These bus-matching operations are not available when transferring  
ENA with MBA HIGH.  
data via mailbox registers. Furthermore, both the word- and byte-size  
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. bus selections limit the width of the data bus that can be used for mail  
For an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In register operations. In this case, only those byte lanes belonging to the  
this case, A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of selected word- or byte-size bus can carry mailbox data. The remaining  
mailbox data are placed on A0-A8. (In this case, A9-A35 are indetermi- data outputs will be indeterminate. The remaining data inputs will be  
nate.)  
don’t care inputs. For example, when a word-size bus is selected, then  
The data in a mail register remains intact after it is read and changes mailbox data can be transmitted only between A0-A17 and B0-B17.  
only when new data is written to the register. The Endian select feature When a byte-size bus is selected, then mailbox data can be transmitted  
has no effect on mailbox data. For mail register and Mail Register Flag only between A0-A8 and B0-B8. (See Figures 27 and 28).  
timing diagrams, see Figure 27 and 28.  
BUS-MATCHING FIFO1 READS  
BUS SIZING  
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.Ifalong  
The Port B bus can be configured in a 36-bit long word, 18-bit word, wordbussizeisimplemented, theentirelongwordimmediatelyshiftstothe  
or 9-bit byte format for data read from FIFO1 or written to FIFO2. The FIFO1outputregister.IfbyteorwordsizeisimplementedonPortB,onlythe  
levels applied to the Port B Bus Size select (SIZE) and the Bus-Match firstoneortwobytesappearontheselectedportionoftheFIFO1outputregister,  
select (BM) determine the Port B bus size. These levels should be static with the rest of the long word stored in auxiliary registers. In this case,  
throughout FIFO operation. Both bus size selections are implemented subsequentFIFO1readsoutputtherestofthelongwordtotheFIFO1output  
at the completion of Master Reset, by the time the Full/Input Ready flag register in the order shown by Figure 2.  
is set HIGH, as shown in Figure 2.  
WhenreadingdatafromFIFO1inbyteorwordformat,theunusedB0-B35  
TwodifferentmethodsforsequencingdatatransferareavailableforPort outputsareindeterminate.  
Bwhenthebussizeselectioniseitherbyte-orword-size.Theyarereferred  
toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant  
BUS-MATCHING FIFO2 WRITES  
bytefirst).ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-  
to-HIGHtransitionofMRS1andMRS2selectstheendianmethodthatwillbe  
active during FIFO operation. BE is a don’t care input when the bus size  
selected for Port B is long word. The endian method is implemented at the  
completionofMasterReset,bythetimetheFull/InputReadyflagissetHIGH,  
as shown in Figure 2.  
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten  
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary  
registers.TheCLKBrisingedgethatwritesthefourthbyteorthesecondword  
oflongwordtoFIFO2alsostorestheentirelongwordintheFIFO2memory.  
The bytes are arranged in the manner shown in Figure 2.  
WhenwritingdatatoFIFO2inbyteorwordformat,theunusedB0-B35inputs  
aredon'tcareinputs.  
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories  
on the IDT72V3624/72V3644. Bus-matching operations are done after  
15  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
A35 A27  
A26 A18  
A17 A9  
A8 A0  
BYTE ORDER ON PORT A:  
Write to FIFO1/  
Read from FIFO2  
D
A
B
C
B35 B27  
B26 B18  
B17 B9  
B8 B0  
BYTE ORDER ON PORT B:  
BE BM SIZE  
Read from FIFO1/  
Write to FIFO2  
A
B
D
C
X
L
X
(a) LONG WORD SIZE  
B35 B27  
B35 B27  
B26 B18  
B17 B9  
B8 B0  
1st: Read from FIFO1/  
Write to FIFO2  
BE BM SIZE  
A
B
H
H
L
B26 B18  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
C
D
(b) WORD SIZE  
BIG ENDIAN  
B35 B27  
B35 B27  
B26 B18  
B17 B9  
B8 B0  
1st: Read from FIFO1/  
Write to FIFO2  
BE BM SIZE  
C
D
L
H
L
B26 B18  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
A
B
(c) WORD SIZE  
LITTLE-ENDIAN  
B35 B27  
B35 B27  
B35 B27  
B35 B27  
B26 B18  
B17 B9  
B8 B0  
BE BM SIZE  
1st: Read from FIFO1/  
Write to FIFO2  
A
H
H
H
B26 B18  
B26 B18  
B26 B18  
B17 B9  
B17 B9  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
B
B8 B0  
3rd: Read from FIFO1/  
Write to FIFO2  
C
B8 B0  
4th: Read from FIFO1/  
Write to FIFO2  
D
(d) BYTE SIZE  
BIG-ENDIAN  
B35 B27  
B35 B27  
B35 B27  
B35 B27  
B26 B18  
B17 B9  
B8 B0  
BE BM SIZE  
1st: Read from FIFO1/  
Write to FIFO2  
D
L
H
H
B26 B18  
B26 B18  
B17 B9  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
C
B8 B0  
3rd: Read from FIFO1/  
Write to FIFO2  
B
B26 B18  
B17 B9  
B8 B0  
4th: Read from FIFO1/  
Write to FIFO2  
A
4664 drw04  
(e) BYTE SIZE  
LITTLE-ENDIAN  
Figure 2. Bus Sizing  
16  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
CLKA  
CLKB  
t
RSTS  
tRSTH  
MRS1  
BE/FWFT  
SPM  
t
BEH  
t
BES  
tFWS  
BE  
0,1  
FWFT  
t
SPMS  
t
SPMH  
t
FSS  
tFSH  
FS1,FS0  
FFA/IRA  
EFB/ORB  
AEB  
t
WFF  
t
WFF  
(3)  
REF  
t
t
RSF  
t
RSF  
AFA  
t
RSF  
MBF1  
4664 drw05  
NOTES:  
1. FIFO2 Master Reset (MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2.  
2. PRS1 must be HIGH during Master Reset.  
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.  
Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)  
CLKA  
CLKB  
t
RSTS  
tRSTH  
PRS1  
t
WFF  
t
WFF  
FFA/IRA  
(3)  
tREF  
EFB/ORB  
AEB  
t
RSF  
t
RSF  
AFA  
t
RSF  
MBF1  
4664 drw06  
NOTES:  
1. Partial Reset is performed in the same manner for FIFO2.  
2. MRS1 must be HIGH during Partial Reset.  
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.  
Figure 4. FIFO1 Partial Reset(1) (IDT Standard and FWFT Modes)  
17  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
CLKA  
2
1
4
MRS1,  
MRS2  
t
FSS  
t
FSH  
SPM  
t
FSS  
t
FSH  
0,0  
FS1,FS0  
t
WFF  
FFA/IRA  
(1)  
tSKEW1  
tENS2  
tENH  
ENA  
tDH  
tDS  
A0-A35  
AEB Offset  
AFA Offset  
AFB Offset  
(Y 2)  
AEA Offset  
(X 2)  
First Word to FIFO1  
(X1)  
(Y1)  
CLKB  
1
2
t
WFF  
FFB/IRB  
4664 drw07  
NOTES:  
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising  
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.  
2. CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.  
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)  
CLKA  
4
MRS1,  
MRS2  
t
FSS  
tFSH  
SPM  
FFA/IRA  
FS1/SEN  
t
WFF  
(1)  
SKEW  
t
t
SENS  
t
FSS  
t
SENH  
SDH  
t
SENS  
tSENH  
tSPH  
tSDS  
t
tSDH  
tSDS  
(3)  
FS0/SD  
AFA Offset (Y1) MSB  
AEA Offset (X2) LSB  
CLKB  
4
t
WFF  
4664 drw08  
FFB/IRB  
NOTES:  
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising  
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.  
2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA and FFB/IRB is set HIGH.  
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).  
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)  
18  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKH  
tCLKL  
CLKA  
FFA/IRA HIGH  
t
ENH  
ENH  
t
ENS1  
CSA  
t
ENS2  
t
W/RA  
t
ENS2  
t
ENH  
ENH  
MBA  
ENA  
tENS2  
tENS2  
tENH  
t
ENS2  
tENH  
t
tDS  
tDH  
W1(1)  
W2(1)  
A0 - A35  
No Operation  
4664 drw09  
NOTE:  
1. Written to FIFO1.  
Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
tCLK  
tCLKH  
tCLKL  
CLKB  
FFB/IRB HIGH  
tENS1  
tENS2  
tENS2  
t
ENH  
CSB  
tENH  
W/RB  
tENH  
MBB  
tENS2  
tENS2  
tENH  
tENH  
tENS2  
tENH  
ENB  
tDH  
tDS  
W1(1)  
W2(1)  
B0-B35  
No Operation  
4664 drw10  
NOTE:  
1. Written to FIFO2.  
DATA SIZE TABLE FOR LONG-WORD WRITES TO FIFO2  
SIZE MODE(1)  
SIZE  
DATA WRITTEN TO FIFO2  
DATA READ FROM FIFO2  
BM  
BE  
B35-B27  
B26-B18  
B17-B9  
B8-B0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
L
X
X
A
B
C
D
A
B
C
D
NOTE:  
1. BE is selected at Master Reset: BM and SIZE must be static throughout device operation.  
Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
19  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
CLKB  
tENS1  
FFB/IRB HIGH  
tENH  
CSB  
tENS2  
W/RB  
tENS2  
tENS2  
tENH  
tENH  
MBB  
tENS2  
tENS2  
tENH  
tENH  
ENB  
tDH  
tDS  
B0-B17  
4664 drw11  
DATA SIZE TABLE FOR WORD WRITES TO FIFO2  
SIZE MODE(1)  
WRITE  
NO.  
DATA WRITTEN  
TO FIFO2  
DATA READ FROM FIFO2  
BM  
SIZE  
BE  
B17-B9  
B8-B0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
1
2
1
2
A
B
H
L
H
A
B
C
D
D
C
C
A
D
D
B
H
L
L
A
B
C
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
CLKB  
tENS1  
FFB/IRB HIGH  
tENH  
CSB  
tENS2  
W/RB  
MBB  
tENH  
tENH  
tENS2  
tENS2  
tENH  
tENS2  
tENH  
ENB  
tDS  
tDH  
B0-B8  
4664 drw12  
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2  
SIZE MODE(1)  
WRITE  
NO.  
DATA WRITTEN  
TO FIFO2  
DATA READ FROM FIFO2  
BM  
SIZE  
BE  
B8-B0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
H
A
B
C
D
H
L
A
B
C
D
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
20  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKH  
tCLKL  
CLKB  
EFB/ORB  
HIGH  
CSB  
W/RB  
MBB  
tENH  
tENS2  
tENH  
tENS2  
tENH  
tENS2  
ENB  
t
MDV  
No Operation  
W2(1)  
tDIS  
t
A
t
A
t
EN  
(1)  
W1  
B0-B35  
Previous Data  
(Standard Mode)  
t
MDV  
tDIS  
tA  
t
A
OR  
tEN  
W2(1)  
W3(1)  
(1)  
B0-B35  
W1  
(FWFT Mode)  
4664 drw13  
NOTE:  
1. Read From FIFO1.  
DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1  
SIZE MODE(1)  
SIZE  
DATA WRITTEN TO FIFO1  
DATA READ FROM FIFO1  
BM  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B35-B27  
B26-B18  
B17-B9  
B8-B0  
L
X
X
A
B
C
D
A
B
C
D
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .  
Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
CLKB  
HIGH  
EFB/ORB  
CSB  
W/RB  
MBB  
ENB  
t
ENS2  
tENH  
No Operation  
Read 2  
t
MDV  
t
A
tA  
t
DIS  
DIS  
t
EN  
B0-B17  
Previous Data  
Read 1  
Read 2  
(Standard Mode)  
t
MDV  
OR  
t
A
tA  
t
t
EN  
B0-B17  
(FWFT Mode)  
Read 3  
Read 1  
4664 drw14  
NOTE:  
1. Unused word B18-B35 are indeterminate for word-size reads.  
DATA SIZE TABLE FOR WORD READS FROM FIFO1  
SIZE MODE(1)  
SIZE  
DATA WRITTEN TO FIFO1  
READ NO.  
DATA READ FROM FIFO1  
BM  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B17-B9  
B8-B0  
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .  
Figure 12. Port-B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
21  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
CLKB  
EFB/ORB  
HIGH  
CSB  
W/RB  
MBB  
tENS2  
tENH  
ENB  
No Operation  
t
DIS  
DIS  
t
MDV  
t
A
t
A
t
A
t
A
t
EN  
B0-B8  
Read 2  
Read 1  
Previous Data  
Read 4  
Read 5  
Read 3  
(Standard Mode)  
t
MDV  
t
OR  
t
A
tA  
tA  
t
A
t
EN  
B0-B8  
Read 1  
Read 2  
Read 3  
Read 4  
(FWFT Mode)  
4664 drw15  
NOTE:  
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.  
DATA SIZE TABLE FOR BYTE READS FROM FIFO1  
SIZE MODE(1)  
DATA WRITTEN TO FIFO1  
READ  
NO.  
DATA READ  
FROM FIFO1  
BM  
SIZE  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B8-B0  
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
H
A
B
C
D
H
L
A
B
C
D
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
tCLK  
tCLKL  
tCLKH  
CLKA  
EFA/ORA HIGH  
CSA  
W/RA  
MBA  
tENS2  
tENS2  
tENH  
tENH  
tENH  
tENS2  
ENA  
No Operation  
W2(1)  
t
MDV  
t
DIS  
DIS  
t
A
t
A
t
EN  
A0-A35  
W1(1)  
W2(1)  
Previous Data  
(Standard Mode)  
t
MDV  
t
tA  
t
A
OR  
t
EN  
A0-A35  
(1)  
W1  
W3(1)  
(FWFT Mode)  
4664 drw16  
NOTE:  
1. Read From FIFO2.  
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
22  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKL  
tCLKH  
CLKA  
CSA  
LOW  
HIGH  
W/RA  
tENS2  
tENH  
MBA  
tENS2  
tENH  
ENA  
IRA  
HIGH  
tDS  
tDH  
A0-A35  
W1  
t
CLKtCLKL  
(1)  
tCLKH  
tSKEW1  
CLKB  
1
2
3
t
REF  
tREF  
ORB  
FIFO1 Empty  
LOW  
CSB  
W/RB  
HIGH  
LOW  
MBB  
tENS2  
tENH  
ENB  
tA  
Old Data in FIFO1 Output Register  
W1  
B0-B35  
4664 drw17  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.  
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB  
cycle later than shown.  
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)  
23  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
t
CLK  
t
CLKL  
t
CLKH  
CLKA  
CSA  
LOW  
HIGH  
W/RA  
t
ENS2  
t
ENH  
ENH  
MBA  
t
t
ENS2  
ENA  
FFA  
HIGH  
tDS  
tDH  
W1  
A0-A35  
t
CLK  
CLKH  
(1)  
SKEW1  
t
tCLKL  
t
CLKB  
1
2
t
REF  
t
REF  
FIFO1 Empty  
LOW  
EFB  
CSB  
W/RB  
HIGH  
LOW  
MBB  
tENH  
tENS2  
ENB  
tA  
W1  
B0-B35  
4664 drw18  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising  
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.  
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 16. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)  
24  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKH  
tCLKL  
CLKB  
CSB  
LOW  
LOW  
W/RB  
MBB  
ENB  
tENS2  
tENH  
tENH  
tENS2  
IRB  
HIGH  
tDH  
tDS  
W1  
B0-B35  
t
CLK  
(1)  
tCLKH  
t
CLKL  
tSKEW1  
1
2
CLKA  
ORA  
3
t
REF  
tREF  
FIFO2 Empty  
CSA  
LOW  
LOW  
LOW  
W/RA  
MBA  
ENA  
tENS2  
tENH  
tA  
Old Data in FIFO2 Output Register  
W1  
A0-A35  
4664 drw19  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.  
If the time between the CLKB edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA  
cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.  
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)  
25  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
t
CLK  
t
CLKL  
t
CLKH  
CLKB  
CSB  
LOW  
LOW  
W/RB  
t
ENS2  
ENS2  
tENH  
MBB  
ENB  
t
tENH  
HIGH  
FFB  
tDH  
tDS  
W1  
B0-B35  
(1)  
t
CLK  
tSKEW1  
t
CLKH  
t
CLKL  
1
2
CLKA  
t
REF  
t
REF  
EFA  
FIFO2 Empty  
LOW  
LOW  
LOW  
CSA  
W/RA  
MBA  
tENS2  
tENH  
ENA  
tA  
A0-A35  
W1  
4664 drw20  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising  
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.  
Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)  
26  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKH  
tCLKL  
CLKB  
CSB  
LOW  
W/RB  
HIGH  
LOW  
MBB  
tENS2  
tENH  
tA  
ENB  
ORB  
HIGH  
Previous Word in FIFO1 Output Register  
Next Word From FIFO1  
B0-B35  
(1)  
tCLK  
tSKEW1  
tCLKH  
tCLKL  
1
2
CLKA  
tWFF  
tWFF  
FIFO1 Full  
IRA  
CSA  
LOW  
W/RA  
HIGH  
tENH  
tENH  
tDH  
tENS2  
tENS2  
tDS  
MBA  
ENA  
Write  
A0-A35  
4664 drw21  
To FIFO1  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising  
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.  
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)  
tCLK  
tCLKH  
tCLKL  
CLKB  
LOW  
CSB  
W/RB  
MBB  
HIGH  
LOW  
tENS2  
tENH  
tA  
ENB  
EFB  
HIGH  
Previous Word in FIFO1 Output Register  
Next Word From FIFO1  
B0-B35  
(1)  
tCLK  
tSKEW1  
tCLKH  
tCLKL  
CLKA  
1
2
tWFF  
tWFF  
FFA  
CSA  
FIFO1 Full  
LOW  
W/RA  
HIGH  
tENS2  
tENS2  
tENH  
tENH  
MBA  
ENA  
tDH  
tDS  
Write  
A0-A35  
4664 drw22  
To FIFO1  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising  
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.  
Figure 20. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)  
27  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKH  
tCLKL  
CLKA  
LOW  
LOW  
LOW  
CSA  
W/RA  
MBA  
tENS2  
tENH  
ENA  
ORA  
HIGH  
tA  
Previous Word in FIFO2 Output Register  
SKEW1  
Next Word From FIFO2  
A0-A35  
(1)  
tCLK  
t
tCLKH  
tCLKL  
1
2
CLKB  
t
WFF  
t
WFF  
IRB  
CSB  
FIFO2 FULL  
LOW  
W/RB  
LOW  
tENS2  
tENH  
MBB  
ENB  
tENS2  
tENH  
tDS  
tDH  
Write  
B0-B35  
4664 drw23  
To FIFO2  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising  
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.  
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.  
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)  
28  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
tCLK  
tCLKH  
tCLKL  
CLKA  
LOW  
LOW  
LOW  
CSA  
W/RA  
MBA  
tENS2  
tENH  
ENA  
EFA  
HIGH  
tA  
Previous Word in FIFO2 Output Register  
Next Word From FIFO2  
A0-A35  
(1)  
tCLK  
tSKEW1  
tCLKH  
tCLKL  
CLKB  
1
2
t
WFF  
t
WFF  
FIFO2 Full  
LOW  
FFB  
CSB  
W/RB  
LOW  
tENS2  
tENH  
MBB  
ENB  
t
ENS2  
t
ENH  
tDS  
tDH  
Write  
B0-B35  
4664 drw24  
To FIFO2  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising  
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.  
2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.  
Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)  
29  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
CLKA  
tENS2  
tENH  
ENA  
(1)  
tSKEW2  
1
2
CLKB  
t
PAE  
t
PAE  
AEB X1 Words in FIFO1  
(X1+1) Words in FIFO1  
ENS2  
t
t
ENH  
ENB  
4664 drw25  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising  
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.  
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.  
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 23. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)  
CLKB  
tENS2  
tENH  
ENB  
(1)  
tSKEW2  
1
2
CLKA  
t
PAE  
t
PAE  
AEA  
X2 Words in FIFO2  
(X2+1) Words in FIFO2  
ENS2  
tENH  
t
ENA  
4664 drw26  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising  
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.  
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.  
3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.  
Figure 24. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)  
(1)  
tSKEW2  
1
2
CLKA  
ENA  
tENS2  
tENH  
t
PAF  
t
PAF  
(D-Y1) Words in FIFO1  
[D-(Y1+1)] Words in FIFO1  
AFA  
CLKB  
ENB  
tENS2  
tENH  
4664 drw27  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising  
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.  
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.  
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 1,024 for the IDT72V3644.  
4. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.  
Figure 25. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)  
30  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
(1)  
tSKEW2  
1
2
CLKB  
ENB  
tENH  
tENS2  
t
PAF  
t
PAF  
(D-Y2) Words in FIFO2  
AFB  
[D-(Y2+1)] Words in FIFO2  
CLKA  
ENA  
tENS2  
tENH  
4664 drw28  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising  
CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.  
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.  
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 1,024 for the IDT72V3644.  
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.  
Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)  
CLKA  
tENS1  
t
ENH  
ENH  
CSA  
tENS2  
t
W/RA  
tENS2  
tENH  
MBA  
tENS2  
tENH  
ENA  
tDH  
tDS  
W1  
A0-A35  
CLKB  
t
PMF  
t
PMF  
MBF1  
CSB  
W/RB  
MBB  
ENB  
tENH  
tENS2  
t
PMR  
tEN  
t
MDV  
tDIS  
B0-B35  
W1 (Remains valid in Mail1 Register after read)  
4664 drw29  
FIFO1 Output Register  
NOTE:  
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be  
indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data  
(B9-B35 will be indeterminate).  
Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)  
31  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
CLKB  
tENS1  
tENH  
CSB  
W/RB  
MBB  
ENB  
t
ENS2  
t
ENH  
tENS2  
t
ENH  
tENS2  
t
t
ENH  
DH  
tDS  
W1  
B0-B35  
CLKA  
t
PMF  
tPMF  
MBF2  
CSA  
W/RA  
MBA  
ENA  
tENH  
tENS2  
t
PMR  
tEN  
tDIS  
t
MDV  
A0-A35  
W1 (Remains valid in Mail 2 Register after read)  
FIFO2 Output Register  
4664 drw30  
NOTE:  
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data  
(A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’t care inputs). In this  
second case, A0-A8 will have valid data (A9-A35 will be indeterminate).  
Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)  
32  
IDT72V3624/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING  
256 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALTEMPERATURERANGE  
PARAMETER MEASUREMENT INFORMATION  
3.3V  
330Ω  
From Output  
Under Test  
30 pF (1)  
510Ω  
PROPAGATION DELAY  
LOAD CIRCUIT  
3V  
3V  
Timing  
Input  
1.5V  
High-Level  
1.5V  
Input  
GND  
1.5V  
GND  
3V  
t
S
th  
tW  
3V  
Data,  
Enable  
Input  
1.5V  
1.5V  
Low-Level  
1.5V  
1.5V  
GND  
Input  
GND  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
VOLTAGE WAVEFORMS  
PULSE DURATIONS  
3V  
Output  
Enable  
1.5V  
1.5V  
t
PZL  
GND  
tPLZ  
3V  
≈ 3V  
Input  
1.5V  
1.5V  
1.5V  
Low-Level  
Output  
GND  
V
OL  
tPD  
t
PZH  
tPD  
V
OH  
V
OH  
≈ OV  
In-Phase  
Output  
1.5V  
1.5V  
High-Level  
Output  
1.5V  
V
t
PHZ  
OL  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
4664 drw31  
NOTE:  
1. Includes probe and jig capacitance.  
Figure 29. Output Load and AC Test Conditions  
33  
ORDERING INFORMATION  
X
XXXXXX  
X
XX  
X
X
X
Device Type Power  
Speed  
Package  
Process/  
Temperature  
Range  
BLANK  
8
Tube or Tray  
Tape and Reel  
BLANK  
G
Commercial (0°C to +70°C)  
Green  
Thin Quad Flat Pack (TQFP, PK128)  
PF  
10  
15  
Clock Cycle Time (tCLK  
)
Commercial Only  
Low Power  
Speed in Nanoseconds  
L
72V3624 256 x 36 x 2 ⎯ 3.3V SyncBiFIFO  
™
with Bus-Matching  
72V3644  
1,024 x 36 x 2 ⎯ 3.3V SyncBiFIFO  
™
with Bus-Matching  
4664 drw32  
NOTES:  
1. Industrial temperature range is available by special order.  
2. Green parts are available. For specific speeds and packages contact your sales office.  
DATASHEETDOCUMENTHISTORY  
12/12/2000  
03/21/2001  
08/01/2001  
02/10/2009  
03/09/2015  
pg. 12.  
pgs. 6 and 7.  
pgs. 6, 8, 9 and 34.  
pg. 34.  
pgs. 1-34.  
CORPORATE HEADQUARTERS  
for SALES:  
for Tech Support:  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
408-360-1753  
email:FIFOhelp@idt.com  
www.idt.com  
34  

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