72V3673L15PF [IDT]
TQFP-128, Tray;型号: | 72V3673L15PF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | TQFP-128, Tray |
文件: | 总30页 (文件大小:303K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36
4,096 x 36
8,192 x 36
IDT72V3653
IDT72V3663
IDT72V3673
• Retransmit Capability
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
FEATURES
• Memory storage capacity:
IDT72V3653
IDT72V3663
IDT72V3673
–
–
–
2,048 x 36
4,096 x 36
8,192 x 36
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Clock frequencies up to 100 MHz (6.5 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723653/723663/723673
• Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• Big- or Little-Endian format for word and byte bus sizes
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
W/RA
Control
ENA
Logic
MBA
36
RAM ARRAY
36
36
FIFO1
Mail1,
Mail2,
Reset
Logic
2,048 x 36
4,096 x 36
8,192 x 36
RS1
RS2
PRS
36
RT
RTM
FIFO
Retransmit
Logic
Write
Pointer
Read
Pointer
A0-A35
B0-B35
Status Flag
Logic
EF/OR
AE
FF/IR
AF
36
36
FS2
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
Timing
Mode
FWFT
13
CLKB
CSB
W/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
SIZE
Mail 2
Register
4662 drw01
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncFIFO™isatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2009
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4662/4
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
fastas6.5ns. The2,048/4,096/8,192x36dual-portSRAMFIFObuffersdata
fromPortAtoPortB. FIFOdataonPortBcanoutputin36-bit,18-bit,or9-bit
formatswithachoiceofBig-orLittle-Endianconfigurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
DESCRIPTION
TheIDT72V3653/72V3663/72V3673arepinand functionallycompatible
versionsoftheIDT723653/723663/723673,designedtorunoffa3.3Vsupply
forexceptionallylowpowerconsumption. Thesedevicesaremonolithic,high-
speed,low-power,CMOSunidirectionalSynchronous(clocked)FIFOmemory
whichsupportsclockfrequenciesupto100MHzandhasreadaccesstimesas
PIN CONFIGURATION
INDEX
1
CLKB
102
W/RA
2
Vcc
101
ENA
3
Vcc
100
CLKA
4
B35
99
GND
5
B34
98
A35
6
B33
97
A34
7
B32
96
A33
8
9
RTM
GND
B31
B30
B29
B28
B27
B26
Vcc
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
B25
B24
BM
A24
A23
BE/FWFT
GND
A22
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
4662 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or ORfunctionsareselectedintheFirstWordFallThroughmode. IRindicates
coincident. The enables for each port are arranged to provide a simple whetherornottheFIFOhasavailablememorylocations. ORshowswhether
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- theFIFOhasdataavailableforreadingornot. Itmarksthepresenceofvalid
nouscontrol.
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox
dataontheoutputs.
TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogram-
registers. Themailboxregisters'widthmatchestheselectedPortBbuswidth. mableAlmost-Fullflag(AF).AE indicateswhenaselectednumberofwords
Eachmailboxregisterhas a flag(MBF1 andMBF2)tosignalwhennewmail remainintheFIFOmemory. AFindicateswhentheFIFOcontainsmorethan
has beenstored.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
aselectednumberofwords.
FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray intoitsarray. EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
andselectsserialflagprogramming,parallelflagprogramming,oroneoffive reads data from its array. Programmable offsets for AE and AF are loaded
possibledefaultflagoffsetsettings,8,16,64,256or1,024.
inparallelusingPortAorinserialviatheSDinput.Fivedefaultoffsetsettings
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe are also provided. The AE threshold can be set at 8, 16, 64, 256 or 1,024
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e., locations fromthe emptyboundaryandthe AF thresholdcanbe setat8, 16,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset 64,256or1,024locationsfromthefullboundary. Allthesechoicesaremade
is useful since it permits flushing of the FIFO memory without changing any using the FS0, FS1 and FS2 inputs during Reset.
configurationsettings.
InterspersedParityisavailableandcanbeselectedduringaMasterReset
TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfour oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming
clockcyclesofCLKAandCLKB,bytakingtheRetransmitpin,RTLOWwhile oftheflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
theRetransmitModepin,RTMisHIGH.WhenaRetransmitisperformedthe Parityis selectedthendatalineA8willbecomeavalidbit.
readpointerisresettothefirstmemorylocation.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, InFirstWordFallThroughmode,morethanonedevicemaybeconnectedin
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A seriestocreategreaterworddepths. Theadditionofexternalcomponentsis
read operation is required to access that word (along with all other words unnecessary.
residing in memory). In the First Word Fall Through mode (FWFT), the first
If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill
wordwrittentoanemptyFIFOappearsautomaticallyontheoutputs,noread automatically power down. During the power down state, supply current
operationrequired(Nevertheless,accessingsubsequentwordsdoesneces- consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
sitate a formal read request). The state of the BE/FWFT pin during Reset inputs)willimmediatelytakethedeviceoutofthePowerDownstate.
determinesthemodeinuse.
TheIDT72V3653/72V3663/72V3673arecharacterizedforoperationfrom
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a 0°C to 70°C. Industrial temperature range (-40°C to +85°C)is available by
combined Full/Input Ready Flag (FF/IR). The EF and FF functions are specialorder. TheyarefabricatedusingIDT’shighspeed,submicronCMOS
selected in the IDT Standard mode. EF indicates whether or not the FIFO technology.
memory is empty. FF shows whether the memory is full or not. The IR and
3
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/O
O
36-bitbidirectionaldataportforsideA.
AE
Almost-EmptyFlag
(Port B)
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsin
theFIFOis less thanorequaltothevalueintheAlmost-EmptyBoffsetregister,X.
AF
Almost-FullFlag
(Port A)
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty
locations intheFIFOis less thanorequaltothevalueintheAlmost-FullAoffsetregister,Y.
B0-B35
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
BE/FWFT
Big-Endian/
FirstWord
Fall Through
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
Inthis case, dependingonthe bus size, the mostsignificantbyte orwordwrittentoPortAis read
fromPortBfirst. ALOWonBEwillselectLittle-Endianoperation. Inthiscase,theleastsignificant
byteorwordwrittentoPortAisreadfromPortBfirst. AfterMasterReset,thispinselectsthetiming
mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through
mode. Once the timingmode has beenselected, the levelon FWFT mustbe staticthroughout
deviceoperation.
(1)
BM
Bus-MatchSelect
(Port B)
I
I
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endianarrangementforPortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.
CLKA
CLKB
PortAClock
PortBClock
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbe
asynchronous or coincident to CLKA. EF/OR and AE are synchronized to the LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EF/OR
Empty/Output
Ready Flag
(Port B)
O
This is adualfunctionpin.IntheIDTStandardmode,the EFfunctionis selected. EFindicates
whetherornottheFIFOmemoryisempty. IntheFWFTmode,the ORfunctionisselected. ORindicates
thepresenceofvaliddataontheB0-B35outputs,availableforreading. EF/ORissynchronizedtothe
LOW-to-HIGHtransitionofCLKB.
ENA
ENB
FF/IR
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
Full/Input
Ready Flag
(Port A)
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FF functionis selected. FF indicates
whetherornotthe FIFOmemoryis full. Inthe FWFTmode, the IRfunctionis selected. IR
indicates whether or not there is space available for writing to the FIFO memory. FF/IRis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FS0/SD
FlagOffsetSelect0/
SerialData,
I
FS1/SEN andFS0/SDare dual-purpose inputs usedforflagoffsetregisterprogramming. During
Reset,FS1/SENandFS0/SD,togetherwithFS2selecttheflagoffsetprogrammingmethod.
Threeoffsetregisterprogrammingmethodsareavailable:automaticallyloadoneoffivepreset
values (8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load.
FS1/SEN
FlagOffsetSelect1/
SerialEnable
I
I
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenable
synchronous totheLOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW,arisingedgeon
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
to program the offset registers is 22 for the 72V3653, 24 for the 72V3663, and 26 for the 72V3673.
ThefirstbitwritestorestheY-registerMSBandthelastbitwritestorestheX-registerLSB.
FS2(1)
FlagOffsetSelect2
4
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutputand
aLOWlevelselectsFIFOdataforoutput.
MBF1
Mail1RegisterFlag
Mail2RegisterFlag
Resets
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
following either a Reset (RS1) or Partial Reset (PRS).
MBF2
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.
Writes tothe mail2 registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
followingeithera Reset(RS2)orPartialReset(PRS).
RS1, RS2
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes. ALOW-to-HIGHtransitiononRS1selectstheprogramming
method(serialorparallel)andoneoffiveprogrammableflag defaultoffsets. ItalsoconfiguresPort
Bforbus sizeandendianarrangement. FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-
HIGHtransitions ofCLKBmustoccurwhile RS1 is LOW.
PRS/
RT
PartialReset/
Retransmit
I
ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM
pin.IfRTMisLOW,thenaLOWonthispininitializestheFIFOreadandwritepointerstothefirstlocation
ofmemoryandsets thePortBoutputregistertoallzeroes. DuringPartialReset, thecurrently
selectedbussize,endian arrangement,programmingmethod(serialorparallel),andprogrammable
flagsettingsareallretained.IfRTMisHIGH,thenaLOWonthispinperformsaRetransmitandinitializes
thereadpointeronly,tothefirstmemorylocation.
RTM
RetransmitMode
I
I
ThispinisusedinconjunctionwiththeRTpin.WhenRTMisHIGHaRetransmitisperformedwhen
RT is taken HIGH.
(1)
SIZE
BusSizeSelect
(Port B)
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
whenBMis HIGHselects word(18-bit)bus size. SIZEworks withBMandBEtoselectthebus size
andendianarrangementforPortB. The levelofSIZEmustbe staticthroughoutdevice operation.
W/RA
PortAWrite/
ReadSelect
I
I
AHIGHselectsawriteoperationandaLOWselectsareadoperationonPortAforaLOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe HIGH impedancestatewhenW/RAisHIGH.
W/RB
PortBWrite/
ReadSelect
ALOWselectsawriteoperationandaHIGHselectsareadoperationonPortBforaLOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RBis LOW.
NOTE:
1. FS2, BM and Size inputs are not TTL compatible. These inputs should be tied to GND or VCC.
5
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
VCC
VI(2)
Rating
Commercial
–0.5to+4.6
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
V
VO(2)
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
SupplyVoltagefor10ns
SupplyVoltagefor15ns
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
Min. Typ.
Max.
3.45
3.6
Unit
V
(1)
VCC
3.15 3.3
VCC
VIH
VIL
IOH
IOL
3.0
2
3.3
—
—
—
—
—
V
VCC+0.5
0.8
V
—
—
—
0
V
–4
mA
mA
°C
8
TA
70
NOTES:
1. For 10ns speed grade: Vcc = 3.3V ± ± 0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3653
IDT72V3663
IDT72V3673
Commercial
tCLK = 10, 15ns(3)
Symbol
Parameter
OutputLogic"1"Voltage
Test Conditions
Min.
Typ.
Max.
Unit
VOH
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
IOH = –4 mA
2.4
—
—
V
VOL
ILI
OutputLogic"0"Voltage
IOL = 8 mA
—
—
—
—
—
—
—
—
—
—
—
—
4
0.5
10
10
1
V
Input Leakage Current (Any Input)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
µA
µA
mA
mA
pF
ILO
ICC3(2)
ICC2(2)
Standby Current (No Clocks running)
VI = VCC - 0.2V or 0
Standby Current (With CLKA & CLKB running) VCC = 3.6V,
VI = VCC - 0.2V or 0
f = 1 MHz
5
(4)
CIN
InputCapacitance
OutputCapacitance
VI = 0,
—
—
(4)
COUT
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
VO = 0,
f = 1 MHZ
8
pF
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Commercial-10ns speed grade only: Vcc = 3.3V ± ±0.15V, TA = 0°±to +70°; JEDEC JESD8-A compliant
4. Characterized values, not currently tested.
6
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingaFIFOontheIDT72V3653/72V3663/72V3673withCLKA
andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected
tonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT72V3653/72V3663/72V3673inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)
N
where:
N
CL
fo
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
output capacitance load
switchingfrequencyofanoutput
100
90
VCC = 3.6V
80
70
60
VCC = 3.0V
VCC = 3.3V
fdata = 1/2 fS
TA = 25°C
CL = 0 pF
50
40
30
20
10
0
100
0
10
20
30
40
50
60
70
90
80
4662 drw03
fS ⎯±Clock Frequency
⎯
MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0ο±C to +70ο C; JEDEC JESD8-A compliant)
IDT72V3653L10(4) IDT72V3653L15
IDT72V3663L10(4) IDT72V3663L15
IDT72V3673L10(4) IDT72V3673L15
Symbol
Parameter
Clock Frequency, CLKA or CLKB
Min.
—
10
4.5
4.5
3
Max.
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
—
15
6
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
fS
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
ns
PulseDuration,CLKAandCLKBLOW
6
ns
SetupTime, A0-A35before CLKA↑andB0-B35before CLKB↑
SetupTime, CSA andW/RAbeforeCLKA↑;CSB andW/RBbeforeCLKB↑
Setup Time, ENA, and MBA before CLKA↑;ENBandMBBbefore CLKB↑
4
ns
tENS1
tENS2
tRSTS
tFSS
4
4.5
4.5
5
ns
3
ns
(1)
SetupTime, RS1orPRS LOWbefore CLKA↑±orCLKB↑
5
ns
Setup Time, FS0, FS1 and FS2 before RS1 HIGH
Setup Time, BE/FWFT before RS1 HIGH
SetupTime,FS0/SDbeforeCLKA↑
7.5
7.5
3
7.5
7.5
4
ns
tBES
ns
tSDS
ns
tSENS
tFWS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
ns
SetupTime,FWFTbeforeCLKA↑
0
0
ns
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
Setup Time, RTM before RT1; RTM before RT2
0.5
5
1
ns
tRTMS
tENH
5
ns
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB
afterCLKB↑
0.5
1
ns
(1)
tRSTH
tFSH
Hold Time, RS1 or PRS LOW after CLKA↑±or CLKB↑
4
2
—
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time, FS0, FS1 and FS2 after RS1 HIGH
Hold Time, BE/FWFT after RS1 HIGH
tBEH
2
2
tSDH
HoldTime, FS0/SDafterCLKA↑
0.5
0.5
2
1
tSENH
tSPH
HoldTime,FS1/SENHIGHafterCLKA↑
1
Hold Time, FS1/SEN HIGH after RS1 HIGH
Hold Time, RTM after RT1; RTM after RT2
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
2
tRTMH
tSKEW1(2)
5
5
5
7.5
12
tSKEW2(2,3) Skew Time between CLKA↑ and CLKB↑ for AE and AF
12
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
4. For 10ns speed grade: Vcc = 3.3V ± ±0.15V; TA = 0°±to +70°.
8
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0ο±C to +70ο C;JEDEC JESD8-A compliant)
IDT72V3653L10(3) IDT72V3653L15
IDT72V3663L10(3) IDT72V3663L15
IDT72V3673L10(3) IDT72V3673L15
Symbol
tA
Parameter
Min.
2
Max.
6.5
6.5
6.5
6.5
6.5
6.5
Min.
2
Max.
10
8
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑±toB0-B35
PropagationDelayTime, CLKA↑to FF/IR
PropagationDelayTime,CLKB↑toEF/OR
PropagationDelayTime,CLKB↑toAE
PropagationDelayTime,CLKA↑toAF
tWFF
tREF
tPAE
tPAF
tPMF
2
2
ns
1
1
8
ns
1
1
8
ns
1
1
8
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 and CLKB↑ to MBF2
LOW or MBF1 HIGH
0
0
8
ns
tPMR
tMDV
tRSF
PropagationDelayTime, CLKA↑ toB0-B35(1) andCLKB↑ toA0-A35(2)
3
3
1
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
6.5
10
Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF HIGH, MBF1
HIGH and MBF2 HIGH
tEN
tDIS
Enable Time, CSA andW/RALOWtoA0-A35Active andCSB LOWandW/RB
2
1
6
6
2
1
10
8
ns
ns
HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or
W/RBLOWtoB0-B35athighimpedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. For 10ns speed grade: Vcc = 3.3V ± ±0.15V; TA = 0°±to +70°.
9
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
SIGNALDESCRIPTION
— ENDIAN SELECTION
RESET (RS1, RS2)
Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionis
active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread
fromPortB. Thisselectiondeterminestheorderbywhichbytes(orwords)of
dataaretransferredthroughthisport. Forthefollowingillustrations,assume
thata byte (orword)bus size has beenselectedforPortB. (Note thatwhen
Port B is configured for a long word size, the Big-Endian function has no
Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW
pulsetoRS1andRS2simultaneously. Afterwards,theFIFOmemoryofthe
IDT72V3653/72V3663/72V3673 undergoes a complete reset by taking its
Reset(RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfour
PortBclock(CLKB)LOW-to-HIGHtransitions.TheResetinputs canswitch
asynchronouslytothe clocks. AResetinitializes the internalreadandwrite
pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output
Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Full flag (AF) HIGH. A Reset (RS1) also forces the Mailbox flag (MBF1) of
theparallelmailboxregisterHIGH,andatthesametimethe RS2andMBF2
operatelikewise. AfteraReset,theFIFO’sFull/InputReadyflagissetHIGH
aftertwowriteclockcyclestobeginnormaloperation.
A LOW-to-HIGH transition on the FlFO Reset (RS1) input latches the
valueoftheBig-Endian(BE)inputfordeterminingtheorderbywhichbytesare
transferredthroughPortB.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe
valuesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag
Programming, and Almost-Empty and Almost-Full flag offset programming
section). The relevantResettimingdiagramcanbe foundinFigure 3.
1
applicationandthe BEinputis a “don’tcare” .)
AHIGHonthe BE/FWFT inputwhenthe Reset(RS1)inputgoes from
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort
Bfirst;theleastsignificantbyte(word)ofthelongwordwrittentoPortAwillbe
readfromPortBlast.
A LOW on the BE/FWFT input when the Reset (RS1) input goes from
LOWtoHIGHwillselectaLittle-Endianarrangement. Inthis case,theleast
significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort
Bfirst;themostsignificantbyte(word)ofthelongwordwrittentoPortAwillbe
readfromPortBlast. RefertoFigure2foranillustrationoftheBEfunction.See
Figure3(Reset)foranEndianselecttimingdiagram.
— TIMING MODE SELECTION
AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT)mode. OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT
inputduringthenextLOW-to-HIGHtransitionofCLKA andCLKB willselect
IDTStandardmode. ThismodeusestheEmptyFlagfunction(EF)toindicate
whetherornotthereareanywords presentintheFIFOmemory. Ituses the
Full Flag function (FF) to indicate whether or not the FIFO memory has any
freespaceforwriting. InIDTStandardmode,everywordreadfromtheFIFO,
includingthefirst,mustberequestedusingaformalreadoperation.
Once the Reset (RS1) input is HIGH, a LOW on the BE/FWFT input
duringthenextLOW-to-HIGHtransitionofCLKA andCLKBwillselectFWFT
mode. ThismodeusestheOutputReadyfunction(OR)toindicatewhetheror
notthereisvaliddataatthedataoutputs(B0-B35). ItalsousestheInputReady
function(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespace
forwriting. Inthe FWFTmode, the firstwordwrittentoanemptyFIFOgoes
directlytodataoutputs,noreadrequestnecessary. Subsequentwordsmust
beaccessedbyperformingaformalreadoperation.
PARTIAL RESET (PRS)
TheFIFOmemoryoftheIDT72V3653/72V3663/72V3673undergoesa
limitedresetbytakingitsPartialReset(PRS)inputLOWforatleastfourPort
Aclock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.The
RTMpinmustbeLOWduringthetimeofPartialReset. ThePartialResetinput
canswitchasynchronouslytotheclocks. APartialResetinitializestheinternal
readandwritepointersandforcestheFull/InputReadyflag(FF/IR)LOW,the
Empty/OutputReadyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,
andthe Almost-Fullflag(AF)HIGH. APartialResetalsoforces the Mailbox
flag(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,
theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteClockcyclestobegin
normal operation. See Figure 4, Partial Reset (IDT Standard and FWFT
Modes)fortherelevanttimingdiagram.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof
the reset operation. A Partial Reset may be useful in the case where
reprogrammingaFIFOfollowingaResetwouldbeinconvenient.
Following Reset,thelevelappliedtotheBE/FWFTinputtochoosethe
desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto
Figure 3(Reset)fora FirstWordFallThroughselecttimingdiagram.
RETRANSMIT (RT)
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
TworegistersintheIDT72V3653/72V3663/72V3673areusedtoholdthe
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag
(AE) Offset register is labeled X and Almost-Full flag (AF) Offset register is
labeledY.Theoffsetregisterscanbeloadedwithpresetvaluesduringthereset
of the FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmedinserialusingtheSerialData(SD)input(seeTable1).FS2 FS0/
SD, and FS1/SEN function the same way in both IDT Standard and FWFT
modes.
The FIFO memory of these devices undergoes a Retransmit by taking its
associatedRetransmit (RT)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializesthereadpointerofFIFOtothefirstmemorylocation.
TheRTMpinmustbeHIGHduringthetimeofRetransmit.Notethatthe RT
inputismuxedwiththePRSinput,thestateoftheRTMpindeterminingwhether
thispinperformsaRetransmitoraPartialReset.SeeFigure19forRetransmit
(Standard IDT mode) and figure 20 for Retransmit (FWFT mode) timing
diagrams.
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
10
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
TABLE 1 — FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
H
H
H
L
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
H
L
L
L
↑
↑
↑
↑
↑
↑
↑
↑
64
16
8
256
1,024
SerialprogrammingviaSD
(2,4)
ParallelprogrammingviaPortA
IP Mode(3,4)
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
— PRESET VALUES
theflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisters ParityisselectedthendatalineA8willbecomeavalidbit.IfInterspersedParity
withoneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbe isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel
HIGHorLOWduringareset. Forexample,toloadthepresetvalueof64into programmingcanbedone.
X and Y, FS0, FS1 and FS2 must be HIGH when RS1 returns HIGH. For
the relevantpresetvalue loadingtimingdiagram, see Figure 3.
— SERIAL LOAD
ToprogramtheXandYregistersserially,initiateaResetwithFS2LOW,
FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1.
— PARALLEL LOAD FROM PORT A
ToprogramtheXandYregistersfromPortA,performaResetwithFS2 After this reset is complete, the X and Y register values are loaded bit-wise
HIGHorLOWandFS0andFS1LOWduringtheLOW-to-HIGHtransitionof throughtheFS0/SDinputoneachLOW-to-HIGHtransitionofCLKAthatthe
RS1. ThestateofFS2atthispointofresetwilldeterminewhethertheparallel FS1/SENinputisLOW.Thereare22-,24-or26-bitwritesneededtocomplete
programmingmethodhasIntersp
the programming for the IDT72V3653, IDT72V3663 or the IDT72V3673,
arityorNon-InterspersedParity.RefertoTable1forFlagProgramming respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue
FlagOffsetsetup.Itisimportanttonotethatonceparallelprogramminghasbeen canbeprogrammedfrom1to2,044(IDT72V3653),1to4,092(IDT72V3663)
selectedduringaMasterResetbyholdingbothFS0&FS1LOW,theseinputs or 1 to 8,188 (IDT72V3673).
must remain LOW during all subsequent FIFO operation. They can only be
toggledHIGHwhenfutureMasterResetsareperformedandotherprogram- Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/
mingmethodsaredesired. IRissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded
Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredata toallownormalFIFOoperation.
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
inRAM. ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X. On
See Figure 6, SerialProgrammingofthe Almost-FullFlagandAlmost-
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed FIFO WRITE/READ OPERATION
timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
bytheOffsetregistersare(A10-A0),(A11-A0),or(A12-A0)fortheIDT72V3653, (CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesareintheHigh-
IDT72V3663,orIDT72V3673,respectively.ForInterspersedParitymodethe impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
PortAdatainputsusedbytheOffsetregistersare(A11-A9,A7-A0),(A12-A9, activeoutputs whenbothCSAandW/RAareLOW.
A7-A0),or(A13-A9,A7-A0)fortheIDT72V3653,IDT72V3663,orIDT72V3673,
DataisloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGH
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof transitionofCLKAwhenCSA is LOW, W/RAis HIGH, ENAis HIGH, MBAis
thebinarynumberineachcase. Validprogrammingvaluesfortheregisters LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
rangefrom1to2,044fortheIDT72V3653;1to4,092fortheIDT72V3663;and of any concurrent reads on Port B.
1to8,188fortheIDT72V3673. Afteralltheoffsetregistersareprogrammed
fromPortA,theFIFObegins normaloperation.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read
select(W/RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB). TheB0-B35
INTERSPERSED PARITY
InterspersedParityis selectedduringaMasterResetoftheFIFO.Refer lines are in the high-impedance state when either CSB is HIGH or W/RB is
toTable1fortheset-upconfigurationofInterspersedParity.TheInterspersed LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is
Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword HIGH.
loaded into the parallel port (A0-An) during programming of the flag offset
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
values.IfInterspersedParityisselectedthenduringparallelprogrammingof transitionofCLKBwhenCSB is LOW, W/RBis HIGH, ENBis HIGH, MBBis
11
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
Port Functions
X
X
X
X
X
↑
None
H
L
X
None
L
H
H
L
Input
FIFOWrite
L
H
H
H
↑
Input
Mail1Write
L
L
L
L
X
↑
Output
None
L
L
H
L
Output
None
None
L
L
L
H
X
↑
Output
L
L
H
H
Output
Mail2 Read (Set MBF2 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
High-Impedance
Input
Port Functions
X
X
X
X
X
↑
None
L
L
X
None
L
L
H
L
Input
None
Mail2Write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
None
L
H
H
L
Output
FIFO read
L
H
L
H
X
↑
Output
None
L
H
H
H
Output
Mail1 Read (Set MBF1 HIGH)
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
(1,2)
Number of Words in FIFO
IDT72V3653(3)
IDT72V3663(3)
IDT72V3673(3)
EF/OR
AE
AF
H
H
H
L
FF/IR
H
0
1 to X
0
1 to X
0
1 to X
L
H
H
H
H
L
L
H
(X+1)to[2,048-(Y+1)]
(2,048-Y)to2,047
2,048
(X+1)to[4,096-(Y+1)]
(4,096-Y)to4,095
4,096
(X+1)to[8,192-(Y+1)]
(8,192-Y)to8,191
8,192
H
H
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the memory count.
3. X is the Almost-Empty offset used by AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are
independentofanyconcurrentwrites onPortA.
WhenoperatingtheFIFOinIDTStandardmode,regardlessofwhether
theEmptyFlagisLOWorHIGH,dataresidingintheFIFO’smemoryarrayis
The setupandholdtime constraints tothe portclocks forthe portChip clocked to the output register only when a read is selected using the port’s
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations Chip Select, Write/Read select, Enable, and Mailbox select. Port A Write
andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable timing diagram can be found in Figure 7. Relevant Port B Read timing
isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay diagrams together with Bus-Matching and Endian select can be found in
changestatesduringthesetupandholdtimewindowofthecycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagis
Figure 8, 9 and 10.
LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregister SYNCHRONIZED FIFO FLAGS
bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop
HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
arrayisclockedtotheoutputregisteronlywhenareadisselectedusingthe ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone
port’sChipSelect,Write/Readselect,Enable,andMailboxselect.
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
12
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread. Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 13 and 14).
synchronizedtoCLKB. Table4 shows therelationshipofeachportflagtothe
numberofwords storedinmemory.
EMPTY/OUTPUTREADYFLAGS(EF/OR)
These are dual purpose flags. In the FWFT mode, the Output Ready
(OR)functionis selected. WhentheOutput-Readyflagis HIGH,newdatais
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
IntheIDTStandardmode,theEmptyFlag(EF)functionisselected. When
theEmptyFlagisHIGH,dataisavailableintheFIFO’smemoryforreadingto
the output register. When the Empty Flag is LOW, the previous data word is
presentinthe FIFOoutputregisterandattemptedFIFOreads are ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock
thatreads data fromits array(CLKB). Forboththe FWFTandIDTStandard
modes,theFIFOreadpointerisincrementedeachtimeanewwordisclocked
to its output register. The state machine that controls an Output Ready flag
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe
FIFOmemorystatusisempty,empty+1,orempty+2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizingclock.Therefore,anOutputReadyflagisLOWifawordinmemory
isthenextdatatobesenttotheFlFOoutputregisterandthreecyclesoftheport
ClockthatreadsdatafromtheFIFOhavenotelapsedsincethetimetheword
waswritten. TheOutputReadyflagoftheFIFOremainsLOWuntilthethirdLOW-
to-HIGHtransitionofthesynchronizingclockoccurs,simultaneouslyforcingthe
OutputReadyflagHIGHandshiftingthewordtotheFIFOoutputregister.
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
ifawordinmemoryis thenextdatatobesenttotheFlFOoutputregisterand
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
thetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOWuntil
thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing
the Empty Flag HIGH; only then can data be read.
ALMOST-EMPTYFLAG(AE)
The Almost-Emptyflagofa FIFOis synchronizedtothe portclockthat
readsdatafromitsarray(CLKB). ThestatemachinethatcontrolsanAlmost-
Emptyflagmonitorsawritepointerandreadpointercomparatorthatindicates
whentheFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-
empty+2. TheAlmost-EmptystateisdefinedbythecontentsofregisterX. These
registersareloadedwithpresetvaluesduringaFIFOreset,programmedfrom
PortA,orprogrammedserially(seeAlmost-EmptyflagandAlmost-Fullflag
offset programming section). An Almost-Empty flag is LOW when its FIFO
contains Xorless words andis HIGHwhenits FIFOcontains (X+1)ormore
words. NotethatadatawordpresentintheFIFOoutputregisterhasbeenread
frommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing
clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
leveloffill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormore
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transitionofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchro-
nizationcycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFO
to(X+1)words. Otherwise,thesubsequentsynchronizingclockcyclemaybe
thefirstsynchronizationcycle.(SeeFigure15).
ALMOST-FULL FLAG (AF)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray. ThestatemachinethatcontrolsanAlmost-Fullflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. TheAlmost-Fullstate
isdefinedbythecontentsofregisterY.Theseregistersareloadedwithpreset
values during a FlFO reset or, programmed from Port A, or programmed
serially (see Almost-Empty flag and Almost-Full flag offset programming
section). AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOis
greaterthanorequalto(2,048-Y),(4,096-Y),or(8,192-Y)fortheIDT72V3653,
IDT72V3663,orIDT72V3673respectively. AnAlmost-FullflagisHIGHwhen
the number of words in its FIFO is less than or equal to [2,048-(Y+1)],
[4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3653, IDT72V3663, or
IDT72V3673respectively. NotethatadatawordpresentintheFIFOoutput
registerhas beenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are requiredaftera FIFOreadforits Almost-Fullflagtoreflectthe newlevel
offill.Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A
LOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthe
firstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)].
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle (see Figure 16).
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (FF/IR)
Thisisadualpurposeflag. InFWFTmode,theInputReady(IR)function
isselected. InIDTStandardmode,theFullFlag(FF) functionisselected. For
bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation
is free in the FIFO to receive new data. No memory locations are free when
theFull/InputReadyflagisLOWandattemptedwritestotheFIFOareignored.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat
writesdatatoitsarray(CLKA). ForbothFWFTandIDTStandardmodes,each
timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer
comparatorthatindicateswhentheFlFO memorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe
nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
13
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
MAILBOX REGISTERS
onmailboxdata. Formailregisterandmailregisterflagtimingdiagrams,see
Two36-bitbypassregistersareontheIDT72V3653/72V3663/72V3673 Figure 17 and 18.
topasscommandandcontrolinformationbetweenPortAandPortBwithout
puttingitinqueue.TheMailboxselect(MBA,MBB)inputschoosebetweena BUS SIZING
mailregisterandaFIFOforaportdatatransferoperation.Theusablewidth
The PortBbus canbe configuredina 36-bitlongword, 18-bitword, or
ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB. 9-bitbyteformatfordatareadfromtheFIFO. ThelevelsappliedtothePortB
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen BusSizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbus
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the size. TheselevelsshouldbestaticthroughoutFIFOoperation. Bothbussize
selectedPortBbussizeis36bits,theusablewidthoftheMail1Registeremploys selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input
datalinesA0-A35.IftheselectedPortBbussizeis18bits,thentheusablewidth Ready flag is set HIGH, as shown in Figure 2.
oftheMail1RegisteremploysdatalinesA0-A17.(Inthiscase,A18-A35are
TwodifferentmethodsforsequencingdatatransferareavailableforPort
don’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusablewidth Bwhenthe bus size selectionis eitherbyte-orword-size. Theyare referred
oftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’t toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant
careinputs.)
bytefirst). ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2 to-HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduring
RegisterwhenaPortBwriteis selectedbyCSB,W/RB,andENBwithMBB FIFOoperation. BEis a don’tcare inputwhenthe bus size selectedforPort
HIGH.IftheselectedPortBbus sizeis 36bits,theusablewidthoftheMail2 Bislongword. TheendianmethodisimplementedatthecompletionofReset,
employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,thenthe by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
usablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthiscase,B18-
Only 36-bit long word data is written to or read from the FIFO memory on
B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusable the IDT72V3653/72V3663/72V3673. Bus-matching operations are done after
widthoftheMail2RegisteremploysdatalinesB0-B8.(Inthiscase,B9-B35are data is read from the FIFO RAM. These bus-matching operations are not
don’tcareinputs.)
available when transferring data via mailbox registers. Furthermore, both the
Writing data to a mail register sets its corresponding flag (MBF1 or word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused
MBF2)LOW.Attemptedwritestoamailregisterareignoredwhilethemailflag for mail register operations. In this case, only those byte lanes belonging to the
isLOW.
selected word- or byte-size bus can carry mailbox data. The remaining data
Whendataoutputsofaportareactive,thedataonthebuscomesfrom outputswillbeindeterminate. Theremainingdatainputswillbedon’tcareinputs.
theFIFOoutputregisterwhentheportMailboxselectinputisLOWandfrom For example, when a word-size bus is selected, then mailbox data can be
themailregisterwhentheportMailboxselectinputisHIGH.
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH selected, then mailbox data can be transmitted only between A0-A8 and B0-
transitiononCLKBwhenaPortBreadis selectedbyCSB,W/RB,andENB B8. (See Figures 17 and 18).
withMBBHIGH. Fora 36-bitbus size, 36bits ofmailboxdata are placedon
B0-B35.Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17. BUS-MATCHING FIFO READS
(Inthiscase,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailbox
data are placedonB0-B8. (Inthis case, B9-B35are indeterminate.)
Data is read from the FIFO RAM in 36-bit long word increments. If a long
wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH output register. If byte or word size is implemented on Port B, only the first one
transitiononCLKAwhenaPortAreadis selectedbyCSA,W/RA,andENA or two bytes appear on the selected portion of the FIFO output register, with the
withMBAHIGH.
rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
Fora36-bitbussize,36bitsofmailboxdataareplacedonA0-A35.For reads output the rest of the long word to the FIFO output register in the order
an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase, shown by Figure 2.
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placedonA0-A8. (Inthis case, A9-A35are indeterminate.)
WhenreadingdatafromFIFOinbyteorwordformat,theunusedB0-B35
outputsareindeterminate.
Thedatainamailregisterremainsintactafteritisreadandchangesonly
whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect
14
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
BYTE ORDER ON PORT A:
A35 ⎯ A27
A26 ⎯ A18
A17 ⎯ A9
A8 ⎯ A0
Write to FIFO
A
B
C
D
B35 ⎯ B27
B26 ⎯±B18
B
B17 ⎯±B9
B8 ⎯±B0
BYTE ORDER ON PORT B:
BE BM SIZE
D
A
C
Read from FIFO
X
L
X
(a) LONG WORD SIZE
B35 ⎯ B27
B35 ⎯ B27
B26 ⎯ B18
B26 ⎯ B18
B17 ⎯ B9
B8 ⎯ B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
A
B
H
H
L
B17 ⎯ B9
B8 ⎯ B0
C
D
(b) WORD SIZE ⎯±BIG-ENDIAN
B35 ⎯±B27
B35 ⎯ B27
B26 ⎯ B18
B17 ⎯ B9
B8 ⎯ B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
C
D
L
H
L
B26 ⎯ B18
B17 ⎯ B9
B8 ⎯ B0
A
B
(c) WORD SIZE ⎯±LITTLE-ENDIAN
B35 ⎯ B27
B35 ⎯ B27
B35 ⎯ B27
B35 ⎯ B27
B26 ⎯ B18
B26 ⎯ B18
B26 ⎯ B18
B26 ⎯ B18
B17 ⎯ B9
B17 ⎯ B9
B17 ⎯ B9
B17 ⎯ B9
B8 ⎯ B0
BE BM SIZE
A
1st: Read from FIFO
2nd: Read from FIFO
H
H
H
B8 ⎯ B0
B
B8 ⎯ B0
C
3rd: Read from FIFO
4th: Read from FIFO
B8 ⎯ B0
D
(d) BYTE SIZE ⎯±BIG-ENDIAN
B35 ⎯ B27 B26 ⎯ B18
B35 ⎯ B27 B26 ⎯ B18
B35 ⎯ B27 B26 ⎯ B18
B35 ⎯ B27 B26 ⎯ B18
B17 ⎯ B9
B8 ⎯ B0
BE BM SIZE
D
1st: Read from FIFO
L
H
H
B17 ⎯ B9
B17 ⎯ B9
B8 ⎯ B0
C
2nd: Read from FIFO
3rd: Read from FIFO
B8 ⎯ B0
B
B17 ⎯ B9
B8 ⎯ B0
A
4th: Read from FIFO
4662 drw 04
(e) BYTE SIZE
⎯
LITTLE-ENDIAN
Figure 2. Bus sizing
15
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
t
RSTS
tRSTH
RS1, RS2
BE/FWFT
t
BEH
t
BES
tFWS
BE
0,1
FWFT
t
FSH
t
FSS
FS2,
FS1,FS0
t
WFF
t
WFF
FF/IR
EF/OR
AE
(2)
tREF
t
t
RSF
RSF
AF
t
RSF
MBF1,
MBF2
RTM
LOW
4662 drw 05
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
CLKA
CLKB
t
RSTS
tRSTH
PRS
t
WFF
t
WFF
FF/IR
(2)
REF
t
EF/OR
AE
t
RSF
t
RSF
AF
t
RSF
MBF1,
MBF2
RTM LOW
4662 drw 06
NOTES:
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
16
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
CLKA
2
1
4
RS1
t
FSS
t
FSH
FS2
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FF/IR
tENS2
tENH
ENA
tDH
tDS
A0-A35
4662 drw 07
AE Offset
First Word to FIFO1
AF Offset
(X)
(Y)
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes)
CLKA
RS1
FS2
4
t
t
FSS
FSS
t
FSH
t
WFF
FF/IR
t
SENS
t
SENH
SDH
t
SENS
t
SENH
SDH
tSPH
FS1/SEN
tSDS
t
t
tSDS
FS0/SD(2)
4662 drw 08
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
17
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
FF/IRA HIGH
tENS1
tENH
CSA
tENS1
t
ENH
ENH
ENH
W/RA
t
ENS2
t
MBA
ENA
tENS2
tENH
t
tENS2
tENS2
tENH
tDS
tDH
W1(1)
W2(1)
No Operation
A0-A35
4662 drw09
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EF/OR HIGH
CSB
W/RB
MBB
ENB
t
ENS2
tENH
t
ENH
t
ENS2
tENH
t
ENS2
No Operation
W2(1)
tDIS
t
MDV
tA
t
A
t
EN
Previous Data
W1 (1)
W2 (1)
B0-B35
(Standard Mode)
t
MDV
tDIS
OR
t
A
t
A
t
EN
B0-B35
W1(1)
W3 (1)
(FWFT Mode)
4662 drw 10
NOTE:
1. Data read from the FIFO
DATA SIZE TABLE FOR FIFO LONG-WORD READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
DATA READ FROM FIFO
(SELECT AT RESET)
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
18
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
CLKB
FF/OR HIGH
CSB
W/RB
MBB
tENS2
tENH
ENB
No Operation
Read 2
t
DIS
t
MDV
t
A
t
A
B0-B17
t
EN
(Standard Mode)
Previous Data
Read 1
Read 2
t
DIS
OR
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
4662 drw 11
NOTE:
1. Unused word B18-B35 are indeterminate.
DATA SIZE TABLE FOR WORD READS
SIZE MODE (1)
DATA WRITTEN TO FIFO 1
READ
NO.
DATA READ FROM FIFO
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
19
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
CLKB
EF/OR HIGH
CSB
W/RB
MBB
t
ENS2
t
ENH
A
ENB
No Operation
t
MDV
tDIS
t
A
tA
t
t
A
t
EN
B0-B8
(Standard Mode)
Read 1
Read 4
Read 5
Previous Data
Read 2
Read 3
tDIS
OR
tA
t
MDV
tA
t
A
tA
t
EN
B0-B8
(FWFT Mode)
Read 1
Read 2
Read 3
Read 4
4662 drw 12
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.
DATA SIZE TABLE FOR BYTE READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
READ
DATA READ FROM FIFO
B8-B0
NO.
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
H
A
B
C
D
1
2
3
4
D
C
B
A
H
L
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
20
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
LOW
HIGH
CSA
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
t
IR HIGH
A0-A35
tDS
tDH
W1
t
tSKEW1
CLKtCLKL
(1)
tCLKH
CLKB
1
2
3
t
REF
tREF
FIFO Empty
LOW
OR
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
tA
Old Data in FIFO Output Register
W1
B0-B35
4662 drw13
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
21
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
W/RA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
FF HIGH
tDS
tDH
A0-A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
t
REF
t
REF
EF
FIFO Empty
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0-B35
NOTES:
W1
4662 drw14
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)
22
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENH
tENS2
ENB
OR HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
CLKA
tCLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
t
WFF
t
WFF
IR
FIFO Full
LOW
CSA
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
To FIFO
4662 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)
23
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
EF HIGH
tA
Previous Word in FIFO Output Register
SKEW1
Next Word From FIFO
B0-B35
(1)
t
tCLK
tCLKH
tCLKL
CLKA
1
2
WFF
ENH
WFF
t
t
FIFO Full
LOW
FF
CSA
HIGH
W/RA
t
t
ENS2
ENS2
MBA
t
tENH
ENA
tDS
tDH
A0-A35
4662 drw16
To FIFO
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
CLKB
AE
(1)
tSKEW2
1
2
t
PAE
t
PAE
X Words in FIFO
(X+1) Words in FIFO
ENS2
t
tENH
ENB
4662 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
24
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
CLKA
1
2
(1)
tENH
tENS2
tSKEW2
ENA
AF
t
PAF
tPAF
(D-Y) Words in FIFO
[D-(Y+1)] Words in FIFO
CLKB
tENH
tENS2
ENB
4662 drw 18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3653, 4,096 for the IDT72V3663, 8,192 for the IDT72V3673.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
CLKA
tENH
tENS1
CSA
W/RA
MBA
t
ENH
t
ENS1
t
t
ENS2
tENH
ENS2
tENH
ENA
tDH
tDS
W1
A0-A35
CLKB
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
MDV
tEN
tDIS
t
PMR
B0-B35
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
4662 drw19
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
25
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
CLKB
tENH
tENS1
CSB
tENH
tENS1
W/RB
t
ENH
t
ENS2
ENS2
MBB
ENB
tENH
t
tDH
tDS
W1
B0-B35
CLKA
MBF2
t
PMF
t
PMF
CSA
W/RA
MBA
ENA
tENH
tENS2
t
EN
tPMR
t
DIS
t
MDV
W1 (Remains valid in Mail2 Register after read)
FIFO Output Register
A0-A35
4662 drw20
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid
data (A9-A35 will be indeterminate).
Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
26
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
CLKA
4
1
2
3
CLKB
2
3
4
1
tENS2
tENH
ENB
tRSTH
tRSTS
tRTMS
RT
tRTMH
RTM
(2)
tREF
(2)
tREF
EF
B0-Bn
NOTE:
tA
Wx
W1
4662 drw 21
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be LOW throughout the Retransmit setup procedure.
D = 2,048, 4,096 and 8,192 for the IDT72V3653. 72V3663 and 72V3673 respectively.
Figure 19. Retransmit Timing (IDT Standard Mode)
CLKA
CLKB
4
1
2
3
2
3
4
1
ENB
RT
LOW
t
RSTH
t
RSTS
t
RTMS
t
RTMH
RTM
OR
(2)
REF
(2)
REF
t
t
tA
B0-Bn
Wx
W1
4662 drw22
NOTE:
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after OR returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 2,048, 4,096 and 8,192 for the IDT72V3653. 72V3663 and 72V3673 respectively.
Figure 20. Retransmit Timing (FWFT Mode)
27
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
TRANSFER CLOCK
CLKB CLKA
WRITE
READ
READ CLOCK (CLKB)
CHIP SELECT (CSB)
EMPTY FLAG/
OUTPUT READY (EF/OR)
WRITE CLOCK (CLKA)
CHIP SELECT (CSA)
EF/OR
ENA
V
CC
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
FF/IR
ENB
READ ENABLE (ENB)
V
CC
CSB
CSA
READ SELECT (W/RB)
IDT
IDT
72V3653
72V3663
72V3673
72V3653
72V3663
72V3673
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A
0
-A35
n
B
0
-B35
B0-B35
n
FULL FLAG/
INPUT READY (FF/IR)
DATA OUT (Qn)
Qn
Dn
V
CC
V
CC
W/RA
MBA
W/RB
MBB
4662 drw23
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 21. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
28
TM
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3 V
330Ω
From Output
Under Test
30 pF (1)
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
1.5 V
Timing
Input
1.5 V
High-Level
Input
GND
1.5 V
1.5 V
GND
t
S
th
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈±3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈±OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
OL
t
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4662 drw 24
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms.
29
ORDERING INFORMATION
X
XX
X
X
X
XXXXXX
Device Type Power Speed Package
Process/
Temperature
Range
Commercial (0oC to +70oC)
Green
BLANK
G
PF
Thin Quad Flat Pack (TQFP, PK128-1)
Clock Cycle Time (tCLK
)
10
15
Commercial Only
Low Power
Speed in Nanoseconds
L
16,384 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
72V3653
72V3663 32,768 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
72V3673 65,536 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
4662 drw 25
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
06/23/2000
09/27/2001
11/03/2003
02/05/2009
pgs. 1-5, 7-9, 11, 12, 14, 17, 18, 21-26, 28 and 29.
pgs. 5, 6, 7, 8, 9, 12 and 30.
pg. 1.
pgs. 1 and 30.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
30
相关型号:
72V3680L7-5BBGI
FIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144
IDT
72V3680L7-5BBGI8
FIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144
IDT
©2020 ICPDF网 联系我们和版权申明